tree adf2b70d03f36e891b84230e352a5a3fec032d7a
parent 12c69562cff8cc542819c156380b6c116c2ca46e
author IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com> 1711360371 +0100
committer Fabio Baltieri <fabio.baltieri@gmail.com> 1711618932 +0000

boards: stm32h573i_dk: Fix CAN core clock

Set the PLL1_Q divider to 6 give a can core clock of 80MHz to
resolve fdcan_clk reception problem because M_CAN requires that
the host clock "APB1" should be higher or equal to the CAN core
clock "PLL1_Q".

Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com>