diff --git a/drivers/cache/cache_aspeed.c b/drivers/cache/cache_aspeed.c
index e3d8a08..f8522b0 100644
--- a/drivers/cache/cache_aspeed.c
+++ b/drivers/cache/cache_aspeed.c
@@ -35,7 +35,7 @@
 
 #define ICACHE_CLEAN		BIT(2)
 #define DCACHE_CLEAN		BIT(1)
-#define CACHE_EANABLE		BIT(0)
+#define CACHE_ENABLE		BIT(0)
 
 /* cache size = 32B * 128 = 4KB */
 #define CACHE_LINE_SIZE_LOG2	5
@@ -62,7 +62,7 @@
 	syscon_write_reg(dev, CACHE_AREA_CTRL_REG, GENMASK(end_bit, start_bit));
 
 	/* enable cache */
-	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, CACHE_EANABLE);
+	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, CACHE_ENABLE);
 }
 
 /**
@@ -129,13 +129,12 @@
 	syscon_write_reg(dev, CACHE_FUNC_CTRL_REG, 0);
 }
 
-int cache_data_all(int op)
+int cache_data_invd_all(void)
 {
 	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
 	uint32_t ctrl;
 	unsigned int key = 0;
 
-	ARG_UNUSED(op);
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
 	/* enter critical section */
@@ -159,14 +158,12 @@
 	return 0;
 }
 
-int cache_data_range(void *addr, size_t size, int op)
+int cache_data_invd_range(void *addr, size_t size)
 {
 	uint32_t aligned_addr, i, n;
 	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
 	unsigned int key = 0;
 
-	ARG_UNUSED(op);
-
 	if (((uint32_t)addr < CACHED_SRAM_ADDR) ||
 	    ((uint32_t)addr > CACHED_SRAM_END)) {
 		return 0;
@@ -194,14 +191,12 @@
 	return 0;
 }
 
-int cache_instr_all(int op)
+int cache_instr_invd_all(void)
 {
 	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
 	uint32_t ctrl;
 	unsigned int key = 0;
 
-	ARG_UNUSED(op);
-
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
 	/* enter critical section */
@@ -224,14 +219,12 @@
 	return 0;
 }
 
-int cache_instr_range(void *addr, size_t size, int op)
+int cache_instr_invd_range(void *addr, size_t size)
 {
 	uint32_t aligned_addr, i, n;
 	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(syscon));
 	unsigned int key = 0;
 
-	ARG_UNUSED(op);
-
 	if (((uint32_t)addr < CACHED_SRAM_ADDR) ||
 	    ((uint32_t)addr > CACHED_SRAM_END)) {
 		return 0;
@@ -259,6 +252,59 @@
 	return 0;
 }
 
+int cache_data_flush_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return -ENOTSUP;
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return -ENOTSUP;
+}
+
+
 #ifdef CONFIG_DCACHE_LINE_SIZE_DETECT
 size_t cache_data_line_size_get(void)
 {
@@ -267,7 +313,7 @@
 
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
-	return (ctrl & CACHE_EANABLE) ? CACHE_LINE_SIZE : 0;
+	return (ctrl & CACHE_ENABLE) ? CACHE_LINE_SIZE : 0;
 }
 #endif /* CONFIG_DCACHE_LINE_SIZE_DETECT */
 
@@ -279,6 +325,6 @@
 
 	syscon_read_reg(dev, CACHE_FUNC_CTRL_REG, &ctrl);
 
-	return (ctrl & CACHE_EANABLE) ? CACHE_LINE_SIZE : 0;
+	return (ctrl & CCHE_EANABLE) ? CACHE_LINE_SIZE : 0;
 }
 #endif /* CONFIG_ICACHE_LINE_SIZE_DETECT */