)]}'
{
  "commit": "76d8be4fe687277d442a83cf4ea7d4a55e35d67a",
  "tree": "bcae3d17aed4359038fbfa8d1c56ac39cfbe3cf9",
  "parents": [
    "9984adf24e115da84763178a7fe504006b341418"
  ],
  "author": {
    "name": "Erwan Gouriou",
    "email": "erwan.gouriou@st.com",
    "time": "Mon May 27 16:53:40 2024 +0200"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Thu Jun 13 08:05:04 2024 -0400"
  },
  "message": "soc: stm32: stm32wb: Enable ART accelerations\n\nEnable instruction and data cache as well as prefetch.\n\nSigned-off-by: Erwan Gouriou \u003cerwan.gouriou@st.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "01364c241e109c880f42c5ed8e8fc751b64b76fa",
      "old_mode": 33188,
      "old_path": "soc/st/stm32/stm32wbx/soc.c",
      "new_id": "02ce55e433d65ed657cbcb1fc1a49e82b63211a5",
      "new_mode": 33188,
      "new_path": "soc/st/stm32/stm32wbx/soc.c"
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}