)]}'
{
  "commit": "7732e6672345de6000d9d64645706965e2d3e604",
  "tree": "45af88724d4ab2ea9e05db1d21244a57ee164274",
  "parents": [
    "a6a11cc57d86d577be16a1f2738e9928e09f674a"
  ],
  "author": {
    "name": "Jimmy Zheng",
    "email": "jimmyzhe@andestech.com",
    "time": "Thu Jul 24 22:01:26 2025 +0800"
  },
  "committer": {
    "name": "Chris Friedt",
    "email": "chrisfriedt@gmail.com",
    "time": "Mon Oct 13 11:26:28 2025 -0400"
  },
  "message": "arch: riscv: custom: add OpenISA RI5CY and Zero-RISCY CSR support\n\nUpdate OpenISA RI5CY and Zero-RISCY CSR handling to use RISC-V custom\nCSR common code. Move these stuff to \u0027arch/riscv/custom/openisa\u0027:\n\n1. Rename \u0027soc_ri5cy.h\u0027 to \u0027ri5cy_csr.h\u0027 for CSR definitions.\n2. Rename \u0027soc_zero_riscy.h\u0027 to \u0027zero_riscy_csr.h\u0027 for CSR definitions.\n3. Move CSR context to common macro \u0027__custom_csr_save/restore_context\u0027.\n4. Move compiler option \u0027-march\u003drv32imcxpulpv2\u0027 to common code.\n\nSigned-off-by: Jimmy Zheng \u003cjimmyzhe@andestech.com\u003e\n",
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