tree 0a1443e9210410392228fac87dca3d347ff9b40c
parent d2ac7b4835ea3f4a32bed74db191a51dfafcf4d2
author Carlo Caione <ccaione@baylibre.com> 1656592852 +0200
committer Carles Cufí <carles.cufi@nordicsemi.no> 1656951490 +0200

riscv: Introduce RISCV_ALWAYS_SWITCH_THROUGH_ECALL

Some early RISC-V SoCs have a problem when an `mret` instruction is used
outside a trap handler.

After the latest Zephyr RISC-V huge rework, the arch_switch code is
indeed calling `mret` when not in handler mode, breaking some early
RISC-V platforms.

Optionally restore the old behavior by adding a new
CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL symbol.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Signed-off-by: Carlo Caione <ccaione@baylibre.com>