)]}'
{
  "commit": "7a510245c96db4e6af126bb519ca1f76f87b274a",
  "tree": "ee0a9333d9c41c93754f1b3af54a7402f1f4dcab",
  "parents": [
    "59aae63f519794c3d5e0aba2ef9e65c0d2d424a7"
  ],
  "author": {
    "name": "Julien Massot",
    "email": "julien.massot@iot.bzh",
    "time": "Thu Jan 27 10:12:55 2022 +0100"
  },
  "committer": {
    "name": "Carles Cufí",
    "email": "carles.cufi@nordicsemi.no",
    "time": "Fri Mar 11 10:59:48 2022 +0100"
  },
  "message": "arch: arm: cortex_a_r: Add support to start in HYP mode\n\nThe ARMv8-R processors always boot into Hyp mode (EL2)\n\nTo enter EL1:\nProgram the HACTLR register because it defaults\nto only allowing EL2 accesses. HACTLR controls\nwhether EL1 can access memory region registers and CPUACTLR.\nProgram the SPSR before entering EL1.\nOther registers default to allowing accesses at EL1 from reset.\nSet VBAR to the correct location for the vector table.\nSet ELR to point to the entry point of the EL1 code and call ERET.\n\nSigned-off-by: Julien Massot \u003cjulien.massot@iot.bzh\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a86942b94b66cea992b076562b90e626a37d564a",
      "old_mode": 33188,
      "old_path": "arch/arm/core/aarch32/cortex_a_r/reset.S",
      "new_id": "7cd4f2dd26970b8773706117e5df4ac8acfdf6f9",
      "new_mode": 33188,
      "new_path": "arch/arm/core/aarch32/cortex_a_r/reset.S"
    },
    {
      "type": "modify",
      "old_id": "3354ad678c027b16f79440b6162f347870327e4e",
      "old_mode": 33188,
      "old_path": "include/arch/arm/aarch32/cortex_a_r/cpu.h",
      "new_id": "04bdb723ddcab39dd69181e003c6d0c751b76117",
      "new_mode": 33188,
      "new_path": "include/arch/arm/aarch32/cortex_a_r/cpu.h"
    }
  ]
}