/*
 * Copyright (c) 2021, TOKITA Hiroshi <tokita.hiroshi@gmail.com>
 * SPDX-License-Identifier: Apache-2.0
 */

#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_
#define ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_

/* Clock divider values */
#define RISCV_MACHINE_TIMER_DIVIDER_1          0
#define RISCV_MACHINE_TIMER_DIVIDER_2          1
#define RISCV_MACHINE_TIMER_DIVIDER_4          2
#define RISCV_MACHINE_TIMER_DIVIDER_8          3
#define RISCV_MACHINE_TIMER_DIVIDER_16         4
#define RISCV_MACHINE_TIMER_DIVIDER_32         5
#define RISCV_MACHINE_TIMER_DIVIDER_64         6
#define RISCV_MACHINE_TIMER_DIVIDER_128        7
#define RISCV_MACHINE_TIMER_DIVIDER_256        8
#define RISCV_MACHINE_TIMER_DIVIDER_512        9
#define RISCV_MACHINE_TIMER_DIVIDER_1024      10

#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TIMER_RISCV_MACHINE_TIMER_H_ */