/*
 * Copyright (c) 2024 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	soc {
		reserved-memory {
			#address-cells = <1>;
			#size-cells = <1>;
			cpuflpr_code_partition: image@165000 {
				/* FLPR core code partition */
				reg = <0x165000 DT_SIZE_K(96)>;
			};
		};

		cpuflpr_sram_code_data: memory@20028000 {
			compatible = "mmio-sram";
			reg = <0x20028000 DT_SIZE_K(96)>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0x0 0x20028000 0x18000>;
		};
	};
};

&uart30 {
	status = "reserved";
};

&cpuapp_sram {
	reg = <0x20000000 DT_SIZE_K(160)>;
	ranges = <0x0 0x20000000 0x28000>;
};

&cpuflpr_vpr {
	execution-memory = <&cpuflpr_sram_code_data>;
	source-memory = <&cpuflpr_code_partition>;
};