# MIMXRT595-EVK board

# Copyright 2022-2023, NXP
# SPDX-License-Identifier: Apache-2.0

if BOARD_MIMXRT595_EVK

config BOARD
	default "mimxrt595_evk_cm33"

config FLASH_MCUX_FLEXSPI_MX25UM51345G
	default y if FLASH

choice FLASH_MCUX_FLEXSPI_XIP_MEM_TARGET
	default FLASH_MCUX_FLEXSPI_XIP_MEM_SRAM
endchoice

config FXOS8700_DRDY_INT1
	default y
	depends on FXOS8700_TRIGGER

if DMA_MCUX_LPC

# Memory from the heap pool is used to allocate DMA descriptors for
# channels that use multiple blocks for a DMA transfer.
# Adjust HEAP_MEM_POOL_SIZE in case you need more memory.
config HEAP_MEM_POOL_SIZE
	default 4096

endif # DMA_MCUX_LPC

if DISPLAY

# Enable MIPI display driver

config MIPI_DSI
	default y

# Use external framebuffer memory for the LCDIF framebuffer
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
	default y
# Use FlexSPI2 base address for framebuffer (pSRAM is present on this bus)
config MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
	default 0x38000000
# M33 core and LCDIF both access FlexSPI2 through the same cache,
# so coherency does not need to be managed.
config MCUX_DCNANO_LCDIF_MAINTAIN_CACHE
	depends on !MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM

endif # DISPLAY

config KSCAN
	default y if LVGL

if LVGL

config LV_Z_POINTER_KSCAN
	default y

config LV_Z_VDB_SIZE
	default 16

config LV_Z_DPI
	default 128

choice LV_COLOR_DEPTH
	default LV_COLOR_DEPTH_16
endchoice

endif # LVGL

if PM
# Turn on Device Level Power Management as we wish
# to reconfigure the FlexSPI pins for power savings
# when transitioning the SoC to Deep Low Power modes.
config PM_DEVICE
	default y
endif # PM

endif # BOARD_MIMXRT595_EVK