blob: a935b37b0dfd35c3d4123d32c734437d25958e67 [file] [log] [blame]
/*
* Copyright (c) 2025 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/mp13/stm32mp13.dtsi>
#include <zephyr/dt-bindings/video/video-interfaces.h>
/ {
soc {
compatible = "st,stm32mp135", "st,stm32mp13", "simple-bus";
dcmipp: dcmipp@5a000000 {
compatible = "st,stm32mp13-dcmipp", "st,stm32-dcmipp";
reg = <0x5a000000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
clocks = <&rcc STM32_CLOCK(APB4, 1)>,
<&rcc STM32_SRC_PLL2_Q DCMIPP_SEL(1)>;
clock-names = "dcmipp", "dcmipp-ker";
resets = <&rctl STM32_RESET(APB4, 1)>;
status = "disabled";
pipe_dump: pipe {};
port {
endpoint {
remote-endpoint-label = "";
bus-type = <VIDEO_BUS_TYPE_PARALLEL>;
};
};
};
ltdc: display-controller@5a001000 {
compatible = "st,stm32-ltdc";
reg = <0x5a001000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
<GIC_SPI 89 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
interrupt-names = "ltdc", "ltdc_er";
clocks = <&rcc STM32_CLOCK(APB4_NS, 0)>;
resets = <&rctl STM32_RESET(APB4, 0)>;
status = "disabled";
};
};
};