)]}'
{
  "commit": "7f577b2d5cce16a44815310cde6f3080e047d9dd",
  "tree": "799b1395cc4e7d6dcd8df541565324e735269662",
  "parents": [
    "c01625210802ad319aeee70830dadff9193fe7f3"
  ],
  "author": {
    "name": "Benjamin Walsh",
    "email": "benjamin.walsh@windriver.com",
    "time": "Tue Dec 13 12:07:49 2016 -0500"
  },
  "committer": {
    "name": "Maureen Helm",
    "email": "maureen.helm@nxp.com",
    "time": "Thu Dec 15 15:57:10 2016 +0000"
  },
  "message": "arm: better handling of IRQ priorities reserved by the kernel\n\nThere are now three flags that decide how many priorities are reserved\nby the kernel, each one requiring one priority level: Zero Latency\nInterrupts, BASEPRI locking (for SVC usage) and faults that are not at\npriority -1, so that taking them in an ISR actually triggers the fault\nsynchronously.\n\nChange-Id: I7f4d760c9110051aeb82dcfd8cd68026a9b74b54\nSigned-off-by: Benjamin Walsh \u003cbenjamin.walsh@windriver.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1cc0a132de9731109f9914a60ef1eff432bb18dd",
      "old_mode": 33188,
      "old_path": "include/arch/arm/cortex_m/nvic.h",
      "new_id": "4deaf8e420e32fdc14828c26d0e56cca3df43a91",
      "new_mode": 33188,
      "new_path": "include/arch/arm/cortex_m/nvic.h"
    }
  ]
}