)]}'
{
  "commit": "87d1f0682b36f844e7002da9a71133f75c8e7bf4",
  "tree": "d24111e18912b25c9273b3bea1ddddafbb3cf0c1",
  "parents": [
    "94851726775a534a0aa9283ccbbf8d24973e8f1c"
  ],
  "author": {
    "name": "Andrew Boie",
    "email": "andrew.p.boie@intel.com",
    "time": "Fri May 03 14:02:51 2019 -0700"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Fri May 03 22:38:22 2019 -0400"
  },
  "message": "boards: qemu_x86: properly enable XIP\n\nThe \u0027#if XIP\u0027 in the DTS file never worked properly,\ncausing the QEMU build to think it has much more RAM\nthen it actually has. If RAM overflowed, this would not\nbe caught by the build, instead there would be strange\ncrashes when the data copy takes place.\n\nThe QEMU targets themselves are not XIP, everything\nis actually RAM, but the first 4 megabytes are\nconsidered to be a memory-mapped flash region. This\nis done to ensure that the XIP data copying infrastructure\ndoesn\u0027t bit-rot on x86. We are at the point where\na lot of things depend on this, so just select it in\nthe board Kconfig instead of enabling in the\ndefconfigs.\n\nFixes: #15835\n\nSigned-off-by: Andrew Boie \u003candrew.p.boie@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "736a402406109960975b43c21e8ea24fd549b384",
      "old_mode": 33188,
      "old_path": "boards/x86/qemu_x86/Kconfig.board",
      "new_id": "d1a21829c960da3df4abe668a090d123bb7a2a4b",
      "new_mode": 33188,
      "new_path": "boards/x86/qemu_x86/Kconfig.board"
    },
    {
      "type": "modify",
      "old_id": "6d1c824f82993009b9c02fe4da0176f9b063edee",
      "old_mode": 33188,
      "old_path": "boards/x86/qemu_x86/qemu_x86.dts",
      "new_id": "e83ec7e43f5cf272c641f5c77de02b86405030a3",
      "new_mode": 33188,
      "new_path": "boards/x86/qemu_x86/qemu_x86.dts"
    },
    {
      "type": "modify",
      "old_id": "16fc2c36b6d0d4af643dc83e65cfa0ab560dc429",
      "old_mode": 33188,
      "old_path": "boards/x86/qemu_x86/qemu_x86_defconfig",
      "new_id": "ca82b60372e66d63e6379e805e2a458ca6bfea29",
      "new_mode": 33188,
      "new_path": "boards/x86/qemu_x86/qemu_x86_defconfig"
    },
    {
      "type": "modify",
      "old_id": "f0e151b7b9fc3617c6bb583823159cd504cee3f4",
      "old_mode": 33188,
      "old_path": "boards/x86/qemu_x86/qemu_x86_iamcu_defconfig",
      "new_id": "06b3c5c388c8bfc48fa10808039219c4d903f025",
      "new_mode": 33188,
      "new_path": "boards/x86/qemu_x86/qemu_x86_iamcu_defconfig"
    },
    {
      "type": "modify",
      "old_id": "0aa3c9e4e25dfcb058b503fde25c88f79a96a9bd",
      "old_mode": 33188,
      "old_path": "boards/x86/qemu_x86/qemu_x86_nommu_defconfig",
      "new_id": "0316974aa102fe9e793c5d9e2a8fd87911698e07",
      "new_mode": 33188,
      "new_path": "boards/x86/qemu_x86/qemu_x86_nommu_defconfig"
    }
  ]
}