# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
# SPDX-License-Identifier: Apache-2.0

choice
prompt "ITE IT8XXX2 system implementation"
depends on SOC_SERIES_RISCV32_IT8XXX2

config SOC_IT8XXX2
	bool "ITE IT8XXX2 system implementation"
	select RISCV
	select ATOMIC_OPERATIONS_BUILTIN
	select RISCV_ISA_RV32I
	select RISCV_ISA_EXT_ZICSR
	select RISCV_ISA_EXT_ZIFENCEI
	# Workaround mul instruction bug, see:
	# https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf
	#select RISCV_ISA_EXT_M
	select RISCV_ISA_EXT_A
	select RISCV_ISA_EXT_C

endchoice

if SOC_IT8XXX2

choice IT8XXX2_SERIES
	prompt "IT8XXX2 Series"
	default SOC_IT81302_BX

config SOC_IT81302_BX
	bool "IT81302 BX version"

config SOC_IT81202_BX
	bool "IT81202 BX version"

endchoice

config SOC_IT8XXX2_PLL_FLASH_48M
	bool "Flash frequency is 48MHz"
	default y
	help
	  Change frequency of PLL, CPU, and flash to 48MHz during initialization.

	  Set n to use the default settings.
	  (PLL and CPU run at 48MHz, flash frequency is 16MHz)

config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN
	bool "The pins of GPIO group K and L aren't bonding with pad"
	default y
	help
	  On IT81202 (128-pins package), the pins of GPIO group K and L aren't
	  bonding with pad. So we configure these pins as internal pull-down
	  at default to prevent leakage current due to floating.

config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW
	bool "The GPIOH7 isn't bonding with pad and is left floating internally"
	default y
	help
	  On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
	  floating internally. We need to enable internal pull-down for the pin
	  to prevent leakage current, but IT81202/IT81302 doesn't have the
	  capability to pull it down. We can only set it as output low,
	  so we enable output low for it at initialization to prevent leakage.

config SOC_IT8XXX2_CPU_IDLE_GATING
	bool
	help
	  This option determines whether the entering CPU idle mode can be
	  gated by individual drivers. When this option is disabled, CPU idle
	  mode is always permitted.

choice
	prompt "Clock source for PLL reference clock"

config SOC_IT8XXX2_INT_32K
	bool "Use the +/-2.3% internal clock generator"

config SOC_IT8XXX2_EXT_32K
	bool "Use external 32.768 kHz clock source"

endchoice

endif # SOC_IT8XXX2