tree 1ca782d4621a7dae6c5298eff17505e9c5923801
parent 21867fd4d0c5039621a906931b56f2763e93158b
author Georgij Cernysiov <geo.cgv@gmail.com> 1644320774 +0100
committer Anas Nashif <anas.nashif@intel.com> 1644333653 -0500

include: drivers: clock_control: stm32: fix xtpre

Correct DT property to set correct STM32_PLL_XTPRE value.
The driver bindings defined `xtpre` instead of used `xtre`
in the `DT_PROP` macro.
That allows to use F1 PLL clock with division by 2.

Signed-off-by: Georgij Cernysiov <geo.cgv@gmail.com>