# Kconfig - Atmel SAM E70 MCU series
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#

choice
	prompt "Atmel SAME70 MCU Selection"
	depends on SOC_SERIES_SAME70

	config SOC_PART_NUMBER_SAME70Q21
		bool "SAME70Q21"

	config SOC_PART_NUMBER_SAME70Q20
		bool "SAME70Q20"

	config SOC_PART_NUMBER_SAME70Q19
		bool "SAME70Q19"

	config SOC_PART_NUMBER_SAME70N21
		bool "SAME70N21"

	config SOC_PART_NUMBER_SAME70N20
		bool "SAME70N20"

	config SOC_PART_NUMBER_SAME70N19
		bool "SAME70N19"

	config SOC_PART_NUMBER_SAME70J21
		bool "SAME70J21"

	config SOC_PART_NUMBER_SAME70J20
		bool "SAME70J20"

	config SOC_PART_NUMBER_SAME70J19
		bool "SAME70J19"
endchoice

if SOC_SERIES_SAME70

config SOC_ATMEL_SAME70_EXT_SLCK
	bool "Use external crystal oscillator for slow clock"
	default n
	help
	Say y if you want to use external 32 kHz crystal
	oscillator to drive the slow clock. Note that this
	adds a few seconds to boot time, as the crystal
	needs to stabilize after power-up.

	Says n if you do not need accurate and precise timers.
	The slow clock will be driven by the internal fast
	RC oscillator running at 32 kHz.

config SOC_ATMEL_SAME70_EXT_MAINCK
	bool "Use external crystal oscillator for main clock"
	default n
	help
	The main clock is being used to drive the PLL, and
	thus driving the processor clock.

	Say y if you want to use external crystal oscillator
	to drive the main clock. Note that this adds about
	a second to boot time, as the crystal needs to
	stabilize after power-up.

	The crystal used here can be from 3 to 20 MHz.

	Says n here will use the internal fast RC oscillator
	running at 12 MHz.

config SOC_ATMEL_SAME70_MDIV
	int "MDIV"
	default 2
	range 1 4
	help
	This divisor defines a ratio between processor clock (HCLK)
	and master clock (MCK):
	MCK = HCLK / MDIV

config SOC_ATMEL_SAME70_PLLA_MULA
	int "PLL MULA"
	default 24
	range 1 62
	help
	This is the multiplier MULA used by the PLL.
	The processor clock is (MAINCK * (MULA + 1) / DIVA).

	Board config file can override this settings
	for a particular board.

	Setting MULA=0 would disable PLL at boot, this is currently
	not supported.

	With default of MULA == 24, and DIVA == 1,
	PLL is running at 25 times the main clock frequency.

config SOC_ATMEL_SAME70_PLLA_DIVA
	int "PLL DIVA"
	default 1
	range 1 255
	help
	This is the divider DIVA used by the PLL.
	The processor clock is (MAINCK * (MULA + 1) / DIVA).

	Board config file can override this settings
	for a particular board.

	Setting DIVA=0 would disable PLL at boot, this is currently
	not supported.

	With default of MULA == 24, and DIVA == 1,
	PLL is running at 25 times the main clock frequency.

config SOC_ATMEL_SAME70_WAIT_MODE
	bool "Go to Wait mode instead of Sleep mode"
	depends on SOC_ATMEL_SAME70_EXT_MAINCK
	default y if DEBUG
	help
	For JTAG debugging CPU clock (HCLK) should not stop. In order
	to achieve this, make CPU go to Wait mode instead of Sleep
	mode while using external crystal oscillator for main clock.

config SOC_ATMEL_SAME70_DISABLE_ERASE_PIN
	bool "Disable ERASE pin"
	default 0
	help
	At reset ERASE pin is configured in System IO mode. Asserting the ERASE
	pin at '1' will completely erase Flash memory. Setting this option will
	switch the pin to general IO mode giving control of the pin to the GPIO
	module.

endif # SOC_SERIES_SAME70