/*
 * Copyright (c) 2021 Guðni Már Gilbert
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/g4/stm32g4.dtsi>

/ {
	soc {
		can {
			can2: can@40006800 {
				compatible = "st,stm32-fdcan";
				reg = <0x40006800 0x400>, <0x4000A750 0x350>;
				reg-names = "m_can", "message_ram";
				interrupts = <86 0>, <87 0>;
				interrupt-names = "LINE_0", "LINE_1";
				clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
				status = "disabled";
				sjw = <1>;
				sample-point = <875>;
				sjw-data = <1>;
				sample-point-data = <875>;
			};
		};

		timers20: timers@40015000 {
			compatible = "st,stm32-timers";
			reg = <0x40015000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
			interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		dma1: dma@40020000 {
			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 96 0>;
			dma-requests = <8>;
		};

		dma2: dma@40020400 {
			interrupts = <56 0 57 0 58 0 59 0 60 0 97 0 98 0 99 0>;
			dma-requests = <8>;
			dma-offset = <8>;
		};

		dmamux1: dmamux@40020800 {
			dma-channels = <16>;
		};

		adc3: adc@50000400 {
			compatible = "st,stm32-adc";
			reg = <0x50000400 0x100>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00004000>;
			interrupts = <47 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			has-vref-channel;
		};
	};
};