diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 44404b1..c38fd40 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -24,6 +24,21 @@
 	string
 	default "arch/arc/defconfig"
 
+config CPU_HAS_MPU
+	bool
+	# Omit prompt to signify "hidden" option
+	default n
+	help
+	  This option is enabled when the CPU has a Memory Protection Unit (MPU).
+
+config CPU_HAS_FPU
+	# Hidden config selected by CPU family
+	bool
+	default n
+	help
+	This option is enabled when the CPU has hardware floating point
+	unit.
+
 menu "ARC EM4 processor options"
 
 config	CPU_ARCEM4
@@ -44,17 +59,6 @@
 	help
 	  This option signifies the use of a CPU of the ARCv2 family.
 
-config NSIM
-	prompt "Running on the MetaWare nSIM simulator"
-	bool
-	default n
-	help
-	  For running on nSIM simulator.
-
-	  a) Uses non-XIP to run in RAM.
-	  b) Linked at address 0x4000 with 0x4000 of RAM so that it works with
-	     a pc_size of 16 (default).
-
 config	DATA_ENDIANNESS_LITTLE
 	bool
 	default y
@@ -156,8 +160,40 @@
 	bool
 	default n
 	help
-	  The ARC CPU can be configured to have two busses;
-	  one for instruction fetching and another that serves as a data bus.
+	The ARC CPU can be configured to have two busses;
+	one for instruction fetching and another that serves as a data bus.
+
+config CODE_DENSITY
+	prompt "Code Density Option"
+	bool
+	default n
+	help
+	Enbale code density option to get better code desntiy
+
+menu "Floating Point Options"
+depends on CPU_HAS_FPU
+
+config FLOAT
+	bool
+	prompt "Floating point registers"
+	default n
+	help
+	This option allows tasks and fibers to use the floating point registers.
+	By default, only a single task or fiber may use the registers.
+
+	Disabling this option means that any task or fiber that uses a
+	floating point register will get a fatal exception.
+
+config FP_SHARING
+	bool
+	prompt "Floating point register sharing"
+	depends on FLOAT
+	default n
+	help
+	This option allows multiple tasks and fibers to use the floating point
+	registers.
+
+endmenu
 
 config ICCM_SIZE
 	int "ICCM Size in kB"
diff --git a/arch/arc/Makefile b/arch/arc/Makefile
index 58ac46b..e3ab74b 100644
--- a/arch/arc/Makefile
+++ b/arch/arc/Makefile
@@ -1,3 +1,8 @@
+# Enable debug support in mdb
+# Dwarf version 2 can be recognized by mdb
+# The default dwarf version in gdb is not recognized by mdb
+cflags-y += $(call cc-option, -g3 -gdwarf-2)
+
 cflags-y += $(call cc-option,-ffunction-sections,) $(call cc-option,-fdata-sections,)
 
 # Without this (poorly named) option, compiler may generate undefined
@@ -16,5 +21,4 @@
 soc-aflags ?= $(soc-cflags)
 KBUILD_CFLAGS += $(soc-cflags)
 KBUILD_CXXFLAGS += $(soc-cxxflags)
-KBUILD_AFLAGS += $(soc-aflags)
-
+KBUILD_AFLAGS += $(soc-aflags)
\ No newline at end of file
diff --git a/arch/arc/core/fast_irq.S b/arch/arc/core/fast_irq.S
index 5d1f1be..31b69cf 100644
--- a/arch/arc/core/fast_irq.S
+++ b/arch/arc/core/fast_irq.S
@@ -181,6 +181,14 @@
 	pop_s r0
 	mov lp_count,r0
 	ld r0,[saved_r0]
+#ifdef CONFIG_CODE_DENSITY
+	pop_s r0
+	sr r0, [_ARC_V2_EI_BASE]
+	pop_s r0
+	sr r0, [_ARC_V2_LDI_BASE]
+	pop_s r0
+	sr r0, [_ARC_V2_JLI_BASE]
+#endif
 	add sp,sp,8 /* don't need ilink & status32_po from stack */
 #endif
 	rtie
diff --git a/arch/arc/core/offsets/offsets.c b/arch/arc/core/offsets/offsets.c
index 09419c7..fd21524 100644
--- a/arch/arc/core/offsets/offsets.c
+++ b/arch/arc/core/offsets/offsets.c
@@ -52,6 +52,11 @@
 GEN_OFFSET_SYM(_isf_t, lp_end);
 GEN_OFFSET_SYM(_isf_t, lp_start);
 GEN_OFFSET_SYM(_isf_t, lp_count);
+#ifdef CONFIG_CODE_DENSITY
+GEN_OFFSET_SYM(_isf_t, ei_base);
+GEN_OFFSET_SYM(_isf_t, ldi_base);
+GEN_OFFSET_SYM(_isf_t, jli_base);
+#endif
 GEN_OFFSET_SYM(_isf_t, pc);
 GEN_OFFSET_SYM(_isf_t, status32);
 GEN_ABSOLUTE_SYM(___isf_t_SIZEOF, sizeof(_isf_t));
@@ -75,6 +80,19 @@
 GEN_OFFSET_SYM(_callee_saved_stack_t, r26);
 GEN_OFFSET_SYM(_callee_saved_stack_t, fp);
 GEN_OFFSET_SYM(_callee_saved_stack_t, r30);
+#ifdef CONFIG_FP_SHARING
+GEN_OFFSET_SYM(_callee_saved_stack_t, r58);
+GEN_OFFSET_SYM(_callee_saved_stack_t, r59);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_status);
+GEN_OFFSET_SYM(_callee_saved_stack_t, fpu_ctrl);
+#ifdef CONFIG_FP_FPU_DA
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2h);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp2l);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1h);
+GEN_OFFSET_SYM(_callee_saved_stack_t, dpfp1l);
+#endif
+
+#endif
 GEN_ABSOLUTE_SYM(___callee_saved_stack_t_SIZEOF, sizeof(_callee_saved_stack_t));
 
 GEN_ABSOLUTE_SYM(_K_THREAD_NO_FLOAT_SIZEOF, sizeof(struct k_thread));
diff --git a/arch/arc/core/regular_irq.S b/arch/arc/core/regular_irq.S
index d69f6b3..12ab5d7 100644
--- a/arch/arc/core/regular_irq.S
+++ b/arch/arc/core/regular_irq.S
@@ -121,7 +121,8 @@
 	 */
 	ldh_s r0, [r2, _thread_offset_to_preempt]
 	mov r3, _NON_PREEMPT_THRESHOLD
-	brhs.d r0, r3, _rirq_no_reschedule
+	cmp_s r0, r3
+	bhs.d _rirq_no_reschedule
 
 	/*
 	 * Both (a)reschedule and (b)non-reschedule cases need to load the
@@ -137,7 +138,8 @@
 
 	/* check if the current thread needs to be rescheduled */
 	ld_s r0, [r1, _kernel_offset_to_ready_q_cache]
-	breq r0, r2, _rirq_no_reschedule
+	cmp_s r0, r2
+	beq _rirq_no_reschedule
 
 	/* cached thread to run is in r0, fall through */
 
diff --git a/arch/arc/include/kernel_arch_data.h b/arch/arc/include/kernel_arch_data.h
index afb370b..d43a8fc 100644
--- a/arch/arc/include/kernel_arch_data.h
+++ b/arch/arc/include/kernel_arch_data.h
@@ -74,6 +74,8 @@
 
 typedef struct _irq_stack_frame _isf_t;
 
+
+
 /* callee-saved registers pushed on the stack, not in k_thread */
 struct _callee_saved_stack {
 	u32_t r13;
@@ -94,6 +96,19 @@
 	/* r28 is the stack pointer and saved separately */
 	/* r29 is ILINK and does not need to be saved */
 	u32_t r30;
+#ifdef CONFIG_FP_SHARING
+	u32_t r58;
+	u32_t r59;
+	u32_t fpu_status;
+	u32_t fpu_ctrl;
+#ifdef CONFIG_FP_FPU_DA
+	u32_t dpfp2h;
+	u32_t dpfp2l;
+	u32_t dpfp1h;
+	u32_t dpfp1l;
+#endif
+
+#endif
 	/*
 	 * No need to save r31 (blink), it's either alread pushed as the pc or
 	 * blink on an irq stack frame.
diff --git a/arch/arc/include/swap_macros.h b/arch/arc/include/swap_macros.h
index c8859d5..1d2a417 100644
--- a/arch/arc/include/swap_macros.h
+++ b/arch/arc/include/swap_macros.h
@@ -42,6 +42,26 @@
 	st r26, [sp, ___callee_saved_stack_t_r26_OFFSET]
 	st fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
 	st r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
+#ifdef CONFIG_FP_SHARING
+	st r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
+	st r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+	lr r13, [_ARC_V2_FPU_STATUS]
+	st_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
+	lr r13, [_ARC_V2_FPU_CTRL]
+	st_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
+
+#ifdef CONFIG_FP_FPU_DA
+	lr r13, [_ARC_V2_FPU_DPFP1L]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP1H]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP2L]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
+	lr r13, [_ARC_V2_FPU_DPFP2H]
+	st_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
+#endif
+
+#endif
 
 	/* save stack pointer in struct tcs */
 	st sp, [r2, _thread_offset_to_sp]
@@ -69,6 +89,31 @@
 	ld fp,  [sp, ___callee_saved_stack_t_fp_OFFSET]
 	ld r30, [sp, ___callee_saved_stack_t_r30_OFFSET]
 
+#ifdef CONFIG_FP_SHARING
+	ld r58, [sp, ___callee_saved_stack_t_r58_OFFSET]
+	ld r59, [sp, ___callee_saved_stack_t_r59_OFFSET]
+
+	ld_s r13, [sp, ___callee_saved_stack_t_fpu_status_OFFSET]
+	sr r13, [_ARC_V2_FPU_STATUS]
+
+	ld_s r13, [sp, ___callee_saved_stack_t_fpu_ctrl_OFFSET]
+	sr r13, [_ARC_V2_FPU_CTRL]
+
+
+#ifdef CONFIG_FP_FPU_DA
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1l_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP1L]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp1h_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP1H]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2l_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP2L]
+	ld_s r13, [sp, ___callee_saved_stack_t_dpfp2h_OFFSET]
+	sr r13, [_ARC_V2_FPU_DPFP2H]
+#endif
+
+#endif
+
+
 	add_s sp, sp, ___callee_saved_stack_t_SIZEOF
 
 .endm
@@ -111,6 +156,15 @@
 	st_s r1, [sp, ___isf_t_lp_start_OFFSET]
 	st_s r0, [sp, ___isf_t_lp_end_OFFSET]
 
+#ifdef CONFIG_CODE_DENSITY
+	lr r1, [_ARC_V2_JLI_BASE]
+	lr r0, [_ARC_V2_LDI_BASE]
+	lr r2, [_ARC_V2_EI_BASE]
+	st_s r1, [sp, ___isf_t_jli_base_OFFSET]
+	st_s r0, [sp, ___isf_t_ldi_base_OFFSET]
+	st_s r2, [sp, ___isf_t_ei_base_OFFSET]
+#endif
+
 .endm
 
 /*
@@ -121,6 +175,15 @@
 
 	ld blink, [sp, ___isf_t_blink_OFFSET]
 
+#ifdef CONFIG_CODE_DENSITY
+	ld_s r1, [sp, ___isf_t_jli_base_OFFSET]
+	ld_s r0, [sp, ___isf_t_ldi_base_OFFSET]
+	ld_s r2, [sp, ___isf_t_ei_base_OFFSET]
+	sr r1, [_ARC_V2_JLI_BASE]
+	sr r0, [_ARC_V2_LDI_BASE]
+	sr r2, [_ARC_V2_EI_BASE]
+#endif
+
 	ld_s r0, [sp, ___isf_t_lp_count_OFFSET]
 	mov lp_count, r0
 	ld_s r1, [sp, ___isf_t_lp_start_OFFSET]
@@ -143,6 +206,7 @@
 	ld_s r1,  [sp, ___isf_t_r1_OFFSET]
 	ld_s r0,  [sp, ___isf_t_r0_OFFSET]
 
+
 	/*
 	 * All gprs have been reloaded, the only one that is still usable is
 	 * ilink.
diff --git a/arch/arc/include/v2/irq.h b/arch/arc/include/v2/irq.h
index 9de86d6..8c3fe82 100644
--- a/arch/arc/include/v2/irq.h
+++ b/arch/arc/include/v2/irq.h
@@ -26,6 +26,7 @@
 #define _ARC_V2_AUX_IRQ_CTRL_16_REGS 8
 #define _ARC_V2_AUX_IRQ_CTRL_32_REGS 16
 
+
 #define _ARC_V2_DEF_IRQ_LEVEL (CONFIG_NUM_IRQ_PRIO_LEVELS-1)
 #define _ARC_V2_WAKE_IRQ_LEVEL _ARC_V2_DEF_IRQ_LEVEL
 
@@ -43,6 +44,9 @@
 {
 	u32_t aux_irq_ctrl_value = (
 		_ARC_V2_AUX_IRQ_CTRL_LOOP_REGS | /* save lp_xxx registers */
+#ifdef CONFIG_CODE_DENSITY
+		_ARC_V2_AUX_IRQ_CTRL_LP | /* save code density registers */
+#endif
 		_ARC_V2_AUX_IRQ_CTRL_BLINK     | /* save blink */
 		_ARC_V2_AUX_IRQ_CTRL_14_REGS     /* save r0 -> r13 (caller-saved) */
 	);
diff --git a/arch/arc/soc/em11d/Kconfig.defconfig b/arch/arc/soc/em11d/Kconfig.defconfig
index c12e3d3..776211c 100644
--- a/arch/arc/soc/em11d/Kconfig.defconfig
+++ b/arch/arc/soc/em11d/Kconfig.defconfig
@@ -19,7 +19,7 @@
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38
 
 config RGF_NUM_BANKS
 	default 2
@@ -58,6 +58,9 @@
 config CACHE_FLUSHING
 	def_bool y
 
+config FP_FPU_DA
+	def_bool y
+
 if GPIO
 
 config GPIO_DW
diff --git a/arch/arc/soc/em11d/Kconfig.soc b/arch/arc/soc/em11d/Kconfig.soc
index 3fe6eeb..dd931a5 100644
--- a/arch/arc/soc/em11d/Kconfig.soc
+++ b/arch/arc/soc/em11d/Kconfig.soc
@@ -1,3 +1,5 @@
 
 config SOC_EM11D
 	bool "Synopsys ARC EM11D"
+	select CPU_HAS_FPU
+
diff --git a/arch/arc/soc/em11d/Makefile b/arch/arc/soc/em11d/Makefile
index a86cfcb..13ccc91 100644
--- a/arch/arc/soc/em11d/Makefile
+++ b/arch/arc/soc/em11d/Makefile
@@ -1,2 +1,16 @@
-soc-cflags = $(call cc-option,-mcpu=arcem) \
-                   $(call cc-option,-mno-sdata)
+#  -mcpu=em4_fpuda is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_fpuda
+
+soc-cflags += $(call cc-option, -mcpu=em4_fpuda -mno-sdata -mdiv-rem -mswap -mnorm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
+		$(call cc-option,--param l1-cache-size=16384) \
+		$(call cc-option,--param l1-cache-line-size=32)
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option, -mcode-density)
+endif
+
+ifeq ($(CONFIG_FLOAT), y)
+soc-cflags += $(call cc-option, -mfpu=fpuda_all)
+endif
+
diff --git a/arch/arc/soc/em11d/soc.h b/arch/arc/soc/em11d/soc.h
index 3e78bfe..be88505 100644
--- a/arch/arc/soc/em11d/soc.h
+++ b/arch/arc/soc/em11d/soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2017 Synopsys, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,63 +18,68 @@
 
 /* default system clock */
 
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
 
 
 /* IRQs */
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
+#define IRQ_CORE_DMA_COMPLETE			22
+#define IRQ_CORE_DMA_ERROR			23
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
 
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
+#define I2C_DW_0_BASE_ADDR			0xF0004000
+#define I2C_DW_0_IRQ				25
 
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
+#define I2C_DW_1_IRQ				26
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ				24
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ				0          /* can't interrupt */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ				0          /* can't interrupt */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ				0          /* can't interrupt */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* undef GPIO_DW_IO_ACCESS .. because memory mapped */
 /* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@@ -83,15 +88,15 @@
 
 /* SPI */
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
 
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -106,18 +111,22 @@
 
 /*
  * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+     UART0 vector 29 0xF0008000
+     UART1 vector 30 0xF0009000
+     UART2 vector 31 0xF000A000
  */
 #define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_IRQ				29
 #define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
 #define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_IRQ				30
 #define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
+#define UART_NS16550_PORT_2_BASE_ADDR			0xF000A000
+#define UART_NS16550_PORT_2_IRQ				31
+#define UART_NS16550_PORT_2_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
 #define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
diff --git a/arch/arc/soc/em7d/Kconfig.defconfig b/arch/arc/soc/em7d/Kconfig.defconfig
index cecf493..9bd5c91 100644
--- a/arch/arc/soc/em7d/Kconfig.defconfig
+++ b/arch/arc/soc/em7d/Kconfig.defconfig
@@ -19,13 +19,13 @@
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38
 
 config RGF_NUM_BANKS
 	default 1
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 30000000
+	default 25000000
 
 config HARVARD
 	def_bool n
diff --git a/arch/arc/soc/em7d/Makefile b/arch/arc/soc/em7d/Makefile
index a86cfcb..9fe42ab 100644
--- a/arch/arc/soc/em7d/Makefile
+++ b/arch/arc/soc/em7d/Makefile
@@ -1,2 +1,12 @@
-soc-cflags = $(call cc-option,-mcpu=arcem) \
-                   $(call cc-option,-mno-sdata)
+#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_dmips
+
+soc-cflags = $(call cc-option,-mcpu=em4_dmips -mno-sdata) \
+		$(call cc-option,-mdiv-rem -mswap -mnormm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
+		$(call cc-option,--param l1-cache-size=16384) \
+		$(call cc-option,--param l1-cache-line-size=32)
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option,-mcode-density)
+endif
diff --git a/arch/arc/soc/em7d/soc.h b/arch/arc/soc/em7d/soc.h
index ea8cf45..91f60ab 100644
--- a/arch/arc/soc/em7d/soc.h
+++ b/arch/arc/soc/em7d/soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2017 Synopsys, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,63 +18,69 @@
 
 /* default system clock */
 
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
 
 
 /* IRQs */
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
+#define IRQ_SEC_TIMER0				20
+#define IRQ_CORE_DMA_COMPLETE			22
+#define IRQ_CORE_DMA_ERROR			23
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
 
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
+#define I2C_DW_0_BASE_ADDR			0xF0004000
+#define I2C_DW_0_IRQ				25
 
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
+#define I2C_DW_1_IRQ				26
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ				24
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ				0          /* can't interrupt */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ				0          /* can't interrupt */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ				0          /* can't interrupt */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* undef GPIO_DW_IO_ACCESS .. because memory mapped */
 /* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@@ -83,15 +89,15 @@
 
 /* SPI */
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
 
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -106,18 +112,22 @@
 
 /*
  * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+     UART0 vector 29 0xF0008000
+     UART1 vector 30 0xF0009000
+     UART2 vector 31 0xF000A000
  */
 #define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_IRQ				29
 #define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
 #define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_IRQ				30
 #define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
+#define UART_NS16550_PORT_2_BASE_ADDR			0xF000A000
+#define UART_NS16550_PORT_2_IRQ				31
+#define UART_NS16550_PORT_2_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
 #define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
diff --git a/arch/arc/soc/em9d/Kconfig.defconfig b/arch/arc/soc/em9d/Kconfig.defconfig
index 3731fd7..1cdff89 100644
--- a/arch/arc/soc/em9d/Kconfig.defconfig
+++ b/arch/arc/soc/em9d/Kconfig.defconfig
@@ -19,7 +19,7 @@
 
 config NUM_IRQS
 	# must be > the highest interrupt number used
-	default 36
+	default 38
 
 config RGF_NUM_BANKS
 	default 2
diff --git a/arch/arc/soc/em9d/Kconfig.soc b/arch/arc/soc/em9d/Kconfig.soc
index 81eb02b..d0af561 100644
--- a/arch/arc/soc/em9d/Kconfig.soc
+++ b/arch/arc/soc/em9d/Kconfig.soc
@@ -1,3 +1,4 @@
 
 config SOC_EM9D
 	bool "Synopsys ARC EM9D"
+	select CPU_HAS_FPU
diff --git a/arch/arc/soc/em9d/Makefile b/arch/arc/soc/em9d/Makefile
index 268ad0c..5c96dcf 100644
--- a/arch/arc/soc/em9d/Makefile
+++ b/arch/arc/soc/em9d/Makefile
@@ -1,2 +1,14 @@
-soc-cflags = $(call cc-option,-mcpu=arcem) \
-                  $(call cc-option,-mno-sdata)
+#  -mcpu=em4_dmips is added to KBUILD_CFLAGS to make cc-option check the options correctly
+KBUILD_CFLAGS += -mcpu=em4_fpus
+
+soc-cflags += $(call cc-option,-mcpu=em4_fpus -mno-sdata) \
+		$(call cc-option,-mdiv-rem -mswap -mnormm) \
+		$(call cc-option,-mmpy-option=6 -mbarrel-shifter) \
+
+ifeq ($(CONFIG_CODE_DENSITY), y)
+soc-cflags += $(call cc-option,-mcode-density)
+endif
+
+ifeq ($(CONFIG_FLOAT), y)
+soc-cflags += 	$(call cc-option,-mfpu=fpus_all)
+endif
\ No newline at end of file
diff --git a/arch/arc/soc/em9d/soc.h b/arch/arc/soc/em9d/soc.h
index ea8cf45..be88505 100644
--- a/arch/arc/soc/em9d/soc.h
+++ b/arch/arc/soc/em9d/soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016 Synopsys, Inc. All rights reserved.
+ * Copyright (c) 2017 Synopsys, Inc. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,63 +18,68 @@
 
 /* default system clock */
 
-#define SYSCLK_DEFAULT_IOSC_HZ MHZ(50)
+#define SYSCLK_DEFAULT_IOSC_HZ			MHZ(50)
 /* On the EM Starter Kit board, the peripheral bus clock frequency is 50Mhz */
 
 
 /* IRQs */
 
-#define IRQ_TIMER0 16
-#define IRQ_TIMER1 17
+#define IRQ_TIMER0				16
+#define IRQ_TIMER1				17
+#define IRQ_CORE_DMA_COMPLETE			22
+#define IRQ_CORE_DMA_ERROR			23
 
 #ifndef _ASMLANGUAGE
 
 #include <misc/util.h>
 #include <drivers/rand32.h>
 
-#define ARCV2_TIMER0_INT_LVL IRQ_TIMER0
-#define ARCV2_TIMER0_INT_PRI 0
+#define ARCV2_TIMER0_INT_LVL			IRQ_TIMER0
+#define ARCV2_TIMER0_INT_PRI			0
 
-#define CONFIG_ARCV2_TIMER1_INT_LVL IRQ_TIMER1
-#define CONFIG_ARCV2_TIMER1_INT_PRI 1
+#define ARCV2_TIMER1_INT_LVL			IRQ_TIMER1
+#define ARCV2_TIMER1_INT_PRI			1
 
-#define INT_ENABLE_ARC					~(0x00000001 << 8)
-#define INT_ENABLE_ARC_BIT_POS				(8)
+#define CONFIG_ARCV2_TIMER1_INT_LVL		IRQ_TIMER1
+#define CONFIG_ARCV2_TIMER1_INT_PRI		1
+
+#define INT_ENABLE_ARC				~(0x00000001 << 8)
+#define INT_ENABLE_ARC_BIT_POS			(8)
 
 /* I2C */
 
 /* I2C_0 is on Pmod2 connector */
-#define I2C_DW_0_BASE_ADDR                      0xF0004000
-#define I2C_DW_0_IRQ                            23
+#define I2C_DW_0_BASE_ADDR			0xF0004000
+#define I2C_DW_0_IRQ				25
 
 
 /* I2C_1 is on Pmod4 connector */
-#define I2C_DW_1_BASE_ADDR                      0xF0005000
-#define I2C_DW_1_IRQ                            24
+#define I2C_DW_1_BASE_ADDR			0xF0005000
+#define I2C_DW_1_IRQ				26
 
 #define I2C_DW_IRQ_FLAGS			0
 
 /* GPIO */
-#define GPIO_DW_0_BASE_ADDR                     0xF0002000 /* GPIO 0 : PORTA */
-#define GPIO_DW_0_IRQ                           22
-#define GPIO_DW_0_BITS                          32
-#define GPIO_DW_PORT_0_INT_MASK                 0 /* n/a */
+#define GPIO_DW_0_BASE_ADDR			0xF0002000 /* GPIO 0 : PORTA */
+#define GPIO_DW_0_IRQ				24
+#define GPIO_DW_0_BITS				32
+#define GPIO_DW_PORT_0_INT_MASK			0 /* n/a */
 #define GPIO_DW_0_IRQ_FLAGS			0 /* Defaults */
 
-#define GPIO_DW_1_BASE_ADDR                     0xF000200C /* GPIO 1 : PORTB */
-#define GPIO_DW_1_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_1_BITS                          9          /* 9 LEDs on board */
-#define GPIO_DW_PORT_1_INT_MASK                 0 /* n/a */
+#define GPIO_DW_1_BASE_ADDR			0xF000200C /* GPIO 1 : PORTB */
+#define GPIO_DW_1_IRQ				0          /* can't interrupt */
+#define GPIO_DW_1_BITS				9          /* 9 LEDs on board */
+#define GPIO_DW_PORT_1_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_2_BASE_ADDR                     0xF0002018 /* GPIO 2 : PORTC */
-#define GPIO_DW_2_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_2_BITS                          32
-#define GPIO_DW_PORT_2_INT_MASK                 0 /* n/a */
+#define GPIO_DW_2_BASE_ADDR			0xF0002018 /* GPIO 2 : PORTC */
+#define GPIO_DW_2_IRQ				0          /* can't interrupt */
+#define GPIO_DW_2_BITS				32
+#define GPIO_DW_PORT_2_INT_MASK			0 /* n/a */
 
-#define GPIO_DW_3_BASE_ADDR                     0xF0002024 /* GPIO 3 : PORTD */
-#define GPIO_DW_3_IRQ                           0          /* can't interrupt */
-#define GPIO_DW_3_BITS                          12
-#define GPIO_DW_PORT_3_INT_MASK                 0 /* n/a */
+#define GPIO_DW_3_BASE_ADDR			0xF0002024 /* GPIO 3 : PORTD */
+#define GPIO_DW_3_IRQ				0          /* can't interrupt */
+#define GPIO_DW_3_BITS				12
+#define GPIO_DW_PORT_3_INT_MASK			0 /* n/a */
 
 /* undef GPIO_DW_IO_ACCESS .. because memory mapped */
 /* undef CONFIG_GPIO_DW_0_IRQ_SHARED */
@@ -83,15 +88,15 @@
 
 /* SPI */
 
-#define SPI_DW_SPI_CLOCK     SYSCLK_DEFAULT_IOSC_HZ
+#define SPI_DW_SPI_CLOCK			SYSCLK_DEFAULT_IOSC_HZ
 
-#define SPI_DW_PORT_0_REGS   0xF0006000
-#define SPI_DW_PORT_1_REGS   0xF0007000
+#define SPI_DW_PORT_0_REGS			0xF0006000
+#define SPI_DW_PORT_1_REGS			0xF0007000
 
-#define SPI_DW_PORT_0_IRQ    25
-#define SPI_DW_PORT_1_IRQ    26
+#define SPI_DW_PORT_0_IRQ			27
+#define SPI_DW_PORT_1_IRQ			28
 
-#define SPI_DW_IRQ_FLAGS     0
+#define SPI_DW_IRQ_FLAGS			0
 
 /*
  * SPI Chip Select Assignments on EM Starter Kit
@@ -106,18 +111,22 @@
 
 /*
  * UART
-     UART0 vector 27 0xF0008000
-     UART1 vector 28 0xF0009000
-     UART2 vector 29 0xF000A000
+     UART0 vector 29 0xF0008000
+     UART1 vector 30 0xF0009000
+     UART2 vector 31 0xF000A000
  */
 #define UART_NS16550_PORT_0_BASE_ADDR			0xF0008000
-#define UART_NS16550_PORT_0_IRQ				27
+#define UART_NS16550_PORT_0_IRQ				29
 #define UART_NS16550_PORT_0_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
 #define UART_NS16550_PORT_1_BASE_ADDR			0xF0009000
-#define UART_NS16550_PORT_1_IRQ				28
+#define UART_NS16550_PORT_1_IRQ				30
 #define UART_NS16550_PORT_1_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
 
+#define UART_NS16550_PORT_2_BASE_ADDR			0xF000A000
+#define UART_NS16550_PORT_2_IRQ				31
+#define UART_NS16550_PORT_2_CLK_FREQ			SYSCLK_DEFAULT_IOSC_HZ
+
 #define UART_IRQ_FLAGS					0 /* Default */
 #endif /* !_ASMLANGUAGE */
 
diff --git a/boards/arc/em_starterkit/Kconfig.board b/boards/arc/em_starterkit/Kconfig.board
index c323e15..ce54761 100644
--- a/boards/arc/em_starterkit/Kconfig.board
+++ b/boards/arc/em_starterkit/Kconfig.board
@@ -10,7 +10,7 @@
 	help
 	The DesignWare ARC EM Starter Kit board is a board
 	that can host up to 3 different SOC FPGA bit files.
-	Version 2.2 firmware supports EM7D, EM9D and EM11D configurations.
+	Version 2.3 firmware supports EM7D, EM9D and EM11D configurations.
 	EM9D using CCM memories and is a Harvard Architecture.
 	EM7D and EM11D have access to 128MB DRAM and use i-cache and d-cache.
-
+	EM7D has secureshield feature, which is not supported in Zephyr currently.
diff --git a/boards/arc/em_starterkit/Makefile.board b/boards/arc/em_starterkit/Makefile.board
index 4ee729b..48f70fb 100644
--- a/boards/arc/em_starterkit/Makefile.board
+++ b/boards/arc/em_starterkit/Makefile.board
@@ -1,16 +1,7 @@
-#
-# TODO: This file is WRONG currently.
-#   The Zephyr-SDK tools don't yet support working with the ARC EM Starter Kit
-#   See doc/board/em_starterkit.rst for more details.
-#
-#FLASH_SCRIPT = openocd.sh
-#  ^^ Keep FLASH_SCRIPT undefined for now since flashing a self-boot image
-#     is not yet supported by Zephyr Makefile.
-OPENOCD_PRE_CMD = "targets 1"
-OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_ICCM_BASE_ADDRESS)"
-OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_BIN_NAME} $(CONFIG_ICCM_BASE_ADDRESS)"
+FLASH_SCRIPT = arc_debugger.sh
+DEBUG_SCRIPT = arc_debugger.sh
 
-GDB_PORT = 3333
+OPENOCD_LOAD_CMD = "load_image ${O}/${KERNEL_ELF_NAME}"
+OPENOCD_VERIFY_CMD = "verify_image ${O}/${KERNEL_ELF_NAME}"
 
-export OPENOCD_PRE_CMD FLASH_SCRIPT OPENOCD_VERIFY_CMD OPENOCD_LOAD_CMD GDB_PORT
-
+export FLASH_SCRIPT DEBUG_SCRIPT OPENOCD_VERIFY_CMD OPENOCD_LOAD_CMD
\ No newline at end of file
diff --git a/boards/arc/em_starterkit/board.h b/boards/arc/em_starterkit/board.h
index 5580515..7a8ede8 100644
--- a/boards/arc/em_starterkit/board.h
+++ b/boards/arc/em_starterkit/board.h
@@ -9,4 +9,55 @@
 
 #include <soc.h>
 
+/* Switches */
+#define SW0_GPIO_PIN	0
+#define SW0_GPIO_NAME	CONFIG_GPIO_DW_2_NAME
+
+#define SW1_GPIO_PIN	1
+#define SW1_GPIO_NAME	CONFIG_GPIO_DW_2_NAME
+
+#define SW2_GPIO_PIN	2
+#define SW2_GPIO_NAME	CONFIG_GPIO_DW_2_NAME
+
+#define SW3_GPIO_PIN	3
+#define SW3_GPIO_NAME	CONFIG_GPIO_DW_2_NAME
+
+/* Buttons */
+#define BTN0_GPIO_PIN	0
+#define BTN0_GPIO_NAME	CONFIG_GPIO_DW_0_NAME
+
+#define BTN1_GPIO_PIN	1
+#define BTN1_GPIO_NAME	CONFIG_GPIO_DW_0_NAME
+
+#define BTN2_GPIO_PIN	2
+#define BTN2_GPIO_NAME	CONFIG_GPIO_DW_0_NAME
+
+/* Onboard LEDs */
+#define LED0_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED0_GPIO_PIN   0
+
+#define LED1_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED1_GPIO_PIN   1
+
+#define LED2_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED2_GPIO_PIN   2
+
+#define LED3_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED3_GPIO_PIN   3
+
+#define LED4_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED4_GPIO_PIN   4
+
+#define LED5_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED5_GPIO_PIN   5
+
+#define LED6_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED6_GPIO_PIN   6
+
+#define LED7_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED7_GPIO_PIN   7
+
+#define LED8_GPIO_PORT  CONFIG_GPIO_DW_1_NAME
+#define LED8_GPIO_PIN   8
+
 #endif /* __INC_BOARD_H */
diff --git a/boards/arc/em_starterkit/em_starterkit_defconfig b/boards/arc/em_starterkit/em_starterkit_defconfig
index 086f3fd..513a3d0 100644
--- a/boards/arc/em_starterkit/em_starterkit_defconfig
+++ b/boards/arc/em_starterkit/em_starterkit_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARC=y
-CONFIG_SOC_EM7D=y
+CONFIG_SOC_EM11D=y
 CONFIG_BOARD_EM_STARTERKIT=y
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_XIP=n
diff --git a/boards/arc/em_starterkit/support/openocd.cfg b/boards/arc/em_starterkit/support/openocd.cfg
index b9359d4..f2cd062 100644
--- a/boards/arc/em_starterkit/support/openocd.cfg
+++ b/boards/arc/em_starterkit/support/openocd.cfg
@@ -1,17 +1,12 @@
-#
-# TODO: This file cannot be used yet. snps_em_sk.cfg is WRONG in Zephyr-SDK.
-#  Instead the user must download newer ARC GNU tools from github.
-#  See doc/board/em_starterkit.rst for more details.
-#
-#source [find interface/digilent-hs1.cfg] ...done in board file.
-source [find board/snps_em_sk.cfg]
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
 
-#em_starterkit.em9d configure -event gdb-attach {
-#        reset halt
-##        gdb_breakpoint_override hard
-#}
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter_khz 5000
 
-#em_starterkit.em9d configure -event gdb-detach {
-#        resume
-#        shutdown
-#}
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
\ No newline at end of file
diff --git a/include/arch/arc/v2/aux_regs.h b/include/arch/arc/v2/aux_regs.h
index 41ae4c5..fd2583a 100644
--- a/include/arch/arc/v2/aux_regs.h
+++ b/include/arch/arc/v2/aux_regs.h
@@ -73,6 +73,9 @@
 #define _ARC_V2_IRQ_PRIORITY 0x206
 #define _ARC_V2_KSTACK_TOP 0x264
 #define _ARC_V2_KSTACK_BASE 0x265
+#define _ARC_V2_JLI_BASE 0x290
+#define _ARC_V2_LDI_BASE 0x291
+#define _ARC_V2_EI_BASE 0x292
 #define _ARC_V2_ERET 0x400
 #define _ARC_V2_ERSTATUS 0x402
 #define _ARC_V2_ECR 0x403
@@ -84,6 +87,12 @@
 #define _ARC_V2_IRQ_STATUS 0x40f
 #define _ARC_V2_IRQ_PULSE_CANCEL 0x415
 #define _ARC_V2_IRQ_PENDING 0x416
+#define _ARC_V2_FPU_CTRL 0x300
+#define _ARC_V2_FPU_STATUS 0x301
+#define _ARC_V2_FPU_DPFP1L 0x302
+#define _ARC_V2_FPU_DPFP1H 0x303
+#define _ARC_V2_FPU_DPFP2L 0x304
+#define _ARC_V2_FPU_DPFP2H 0x305
 
 /* STATUS32/STATUS32_P0 bits */
 #define _ARC_V2_STATUS32_H (1 << 0)
diff --git a/scripts/support/arc_debugger.sh b/scripts/support/arc_debugger.sh
new file mode 100755
index 0000000..02aa926
--- /dev/null
+++ b/scripts/support/arc_debugger.sh
@@ -0,0 +1,127 @@
+#!/bin/sh
+
+# This script is loosly based on a script with same purpose provided
+# by RIOT-OS (https://github.com/RIOT-OS/RIOT)
+
+OPENOCD=${OPENOCD:-openocd}
+OPENOCD_CMD="${OPENOCD}${OPENOCD_DEFAULT_PATH:+ -s $OPENOCD_DEFAULT_PATH}"
+OPENOCD_CONFIG=${ZEPHYR_BASE}/boards/${ARCH}/${BOARD_NAME}/support/openocd.cfg
+BIN_NAME=${O}/${KERNEL_BIN_NAME}
+ELF_NAME=${O}/${KERNEL_ELF_NAME}
+
+test_config() {
+    if [ ! -f "${OPENOCD_CONFIG}" ]; then
+        echo "Error: Unable to locate OpenOCD configuration file: ${OPENOCD_CONFIG}"
+        exit 1
+    fi
+    if ! which ${OPENOCD} >/dev/null 2>&1; then
+        echo "Error: Unable to locate OpenOCD executable: ${OPENOCD}"
+        exit 1
+    fi
+}
+
+test_bin() {
+    if [ ! -f "${BIN_NAME}" ]; then
+        echo "Error: Unable to locate image binary: ${BIN_NAME}"
+        exit 1
+    fi
+}
+
+do_flash() {
+    test_config
+    test_bin
+
+    # flash device with specified image
+    # setsid is needed so that Ctrl+C in GDB doesn't kill OpenOCD
+    [ -z "${SETSID}" ] && SETSID="$(which setsid)"
+    # temporary file that saves OpenOCD pid
+    OCD_PIDFILE=$(mktemp -t "openocd_pid.XXXXXXXXXX")
+    # cleanup after script terminates
+    trap "cleanup ${OCD_PIDFILE}" EXIT
+    # don't trap on Ctrl+C, because GDB keeps running
+    trap '' INT
+    # start OpenOCD as GDB server
+    ${SETSID} sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
+            ${OPENOCD_EXTRA_INIT} \
+            -c 'tcl_port ${TCL_PORT:-6333}' \
+            -c 'telnet_port ${TELNET_PORT:-4444}' \
+            -c 'gdb_port ${GDB_PORT:-3333}' \
+            -c 'init' \
+            -c 'targets' \
+            -c 'halt' \
+             & \
+            echo \$! > $OCD_PIDFILE" &
+    # connect to the GDB server
+    ${GDB} ${TUI} -ex "target remote :${GDB_PORT:-3333}" \
+            -ex "load" -ex "c" ${ELF_NAME}
+    # will be called by trap
+    cleanup() {
+        OCD_PID="$(cat $OCD_PIDFILE)"
+        kill ${OCD_PID} &>/dev/null
+        rm -f "$OCD_PIDFILE"
+        exit 0
+    }
+}
+
+
+do_debug() {
+    test_config
+    test_bin
+    # setsid is needed so that Ctrl+C in GDB doesn't kill OpenOCD
+    [ -z "${SETSID}" ] && SETSID="$(which setsid)"
+    # temporary file that saves OpenOCD pid
+    OCD_PIDFILE=$(mktemp -t "openocd_pid.XXXXXXXXXX")
+    # cleanup after script terminates
+    trap "cleanup ${OCD_PIDFILE}" EXIT
+    # don't trap on Ctrl+C, because GDB keeps running
+    trap '' INT
+    # start OpenOCD as GDB server
+    ${SETSID} sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
+            ${OPENOCD_EXTRA_INIT} \
+            -c 'tcl_port ${TCL_PORT:-6333}' \
+            -c 'telnet_port ${TELNET_PORT:-4444}' \
+            -c 'gdb_port ${GDB_PORT:-3333}' \
+            -c 'init' \
+            -c 'targets' \
+            -c 'halt' \
+             & \
+            echo \$! > $OCD_PIDFILE" &
+    # connect to the GDB server
+    ${GDB} ${TUI} -ex "target remote :${GDB_PORT:-3333}" -ex "load" ${ELF_NAME}
+    # will be called by trap
+    cleanup() {
+        OCD_PID="$(cat $OCD_PIDFILE)"
+        kill ${OCD_PID} &>/dev/null
+        rm -f "$OCD_PIDFILE"
+        exit 0
+    }
+}
+
+do_debugserver() {
+    test_config
+    sh -c "${OPENOCD_CMD} -f '${OPENOCD_CONFIG}' \
+            -c 'init' \
+            -c 'targets' \
+            -c 'reset halt'"
+}
+
+CMD="$1"
+shift
+
+if [ "$KBUILD_VERBOSE" -eq 1 ]
+then
+	set -x
+fi
+
+case "${CMD}" in
+  flash)
+    echo "Flashing Target Device"
+    do_flash "$@"
+    ;;
+  debugserver)
+    do_debugserver "$@"
+    ;;
+  debug)
+    do_debug "$@"
+    ;;
+esac