drivers: flash: flash_mcux_flexspi_nor: fix QER S2B1v5 status reg case

The JESD216_DW15_QER_VAL_S2B1v5 case had incorrect status register
read/write logic. It was reading only SR2 but writing both SR1 and SR2,
which could corrupt SR1 if not read first.

Merge the S2B1v5 case with S2B1v1/v4 cases since they all set bit 1 of
SR2. Update the common path to properly handle both single-byte (SR2 only)
and two-byte (SR1+SR2) read/write operations by:

- Reading SR1 first when rd_size is 2, saving it temporarily
- Reading SR2 using the scratch command
- Combining both bytes with SR2 in the upper byte when needed
- Writing the combined value with the QE bit set

Remove the now-redundant S2B1v5-specific case and simplify the LUT
sequence to read SR2 directly instead of reading SR1 first.

Signed-off-by: Albort Xue <yao.xue@nxp.com>