/*
 * Copyright 2022 NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/ {
	soc {
		sram: sram@400000 {
			ranges = <0x4000000 0x4000000 0x20000000>;
		};

		peripheral: peripheral@40000000 {
			ranges = <0x0 0x40000000 0x10000000>;
		};
	};
};

#include "nxp_lpc55S3x_common.dtsi"

/*
 * lpc55S_36:
 * Combine SRAM0, SRAM1, SRAM2, SRAM3, SRAM4 for total of 112K RAM
 */
&sram0 {
	compatible = "mmio-sram";
	reg = <0x20000000 DT_SIZE_K(112)>;
};