# Copyright (c) 2021, Linaro ltd
# SPDX-License-Identifier: Apache-2.0

description: |
  STM32L4 Main PLL node binding:

  Takes one of clk_hse or clk_hsi as input clock, with an
  input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
  in this acceptable range.

  Up to 2 output clocks could be supported and for each output clock, the
  frequency can be computed with the following formula:

    f(PLL_P) = f(VCO clock) / PLLP  --> PLLCLK (System Clock)
    f(PLL_Q) = f(VCO clock) / PLLQ  --> PLL48CLK (Optional)

      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

  The PLL output frequency must not exceed 80 MHz.


compatible: "st,stm32f4-pll-clock"

include: [clock-controller.yaml, base.yaml]

properties:
    "#clock-cells":
      const: 0

    clocks:
      required: true

    div-m:
      type: int
      required: true
      description: |
          Division factor for the PLL input clock
          Valid range: 2 - 63

    mul-n:
      type: int
      required: true
      description: |
          Main PLL multiplication factor for VCO
          Valid range: 50 - 432

    div-p:
      type: int
      required: true
      description: |
          Main PLL division factor for PLLSAI2CLK
      enum:
        - 2
        - 4
        - 6
        - 8

    div-q:
      type: int
      required: false
      description: |
          Main PLL (PLL) division factor for USB OTG FS, SDMMC and random number
          generator clocks.
          Valid range: 2 - 15