/*
 * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <freq.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/timer/nuclei-systimer.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/clock/gd32vf103-clocks.h>
#include <zephyr/dt-bindings/reset/gd32vf103.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu: cpu@0 {
			clock-frequency = <DT_FREQ_M(108)>;
			mcause-exception-mask = <0x7ff>;
			compatible = "nuclei,bumblebee";
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&eclic>;
		ranges;

		systimer: timer@d1000000 {
			compatible = "nuclei,systimer";
			reg = <0xd1000000 0x10000>;
			interrupts = <3 0>, <7 0>;
			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
		};

		eclic: interrupt-controller@d2000000 {
			compatible = "nuclei,eclic";
			#address-cells = <0>;
			#interrupt-cells = <2>;
			interrupt-controller;
			reg =  <0xd2000000 0x0001
				0xd2000004 0x0004
				0xd200000b 0x0001
				0xd2001000 0x1000>;
		};

		rcu: reset-clock-controller@40021000 {
			compatible = "gd,gd32-rcu";
			reg = <0x40021000 0x400>;
			status = "okay";

			cctl: clock-controller {
				compatible = "gd,gd32-cctl";
				#clock-cells = <1>;
				status = "okay";
			};

			rctl: reset-controller {
				compatible = "gd,gd32-rctl";
				#reset-cells = <1>;
				status = "okay";
			};
		};

		fmc: flash-controller@40022000 {
			compatible = "gd,gd32-flash-controller";
			reg = <0x40022000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "gd,gd32-nv-flash-v1", "soc-nv-flash";
				write-block-size = <2>;
				max-erase-time-ms = <300>;
				page-size = <DT_SIZE_K(1)>;
			};
		};

		usart0: serial@40013800 {
			compatible = "gd,gd32-usart";
			reg = <0x40013800 0x400>;
			interrupts = <56 0>;
			clocks = <&cctl GD32_CLOCK_USART0>;
			resets = <&rctl GD32_RESET_USART0>;
			status = "disabled";
		};

		usart1: serial@40004400 {
			compatible = "gd,gd32-usart";
			reg = <0x40004400 0x400>;
			interrupts = <57 0>;
			clocks = <&cctl GD32_CLOCK_USART1>;
			resets = <&rctl GD32_RESET_USART1>;
			status = "disabled";
		};

		usart2: serial@40004800 {
			compatible = "gd,gd32-usart";
			reg = <0x40004800 0x400>;
			interrupts = <58 0>;
			clocks = <&cctl GD32_CLOCK_USART2>;
			resets = <&rctl GD32_RESET_USART2>;
			status = "disabled";
		};

		adc0: adc@40012400 {
			compatible = "gd,gd32-adc";
			reg = <0x40012400 0x400>;
			interrupts = <37 0>;
			clocks = <&cctl GD32_CLOCK_ADC0>;
			resets = <&rctl GD32_RESET_ADC0>;
			channels = <16>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		adc1: adc@40012800 {
			compatible = "gd,gd32-adc";
			reg = <0x40012800 0x400>;
			interrupts = <37 0>;
			clocks = <&cctl GD32_CLOCK_ADC1>;
			resets = <&rctl GD32_RESET_ADC1>;
			channels = <16>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		dac: dac@40007400 {
			compatible = "gd,gd32-dac";
			reg = <0x40007400 0x400>;
			clocks = <&cctl GD32_CLOCK_DAC>;
			resets = <&rctl GD32_RESET_DAC>;
			num-channels = <2>;
			status = "disabled";
			#io-channel-cells = <1>;
		};

		i2c0: i2c@40005400 {
			compatible = "gd,gd32-i2c";
			reg = <0x40005400 0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <50 0>, <51 0>;
			interrupt-names = "event", "error";
			clocks = <&cctl GD32_CLOCK_I2C0>;
			resets = <&rctl GD32_RESET_I2C0>;
			status = "disabled";
		};

		spi0: spi@40013000 {
			compatible = "gd,gd32-spi";
			reg = <0x40013000 0x400>;
			interrupts = <54 0>;
			clocks = <&cctl GD32_CLOCK_SPI0>;
			resets = <&rctl GD32_RESET_SPI0>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		spi1: spi@40003800 {
			compatible = "gd,gd32-spi";
			reg = <0x40003800 0x400>;
			interrupts = <55 0>;
			clocks = <&cctl GD32_CLOCK_SPI1>;
			resets = <&rctl GD32_RESET_SPI1>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		afio: afio@40010000 {
			compatible = "gd,gd32-afio";
			reg = <0x40010000 0x400>;
			clocks = <&cctl GD32_CLOCK_AFIO>;
			status = "okay";
		};

		exti: interrupt-controller@40010400 {
			compatible = "gd,gd32-exti";
			#address-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x40010400 0x400>;
			num-lines = <19>;
			interrupts = <25 0>, <26 0>, <27 0>, <28 0>, <29 0>,
				     <42 0>, <59 0>;
			interrupt-names = "line0", "line1", "line2", "line3",
					  "line4", "line5-9", "line10-15";
			status = "okay";
		};

		fwdgt: watchdog@40003000 {
			compatible = "gd,gd32-fwdgt";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdgt: watchdog@40002c00 {
			compatible = "gd,gd32-wwdgt";
			reg = <0x40002C00 0x400>;
			clocks = <&cctl GD32_CLOCK_WWDGT>;
			resets = <&rctl GD32_RESET_WWDGT>;
			interrupts = <0 0>;
			status = "disabled";
		};

		pinctrl: pin-controller@40010800 {
			compatible = "gd,gd32-pinctrl-afio";
			reg = <0x40010800 0x1c00>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "okay";

			gpioa: gpio@40010800 {
				compatible = "gd,gd32-gpio";
				reg = <0x40010800 0x400>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&cctl GD32_CLOCK_GPIOA>;
				resets = <&rctl GD32_RESET_GPIOA>;
				status = "disabled";
			};

			gpiob: gpio@40010c00 {
				compatible = "gd,gd32-gpio";
				reg = <0x40010c00 0x400>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&cctl GD32_CLOCK_GPIOB>;
				resets = <&rctl GD32_RESET_GPIOB>;
				status = "disabled";
			};

			gpioc: gpio@40011000 {
				compatible = "gd,gd32-gpio";
				reg = <0x40011000 0x400>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&cctl GD32_CLOCK_GPIOC>;
				resets = <&rctl GD32_RESET_GPIOC>;
				status = "disabled";
			};

			gpiod: gpio@40011400 {
				compatible = "gd,gd32-gpio";
				reg = <0x40011400 0x400>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&cctl GD32_CLOCK_GPIOD>;
				resets = <&rctl GD32_RESET_GPIOD>;
				status = "disabled";
			};

			gpioe: gpio@40011800 {
				compatible = "gd,gd32-gpio";
				reg = <0x40011800 0x400>;
				gpio-controller;
				#gpio-cells = <2>;
				clocks = <&cctl GD32_CLOCK_GPIOE>;
				resets = <&rctl GD32_RESET_GPIOE>;
				status = "disabled";
			};
		};

		timer0: timer@40012c00 {
			compatible = "gd,gd32-timer";
			reg = <0x40012c00 0x400>;
			interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			clocks = <&cctl GD32_CLOCK_TIMER0>;
			resets = <&rctl GD32_RESET_TIMER0>;
			is-advanced;
			channels = <4>;
			status = "disabled";

			pwm {
				compatible = "gd,gd32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer1: timer@40000000 {
			compatible = "gd,gd32-timer";
			reg = <0x40000000 0x400>;
			interrupts = <47 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER1>;
			resets = <&rctl GD32_RESET_TIMER1>;
			channels = <4>;
			status = "disabled";

			pwm {
				compatible = "gd,gd32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer2: timer@40000400 {
			compatible = "gd,gd32-timer";
			reg = <0x40000400 0x400>;
			interrupts = <48 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER2>;
			resets = <&rctl GD32_RESET_TIMER2>;
			channels = <4>;
			status = "disabled";

			pwm {
				compatible = "gd,gd32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer3: timer@40000800 {
			compatible = "gd,gd32-timer";
			reg = <0x40000800 0x400>;
			interrupts = <49 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER3>;
			resets = <&rctl GD32_RESET_TIMER3>;
			channels = <4>;
			status = "disabled";

			pwm {
				compatible = "gd,gd32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer4: timer@40000c00 {
			compatible = "gd,gd32-timer";
			reg = <0x40000c00 0x400>;
			interrupts = <69 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER4>;
			resets = <&rctl GD32_RESET_TIMER4>;
			channels = <4>;
			status = "disabled";

			pwm {
				compatible = "gd,gd32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timer5: timer@40001000 {
			compatible = "gd,gd32-timer";
			reg = <0x40001000 0x400>;
			interrupts = <73 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER5>;
			resets = <&rctl GD32_RESET_TIMER5>;
			channels = <0>;
			status = "disabled";
		};

		timer6: timer@40001400 {
			compatible = "gd,gd32-timer";
			reg = <0x40001400 0x400>;
			interrupts = <74 0>;
			interrupt-names = "global";
			clocks = <&cctl GD32_CLOCK_TIMER6>;
			resets = <&rctl GD32_RESET_TIMER6>;
			channels = <0>;
			status = "disabled";
		};

		dma0: dma@40020000 {
			compatible = "gd,gd32-dma";
			reg = <0x40020000 0x400>;
			interrupts = <30 0>, <31 0>, <32 0>, <33 0>,
				     <34 0>, <35 0>, <36 0>;
			clocks = <&cctl GD32_CLOCK_DMA0>;
			dma-channels = <7>;
			#dma-cells = <1>;
			status = "disabled";
		};

		dma1: dma@40020400 {
			compatible = "gd,gd32-dma";
			reg = <0x40020400 0x400>;
			interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
				     <79 0>;
			clocks = <&cctl GD32_CLOCK_DMA0>;
			dma-channels = <5>;
			#dma-cells = <1>;
			status = "disabled";
		};
	};
};