/*
 * Copyright (c) 2019,2022 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <xtensa/intel/intel_adsp_cavs.dtsi>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx6";
			reg = <0>;
			i-cache-line-size = <64>;
			d-cache-line-size = <64>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx6";
			reg = <1>;
		};
	};

	sram0: memory@be000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0xbe000000 DT_SIZE_K(1920)>;
	};

	sram1: memory@be800000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0xbe800000 DT_SIZE_K(64)>;
	};

	soc {
		shim: shim@71f00 {
			compatible = "intel,adsp-shim";
			reg = <0x71f00 0x100>;
		};

		mem_window0: mem_window@71a00 {
			compatible = "intel,adsp-mem-window";
			reg = <0x71a00 0x8>;
			offset = <0x4000>;
			memory = <&sram0>;
			initialize;
		};
		mem_window1: mem_window@71a08 {
			compatible = "intel,adsp-mem-window";
			reg = <0x71a08 0x8>;
			memory = <&sram0>;
		};

		mem_window2: mem_window@71a10 {
			compatible = "intel,adsp-mem-window";
			reg = <0x71a10 0x8>;
			memory = <&sram0>;
		};

		mem_window3: mem_window@71a18 {
			compatible = "intel,adsp-mem-window";
			reg = <0x71a18 0x8>;
			memory = <&sram0>;
		};

		timer: timer {
			compatible = "intel,adsp-timer";
			syscon = <&shim>;
		};

		l2lm: l2lm@71d00 {
			compatible = "intel,cavs-l2lm";
			reg = <0x71d00 0x20>;
		};

		core_intc: core_intc@0 {
			compatible = "cdns,xtensa-core-intc";
			reg = <0x00 0x400>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		cavs_intc0: cavs@78800  {
			compatible = "intel,cavs-intc";
			reg = <0x78800 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <6 0 0>;
			interrupt-parent = <&core_intc>;
		};

		cavs_intc1: cavs@78810  {
			compatible = "intel,cavs-intc";
			reg = <0x78810 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0xA 0 0>;
			interrupt-parent = <&core_intc>;
		};

		cavs_intc2: cavs@78820  {
			compatible = "intel,cavs-intc";
			reg = <0x78820 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0XD 0 0>;
			interrupt-parent = <&core_intc>;
		};

		cavs_intc3: cavs@78830  {
			compatible = "intel,cavs-intc";
			reg = <0x78830 0x10>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <0x10 0 0>;
			interrupt-parent = <&core_intc>;
		};

		adsp_idc: idc@1200 {
			compatible = "intel,adsp-idc";
			reg = <0x1200 0x80>;
			interrupts = <8 0 0>;
			interrupt-parent = <&cavs_intc0>;
		};

		tlb: tlb@3000 {
			compatible = "intel,adsp-tlb";
			reg = <0x3000 0x1000>;
			paddr-size = <11>;
		};
	};
};