diff --git a/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt b/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt
new file mode 100644
index 0000000..f75aec6
--- /dev/null
+++ b/arch/riscv/custom/openhwgroup/cva6/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
diff --git a/arch/riscv/custom/openhwgroup/cva6/cva6_csr.h b/arch/riscv/custom/openhwgroup/cva6/cva6_csr.h
new file mode 100644
index 0000000..09edcee
--- /dev/null
+++ b/arch/riscv/custom/openhwgroup/cva6/cva6_csr.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * @file
+ * OpenHwGroup CVA6 declarations
+ */
+
+#ifndef ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_
+#define ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CVA6 provides two custom CSRs for cache management:
+ * CSR 7C1 controls the data cache, CSR 7C0 controls the instruction cache.
+ * The least significant bit of the CSRs can be written to enable or disable the cache.
+ * Writing a value of 1 means enabling the cache, writing 0 disables it.
+ * After reset, both caches are enabled by default.
+ *
+ */
+
+#define CVA6_DCACHE 0x7C1
+#define CVA6_ICACHE 0x7C0
+
+#define CVA6_DCACHE_ENABLE  0x1
+#define CVA6_DCACHE_DISABLE 0x0
+
+#define CVA6_ICACHE_ENABLE  0x1
+#define CVA6_ICACHE_DISABLE 0x0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_ARCH_RISCV_CUSTOM_OPENHWGROUP_CVA6_CSR_H_ */
diff --git a/soc/openhwgroup/cva6/cva6.h b/soc/openhwgroup/cva6/cva6.h
deleted file mode 100644
index e728eb7..0000000
--- a/soc/openhwgroup/cva6/cva6.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2024, CISPA Helmholtz Center for Information Security
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * @file
- * OpenHwGroup CVA6 declarations
- */
-
-#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
-#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * CVA6 provides two custom CSRs for cache management:
- * CSR 7C1 controls the data cache, CSR 7C0 controls the instruction cache.
- * The least significant bit of the CSRs can be written to enable or disable the cache.
- * Writing a value of 1 means enabling the cache, writing 0 disables it.
- * After reset, both caches are enabled by default.
- *
- */
-
-#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1
-#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0
-
-#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE  0x1
-#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0
-
-#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE  0x1
-#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */
diff --git a/soc/openhwgroup/cva6/soc_cache_management.c b/soc/openhwgroup/cva6/soc_cache_management.c
index cb37c55..e456f63 100644
--- a/soc/openhwgroup/cva6/soc_cache_management.c
+++ b/soc/openhwgroup/cva6/soc_cache_management.c
@@ -9,16 +9,16 @@
 #include <zephyr/arch/riscv/csr.h>
 #include <zephyr/kernel.h>
 
-#include "cva6.h"
+#include <cva6_csr.h>
 
 void __weak arch_dcache_enable(void)
 {
-	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE);
+	csr_write(CVA6_DCACHE, CVA6_DCACHE_ENABLE);
 }
 
 void __weak arch_dcache_disable(void)
 {
-	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
+	csr_write(CVA6_DCACHE, CVA6_DCACHE_DISABLE);
 }
 
 int __weak arch_dcache_flush_all(void)
@@ -66,12 +66,12 @@
 
 void __weak arch_icache_enable(void)
 {
-	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
+	csr_write(CVA6_ICACHE, CVA6_ICACHE_ENABLE);
 }
 
 void __weak arch_icache_disable(void)
 {
-	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
+	csr_write(CVA6_ICACHE, CVA6_ICACHE_DISABLE);
 }
 
 int __weak arch_icache_flush_all(void)