/*
 * Copyright (c) 2021 Linaro Limited
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/*
 * Warning: This overlay performs configuration from clean sheet.
 * It is assumed that it is applied after clear_clocks.overlay file.
 */

&clk_hse {
	hse-bypass;
	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
	status = "okay";
};

&pll {
	div-m = <4>;
	mul-n = <275>;
	div-p = <1>;
	div-q = <4>;
	div-r = <2>;
	clocks = <&clk_hse>;
	status = "okay";
};

&rcc {
	clocks = <&pll>;
	clock-frequency = <DT_FREQ_M(550)>;
	d1cpre = <1>;
	hpre = <2>;    /* HCLK: 275   MHz */
	d1ppre = <2>;  /* APB1: 137.5 MHz */
	d2ppre1 = <2>; /* APB2: 137.5 MHz */
	d2ppre2 = <2>; /* APB3: 137.5 MHz */
	d3ppre = <2>;  /* APB4: 137.5 MHz */
};