tree a43716ca977b28003c8d09f69cef8de66599acae
parent 1feaea34aa5d5d034da3932d3c216ea126813203
author Thomas Stranger <thomas.stranger@outlook.com> 1656448103 +0200
committer Carles Cufí <carles.cufi@nordicsemi.no> 1656945684 +0200

tests/drivers/clock_control: stm32 add adc-pll_p overlays(g0,g4,wl)

For the STM32G0, STM32G4, and STM32WL enable the adc node in one
configuration, and select the PLL_P output as its clock source.
PLL_P divider is chosen to be 20 to make sure it's a unique frequency.
- g0, and g4 have pll as sysclk
- wl has hse as sysclock

The test configurations and the overlay-files are renamed accordingly.
All overlays that don't specify an alternative clock source still
make sure that the adc node is "okay" to be able to perform basic test.
The basic test only turns on and off the gate clock without checking the
frequency.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>