/*
 * Copyright (c) 2024 Microchip Technology Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <freq.h>
#include <mem.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4";
			reg = <0>;
		};
	};

	soc {
		ecs: ecs@4000fc00 {
			reg = <0x4000fc00 0x200>;
			status = "disabled";
		};
		pcr: pcr@40080100 {
			reg = <0x40080100 0x100 0x4000a400 0x100>;
			reg-names = "pcrr", "vbatr";
			interrupts = <174 0>;
			status = "disabled";
		};
		ecia: ecia@4000e000 {
			reg = <0x4000e000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			status = "disabled";

			ranges = <0x0 0x4000e000 0x400>;

			girq8: girq8@0 {
				reg = <0x0 0x14>;
				interrupts = <0 1>;
				status = "disabled";
			};
			girq9: girq9@14 {
				reg = <0x14 0x14>;
				interrupts = <1 1>;
				status = "disabled";
			};
			girq10: girq10@28 {
				reg = <0x28 0x14>;
				interrupts = <2 1>;
				status = "disabled";
			};
			girq11: girq11@3c {
				reg = <0x3c 0x14>;
				interrupts = <3 1>;
				status = "disabled";
			};
			girq12: girq12@50 {
				reg = <0x50 0x14>;
				interrupts = <4 1>;
				status = "disabled";
			};
			girq13: girq13@64 {
				reg = <0x64 0x14>;
				interrupts = <5 1>;
				status = "disabled";
			};
			girq14: girq14@78 {
				reg = <0x78 0x14>;
				interrupts = <6 1>;
				status = "disabled";
			};
			girq15: girq15@8c {
				reg = <0x8c 0x14>;
				interrupts = <7 1>;
				status = "disabled";
			};
			girq16: girq16@a0 {
				reg = <0xa0 0x14>;
				interrupts = <8 1>;
				status = "disabled";
			};
			girq17: girq17@b4 {
				reg = <0xb4 0x14>;
				interrupts = <9 1>;
				status = "disabled";
			};
			girq18: girq18@c8 {
				reg = <0xc8 0x14>;
				interrupts = <10 1>;
				status = "disabled";
			};
			girq19: girq19@dc {
				reg = <0xdc 0x14>;
				interrupts = <11 1>;
				status = "disabled";
			};
			girq20: girq20@f0 {
				reg = <0xf0 0x14>;
				interrupts = <12 1>;
				status = "disabled";
			};
			girq21: girq21@104 {
				reg = <0x104 0x14>;
				interrupts = <13 1>;
				status = "disabled";
			};
			girq22: girq22@118 {
				reg = <0x118 0x14>;
				interrupts = <255 0>;
				status = "disabled";
			};
			girq23: girq23@12c {
				reg = <0x12c 0x14>;
				interrupts = <14 1>;
				status = "disabled";
			};
			girq24: girq24@140 {
				reg = <0x140 0x14>;
				interrupts = <15 1>;
				status = "disabled";
			};
			girq25: girq25@154 {
				reg = <0x154 0x14>;
				interrupts = <16 1>;
				status = "disabled";
			};
			girq26: girq26@168 {
				reg = <0x168 0x14>;
				interrupts = <17 1>;
				status = "disabled";
			};
		};
		pinctrl: pin-controller@40081000 {
			compatible = "microchip,mec5-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40081000 0x1000>;

			gpio_000_036: gpio@40081000 {
				reg = < 0x40081000 0x80 0x40081300 0x04
					0x40081380 0x04 0x400813fc 0x04>;
				interrupts = <3 2>;
				gpio-controller;
				port-id = <0>;
				girq-id = <11>;
				#gpio-cells=<2>;
			};
			gpio_040_076: gpio@40081080 {
				reg = < 0x40081080 0x80 0x40081304 0x04
					0x40081384 0x04 0x400813f8 0x4>;
				interrupts = <2 2>;
				gpio-controller;
				port-id = <1>;
				girq-id = <10>;
				#gpio-cells=<2>;
			};
			gpio_100_136: gpio@40081100 {
				reg = < 0x40081100 0x80 0x40081308 0x04
					0x40081388 0x04 0x400813f4 0x04>;
				gpio-controller;
				interrupts = <1 2>;
				port-id = <2>;
				girq-id = <9>;
				#gpio-cells=<2>;
			};
			gpio_140_176: gpio@40081180 {
				reg = < 0x40081180 0x80 0x4008130c 0x04
					0x4008138c 0x04 0x400813f0 0x04>;
				gpio-controller;
				interrupts = <0 2>;
				port-id = <3>;
				girq-id = <8>;
				#gpio-cells=<2>;
			};
			gpio_200_236: gpio@40081200 {
				reg = < 0x40081200 0x80 0x40081310 0x04
					0x40081390 0x04 0x400813ec 0x04>;
				gpio-controller;
				interrupts = <4 2>;
				port-id = <4>;
				girq-id = <12>;
				#gpio-cells=<2>;
			};
			gpio_240_276: gpio@40081280 {
				reg = < 0x40081280 0x80 0x40081314 0x04
					0x40081394 0x04 0x400813e8 0x04>;
				gpio-controller;
				interrupts = <17 2>;
				port-id = <5>;
				girq-id = <26>;
				#gpio-cells=<2>;
			};
		};
		uart0: uart@400f2400 {
			reg = <0x400f2400 0x400>;
			interrupts = <40 1>;
			status = "disabled";
		};
		uart1: uart@400f2800 {
			reg = <0x400f2800 0x400>;
			interrupts = <41 1>;
			status = "disabled";
		};
		wdog: watchdog@40000400 {
			reg = <0x40000400 0x400>;
			interrupts = <171 0>;
			status = "disabled";
		};
		rtimer: timer@40007400 {
			reg = <0x40007400 0x10>;
			interrupts = <111 0>;
			clock-frequency = <32768>;
			max-value = <0xffffffff>;
			status = "disabled";
		};
		timer0: timer@40000c00 {
			reg = <0x40000c00 0x20>;
			interrupts = <136 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffff>;
			status = "disabled";
		};
		timer1: timer@40000c20 {
			reg = <0x40000c20 0x20>;
			interrupts = <137 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffff>;
			status = "disabled";
		};
		timer2: timer@40000c40 {
			reg = <0x40000c40 0x20>;
			interrupts = <138 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffff>;
			status = "disabled";
		};
		timer3: timer@40000c60 {
			reg = <0x40000c60 0x20>;
			interrupts = <139 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffff>;
			status = "disabled";
		};
		timer4: timer@40000c80 {
			reg = <0x40000c80 0x20>;
			interrupts = <140 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffffffff>;
			status = "disabled";
		};
		timer5: timer@40000ca0 {
			reg = <0x40000ca0 0x20>;
			interrupts = <141 0>;
			clock-frequency = <48000000>;
			prescaler = <0>;
			max-value = <0xffffffff>;
			status = "disabled";
		};
		cntr0: timer@40000d00 {
			reg = <0x40000d00 0x20>;
			interrupts = <142 0>;
			status = "disabled";
		};
		cntr1: timer@40000d20 {
			reg = <0x40000d20 0x20>;
			interrupts = <143 0>;
			status = "disabled";
		};
		cntr2: timer@40000d40 {
			reg = <0x40000d40 0x20>;
			interrupts = <144 0>;
			status = "disabled";
		};
		cntr3: timer@40000d60 {
			reg = <0x40000d60 0x20>;
			interrupts = <145 0>;
			status = "disabled";
		};
		cctmr0: timer@40001000 {
			reg = <0x40001000 0x40>;
			interrupts = <146 0>, <147 0>, <148 0>, <149 0>,
				     <150 0>, <151 0>, <152 0>, <153 0>,
				     <154 0>;
			status = "disabled";
		};
		hibtimer0: timer@40009800 {
			reg = <0x40009800 0x20>;
			interrupts = <112 0>;
			status = "disabled";
		};
		hibtimer1: timer@40009820 {
			reg = <0x40009820 0x20>;
			interrupts = <113 0>;
			status = "disabled";
		};
		weektmr0: timer@4000ac80 {
			reg = <0x4000ac80 0x80>;
			interrupts = <114 0>, <115 0>, <116 0>,
				     <117 0>, <118 0>;
			status = "disabled";
		};
		rtc0: rtc@400f5000 {
			reg = <0x400f5000 0x100>;
			interrupts = <119 3>, <120 3>;
			status = "disabled";
		};
		bbram: bb-ram@4000a800 {
			reg = <0x4000a800 0x100>;
			reg-names = "memory";
			status = "disabled";
		};
		vci0: vci@4000ae00 {
			reg = <0x4000ae00 0x40>;
			interrupts = <121 0>, <122 0>, <123 0>,
				     <124 0>, <125 0>;
			status = "disabled";
		};
		i2c_smb_0: i2c@40004000 {
			reg = <0x40004000 0x80>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <20 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		i2c_smb_1: i2c@40004400 {
			reg = <0x40004400 0x80>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <21 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		i2c_smb_2: i2c@40004800 {
			reg = <0x40004800 0x80>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <22 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		i2c_smb_3: i2c@40004c00 {
			reg = <0x40004C00 0x80>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <23 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		i2c_smb_4: i2c@40005000 {
			reg = <0x40005000 0x80>;
			clock-frequency = <I2C_BITRATE_STANDARD>;
			interrupts = <158 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		ps2_0: ps2@40009000 {
			reg = <0x40009000 0x40>;
			interrupts = <100 1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		pwm0: pwm@40005800 {
			reg = <0x40005800 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm1: pwm@40005810 {
			reg = <0x40005810 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm2: pwm@40005820 {
			reg = <0x40005820 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm3: pwm@40005830 {
			reg = <0x40005830 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm4: pwm@40005840 {
			reg = <0x40005840 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm5: pwm@40005850 {
			reg = <0x40005850 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm6: pwm@40005860 {
			reg = <0x40005860 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm7: pwm@40005870 {
			reg = <0x40005870 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		pwm8: pwm@40005880 {
			reg = <0x40005880 0x10>;
			status = "disabled";
			#pwm-cells = <3>;
		};
		tach0: tach@40006000 {
			reg = <0x40006000 0x10>;
			interrupts = <71 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		tach1: tach@40006010 {
			reg = <0x40006010 0x10>;
			interrupts = <72 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		tach2: tach@40006020 {
			reg = <0x40006020 0x10>;
			interrupts = <73 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		tach3: tach@40006030 {
			reg = <0x40006030 0x10>;
			interrupts = <159 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		rpmfan0: rpmfan@4000a000 {
			reg = <0x4000a000 0x80>;
			interrupts = <74 1>, <75 1>;
			status = "disabled";
		};
		rpmfan1: rpmfan@4000a080 {
			reg = <0x4000a080 0x80>;
			interrupts = <76 1>, <77 1>;
			status = "disabled";
		};
		adc0: adc@40007c00 {
			reg = <0x40007c00 0x90>;
			interrupts = <78 0>, <79 0>;
			interrupt-names = "single", "repeat";
			status = "disabled";
			#io-channel-cells = <1>;
			clktime = <32>;
		};
		peci0: peci@40006400 {
			reg = <0x40006400 0x80>;
			interrupts = <70 4>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		qspi0: spi@40070000 {
			reg = <0x40070000 0x400>;
			interrupts = <91 2>;
			clock-frequency = <12000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		prochot0: prochot@40003400 {
			reg = <0x40003400 0x20>;
			interrupts = <87 0>;
			status = "disabled";
		};
		rcid0: rcid@40001400 {
			reg = <0x40001400 0x80>;
			interrupts = <80 0>;
			status = "disabled";
		};
		rcid1: rcid@40001480 {
			reg = <0x40001480 0x80>;
			interrupts = <81 0>;
			status = "disabled";
		};
		rcid2: rcid@40001500 {
			reg = <0x40001500 0x80>;
			interrupts = <82 0>;
			status = "disabled";
		};
		bbled0: bbled@4000b800 {
			reg = <0x4000b800 0x100>;
			interrupts = <83 0>;
			status = "disabled";
		};
		bbled1: bbled@4000b900 {
			reg = <0x4000b900 0x100>;
			interrupts = <84 0>;
			status = "disabled";
		};
		bbled2: bbled@4000ba00 {
			reg = <0x4000ba00 0x100>;
			interrupts = <85 0>;
			status = "disabled";
		};
		bbled3: bbled@4000bb00 {
			reg = <0x4000bb00 0x100>;
			interrupts = <86 0>;
			status = "disabled";
		};
		bclink0: bclink@4000cd00 {
			reg = <0x4000cd00 0x20>;
			interrupts = <96 0>, <97 0>;
			status = "disabled";
		};
		tfdp0: tfdp@40008c00 {
			reg = <0x40008c00 0x10>;
			status = "disabled";
		};
		glblcfg0: glblcfg@400fff00 {
			reg = <0x400fff00 0x40>;
			status = "disabled";
		};
		espi0: espi@400f3400 {
			#address-cells = <1>;
			#size-cells = <1>;
			reg = < 0x400f3400 0x400
				0x400f3800 0x400
				0x400f9c00 0x400>;
			reg-names = "io", "mem", "vw";
			interrupts = <103 3>, <104 3>, <105 3>, <106 3>,
				     <107 3>, <108 3>, <109 3>, <110 2>,
				     <156 3>, <15 3>, <16 3>;
			interrupt-names = "pc", "bm1", "bm2", "ltr", "oob_up",
					  "oob_dn", "fc", "erst", "vw_chan_en",
					  "vwct_0_6", "vwct_7_10";
			status = "disabled";

			/* Devices accessible to the Host via Logical Device mechanism.
			 * Some devices are capable of having their registers mapped to
			 * Host I/O or memory address space. Some devices are capable
			 * of generating Serial IRQ to the Host over eSPI.
			 */
			mbox0: mbox@400f0000 {
				reg = <0x400f0000 0x200>;
				interrupts = <60 3>;
				status = "disabled";
			};
			kbc0: kbc@400f0400 {
				reg = <0x400f0400 0x400>, <0x400f2000 0x400>;
				interrupts = <59 3>, <58 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_ec0: acpi_ec@400f0800 {
				reg = <0x400f0800 0x400>;
				interrupts = <45 3>, <46 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_ec1: acpi_ec@400f0c00 {
				reg = <0x400f0c00 0x400>;
				interrupts = <47 3>, <48 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_ec2: acpi_ec@400f1000 {
				reg = <0x400f1000 0x400>;
				interrupts = <49 3>, <50 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_ec3: acpi_ec@400f1400 {
				reg = <0x400f1400 0x400>;
				interrupts = <51 3>, <52 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_ec4: acpi_ec@400f1800 {
				reg = <0x400f1800 0x400>;
				interrupts = <53 3>, <54 3>;
				interrupt-names = "ibf", "obe";
				status = "disabled";
			};
			acpi_pm1: acpi_pm1@400f1c00 {
				reg = <0x400f1c00 0x400>;
				interrupts = <55 3>, <56 3>, <57 3>;
				interrupt-names = "ctl", "en", "sts";
				status = "disabled";
			};
			glue: glue_logic@400f3c00 {
				reg = <0x400f3c00 0x200>;
				interrupts = <172 1>;
				status = "disabled";
			};
			emi0: emi@400f4000 {
				reg = <0x400f4000 0x400>;
				interrupts = <42 3>;
				status = "disabled";
			};
			emi1: emi@400f4400 {
				reg = <0x400f4400 0x400>;
				interrupts = <43 3>;
				status = "disabled";
			};
			emi2: emi@400f4800 {
				reg = <0x400f4800 0x400>;
				interrupts = <44 3>;
				status = "disabled";
			};
			/* Capture Host writes to a 4-byte I/O range
			 * plus a one byte alias I/O location which maps
			 * to one of the 4-byte locations.
			 */
			p80bd0: p80bd@400f8000 {
				reg = <0x400f8000 0x400>;
				interrupts = <62 0>;
				status = "disabled";
			};
		};
		/* eSPI target attached flash controller.
		 * When this device is fully activated via its driver, it takes
		 * ownership of the QSPI controller. EC access to QSPI
		 * registers is discarded by hardware.
		 */
		espi_taf0: espi_taf@40008000 {
			reg = <0x40008000 0x400>, <0x40070000 0x400>, <0x40071000 0x400>;
			reg-names = "tafbr", "tafqspi", "tafcomm";
			interrupts = <166 3>, <167 3>;
			interrupt-names = "done", "err";
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};

&systick {
	status = "disabled";
};