boards/arm/bl5340_dvk/bl5340_dvk_shared_sram_planning_conf.dts

/*
 * Copyright (c) 2019 Nordic Semiconductor ASA
 * Copyright (c) 2021 Laird Connectivity
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/* Default shared SRAM planning when building for BL5340 DVK.
 * This file is included by both nRF5340 CPUAPP (Application MCU)
 * and nRF5340 CPUNET (Network MCU).
 * - 64 kB SRAM allocated as Shared memory (sram0_shared)
 * - Region defined after the image SRAM of Application MCU
 */

/ {
	chosen {
		/* shared memory reserved for the inter-processor communication */
		zephyr,ipc_shm = &sram0_shared;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		sram0_shared: memory@20070000 {
			/* SRAM allocated to shared memory */
			reg = <0x20070000 0x10000>;
		};
	};
};