boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1.dts

/*
 * Copyright (c) 2019, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <nxp/nxp_lpc55S6x_ns.dtsi>
#include "lpcxpresso55s69.dtsi"

/ {
	model = "NXP LPCXpresso55S69 board";
	compatible = "nxp,lpc55xxx", "nxp,lpc";

	cpus {
		/delete-node/ cpu@0;
	};

	chosen {
		zephyr,sram = &sram3;
		zephyr,flash = &flash0;
		zephyr,code-partition = &slot1_partition;
		zephyr,entropy = &rng;
	};
};

/*
 * Default for this board is to allocate SRAM3-4 to cpu1 but the
 * application can have an application specific device tree to
 * allocate the SRAM0-4 differently.
 *
 * For example, SRAM0-3 could be allocated to cpu0 with only SRAM4
 * for cpu1. This would require the zephyr,sram chosen value for cpu1
 * to be changed to sram4 and the value of sram0 to have a DT_SIZE_K
 * of 256.
 *
 */
&sram3 {
	compatible = "mmio-sram";
	reg = <0x20030000 DT_SIZE_K(80)>;
};


&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&blue_led {
	status = "okay";
};

&mailbox0 {
	status = "okay";
};