/*
 * Copyright (c) 2022 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	uart0_default: uart0_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 6)>,
				<NRF_PSEL(UART_RX, 0, 8)>,
				<NRF_PSEL(UART_RTS, 0, 7)>,
				<NRF_PSEL(UART_CTS, 0, 11)>;
		};
	};

	uart0_sleep: uart0_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 6)>,
				<NRF_PSEL(UART_RX, 0, 8)>,
				<NRF_PSEL(UART_RTS, 0, 7)>,
				<NRF_PSEL(UART_CTS, 0, 11)>;
			low-power-enable;
		};
	};

	uart1_default: uart1_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 1, 1)>,
				<NRF_PSEL(UART_RX, 1, 2)>;
		};
	};

	uart1_sleep: uart1_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 1, 1)>,
				<NRF_PSEL(UART_RX, 1, 2)>;
			low-power-enable;
		};
	};

	i2c1_default: i2c1_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
				<NRF_PSEL(TWIM_SCL, 0, 13)>;
		};
	};

	i2c1_sleep: i2c1_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 0, 14)>,
				<NRF_PSEL(TWIM_SCL, 0, 13)>;
			low-power-enable;
		};
	};

	qspi_default: qspi_default {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 1, 11)>,
				<NRF_PSEL(QSPI_IO0, 1, 15)>,
				<NRF_PSEL(QSPI_IO1, 1, 14)>,
				<NRF_PSEL(QSPI_IO2, 1, 13)>,
				<NRF_PSEL(QSPI_IO3, 1, 12)>,
				<NRF_PSEL(QSPI_CSN, 1, 10)>;
		};
	};

	qspi_sleep: qspi_sleep {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 1, 11)>,
				<NRF_PSEL(QSPI_IO0, 1, 15)>,
				<NRF_PSEL(QSPI_IO1, 1, 14)>,
				<NRF_PSEL(QSPI_IO2, 1, 13)>,
				<NRF_PSEL(QSPI_IO3, 1, 12)>,
				<NRF_PSEL(QSPI_CSN, 1, 10)>;
			low-power-enable;
		};
	};

};