/*
 * Copyright (c) 2022 Nordic Semiconductor
 * SPDX-License-Identifier: Apache-2.0
 */

&pinctrl {
	pwm0_default: pwm0_default {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 8)>,
				<NRF_PSEL(PWM_OUT1, 1, 6)>,
				<NRF_PSEL(PWM_OUT2, 1, 7)>;
		};
	};

	pwm0_sleep: pwm0_sleep {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 8)>,
				<NRF_PSEL(PWM_OUT1, 1, 6)>,
				<NRF_PSEL(PWM_OUT2, 1, 7)>;
			low-power-enable;
		};
	};

	pwm1_default: pwm1_default {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 15)>;
		};
	};

	pwm1_sleep: pwm1_sleep {
		group1 {
			psels = <NRF_PSEL(PWM_OUT0, 1, 15)>;
			low-power-enable;
		};
	};

	i2c1_default: i2c1_default {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
				<NRF_PSEL(TWIM_SCL, 1, 3)>;
		};
	};

	i2c1_sleep: i2c1_sleep {
		group1 {
			psels = <NRF_PSEL(TWIM_SDA, 1, 2)>,
				<NRF_PSEL(TWIM_SCL, 1, 3)>;
			low-power-enable;
		};
	};

	spi3_default: spi3_default {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 29)>,
				<NRF_PSEL(SPIM_MOSI, 0, 28)>,
				<NRF_PSEL(SPIM_MISO, 0, 26)>;
		};
	};

	spi3_sleep: spi3_sleep {
		group1 {
			psels = <NRF_PSEL(SPIM_SCK, 0, 29)>,
				<NRF_PSEL(SPIM_MOSI, 0, 28)>,
				<NRF_PSEL(SPIM_MISO, 0, 26)>;
			low-power-enable;
		};
	};

	uart0_default: uart0_default {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 12)>,
				<NRF_PSEL(UART_RX, 0, 11)>,
				<NRF_PSEL(UART_RTS, 0, 10)>,
				<NRF_PSEL(UART_CTS, 0, 9)>;
		};
	};

	uart0_sleep: uart0_sleep {
		group1 {
			psels = <NRF_PSEL(UART_TX, 0, 12)>,
				<NRF_PSEL(UART_RX, 0, 11)>,
				<NRF_PSEL(UART_RTS, 0, 10)>,
				<NRF_PSEL(UART_CTS, 0, 9)>;
			low-power-enable;
		};
	};

	qspi_default: qspi_default {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
				<NRF_PSEL(QSPI_IO0, 0, 13)>,
				<NRF_PSEL(QSPI_IO1, 0, 14)>,
				<NRF_PSEL(QSPI_CSN, 0, 18)>;
		};
	};

	qspi_sleep: qspi_sleep {
		group1 {
			psels = <NRF_PSEL(QSPI_SCK, 0, 17)>,
				<NRF_PSEL(QSPI_IO0, 0, 13)>,
				<NRF_PSEL(QSPI_IO1, 0, 14)>,
				<NRF_PSEL(QSPI_CSN, 0, 18)>;
			low-power-enable;
		};
	};

};