boards/riscv/qemu_riscv32/qemu_riscv32_xip-pinctrl.dtsi

/*
 * Copyright (c) 2022 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/dt-bindings/pinctrl/sifive-pinctrl.h>

&pinctrl {
	/* UART0 */
	uart0_rx_default: uart0_rx_default {
		pinmux = <16 SIFIVE_PINMUX_IOF0>;
	};
	uart0_tx_default: uart0_tx_default {
		pinmux = <17 SIFIVE_PINMUX_IOF0>;
	};
};