/*
 * Copyright (c) 2019 Linaro Limited
 * Copyright (c) 2019 Centaur Analytics, Inc
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32wb_clock.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/pwm/stm32_pwm.h>
#include <freq.h>

/ {
	chosen {
		zephyr,entropy = &rng;
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m4f";
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	sram1: memory@20030000 {
		compatible = "zephyr,memory-region", "mmio-sram";
		reg = <0x20030000 0x2800>;
		zephyr,memory-region = "SRAM1";
	};

	sram2: memory@20038000 {
		compatible = "zephyr,memory-region", "mmio-sram";
		reg = <0x20038000 0x5000>;
		zephyr,memory-region = "SRAM2";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			/* Expected clock-frequency on the whole series 32MHz */
			clock-frequency = <DT_FREQ_M(32)>;
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(16)>;
			status = "disabled";
		};

		clk_msi: clk-msi {
			#clock-cells = <0>;
			compatible = "st,stm32-msi-clock";
			msi-range = <6>; /* 4MHz (reset value) */
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "st,stm32-lse-clock";
			clock-frequency = <32768>;
			driving-capability = <0>;
			status = "disabled";
		};

		clk_lsi1: clk-lsi1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};

		clk_lsi2: clk-lsi2 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};

		pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32wb-pll-clock";
			status = "disabled";
		};
	};

	soc {
		flash: flash-controller@58004000 {
			compatible = "st,stm32-flash-controller", "st,stm32wb-flash-controller";
			reg = <0x58004000 0x400>;
			interrupts = <4 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x02000000>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <8>;
				erase-block-size = <4096>;
				/* maximum erase time(ms) for a 4K sector */
				max-erase-time = <25>;
			};
		};

		rcc: rcc@58000000 {
			compatible = "st,stm32wb-rcc";
			#clock-cells = <2>;
			reg = <0x58000000 0x400>;
		};

		exti: interrupt-controller@58000800 {
			compatible = "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x58000800 0x400>;
		};

		pinctrl: pin-controller@48000000 {
			compatible = "st,stm32-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x48000000 0x2000>;

			gpioa: gpio@48000000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
			};

			gpiob: gpio@48000400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
			};

			gpioc: gpio@48000800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
			};

			gpiod: gpio@48000c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48000c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
			};

			gpioe: gpio@48001000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
			};

			gpioh: gpio@48001c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
			};
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002C00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
			interrupts = <0 7>;
			status = "disabled";
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			interrupts = <36 0>;
			status = "disabled";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
			interrupts = <30 0>, <31 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c3: i2c@40005c00 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
			interrupts = <32 0>, <33 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		rtc: rtc@40002800 {
			compatible = "st,stm32-rtc";
			reg = <0x40002800 0x400>;
			interrupts = <41 0>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
			prescaler = <32768>;
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			interrupts = <34 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
			status = "disabled";
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			interrupts = <35 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			status = "disabled";
		};

		lpuart1: serial@40008000 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x40008000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
			interrupts = <37 0>;
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
			interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
			interrupts = <28 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers16: timers@40014400 {
			compatible = "st,stm32-timers";
			reg = <0x40014400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
			interrupts = <25 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers17: timers@40014800 {
			compatible = "st,stm32-timers";
			reg = <0x40014800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
			interrupts = <26 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		adc1: adc@50040000 {
			compatible = "st,stm32-adc";
			reg = <0x50040000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
			interrupts = <18 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			has-temp-channel;
			has-vref-channel;
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
		};

		lptim1: timers@40007c00 {
			compatible = "st,stm32-lptim";
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40007c00 0x400>;
			interrupts = <47 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		dma1: dma@40020000 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020000 0x400>;
			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
			dma-requests = <7>;
			dma-offset = <0>;
			status = "disabled";
		};

		dma2: dma@40020400 {
			compatible = "st,stm32-dma-v2";
			#dma-cells = <3>;
			reg = <0x40020400 0x400>;
			interrupts = <55 0 56 0 57 0 58 0 59 0 60 0 61 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
			dma-requests = <7>;
			dma-offset = <7>;
			status = "disabled";
		};

		dmamux1: dmamux@40020800 {
			compatible = "st,stm32-dmamux";
			#dma-cells = <3>;
			reg = <0x40020800 0x400>;
			interrupts = <62 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x4>;
			dma-channels = <14>;
			dma-generators = <4>;
			dma-requests= <36>;
			status = "disabled";
		};

		usb: usb@40006800 {
			compatible = "st,stm32-usb";
			reg = <0x40006800 0x400>;
			interrupts = <20 0>, <19 0>;
			interrupt-names = "usb", "usbhp";
			num-bidir-endpoints = <8>;
			ram-size = <1024>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
			status = "disabled";
		};

		quadspi: quadspi@a0001000 {
			compatible = "st,stm32-qspi";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			reg = <0xa0001000 0x400>;
			interrupts = <0x32 0x0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x100>;
			status = "disabled";
		};

		rng: rng@58001000 {
			compatible = "st,stm32-rng";
			reg = <0x58001000 0x400>;
			interrupts = <53 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00040000>;
			status = "disabled";
		};
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};