/*
 * Copyright (c) 2023 Antmicro <www.antmicro.com>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-r.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;
	compatible = "renesas,rzt2m-dev";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-r52";
			reg = <1>;
		};
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
		interrupt-parent = <&gic>;
	};

	soc {
		compatible = "renesas,rzt2m-soc";

		interrupt-parent = <&gic>;

		gic: interrupt-controller@94000000 {
			compatible = "arm,gic-v3", "arm,gic";
			reg = <0x94000000 0x10000>,
				<0x94100000 0x80000>;
			interrupt-controller;
			#interrupt-cells = <4>;
			status = "okay";
		};

		cpu0_atcm: memory@0 {
			compatible = "mmio-sram";
			reg = <0x00000000 DT_SIZE_K(512)>;
		};

		cpu0_btcm: memory@100000 {
			compatible = "mmio-sram";
			reg = <0x00100000 DT_SIZE_K(64)>;
		};

		sram0: memory@10000000 {
			compatible = "mmio-sram";
			reg = <0x10000000 DT_SIZE_M(2)>;
		};

		gsc: gsc@c0060000 {
			/* Global System Counter */
			compatible = "syscon";
			reg = <0xc0060000 0x30>;
			reg-io-width = <4>;
		};

		prcrn: prcrn@80281a10 {
			/* Non-safety area */
			compatible = "syscon";
			reg = <0x80281a10 0x10>;
			reg-io-width = <4>;
		};

		prcrs: prcrs@81281a00 {
			/* Safety area */
			compatible = "syscon";
			reg = <0x81281a00 0x10>;
			reg-io-width = <4>;
		};

		sckcr: sckcr@81280004 {
			/* System Clock Control Register*/
			compatible = "syscon";
			reg = <0x80280000 0x20>;
			reg-io-width = <4>;
		};

		sckcr2: sckcr2@81280004 {
			/* System Clock Control Register 2 */
			compatible = "syscon";
			reg = <0x81280004 0x1a>;
			reg-io-width = <4>;
		};

		uart0: serial@80001000 {
			compatible = "renesas,rzt2m-uart";
			reg = <0x80001000 0x1000>;
			current-speed = <115200>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "rx_err", "rx", "tx", "tx_end";
			status = "disabled";
		};

		uart3: serial@80001c00 {
			compatible = "renesas,rzt2m-uart";
			reg = <0x80001c00 0x1000>;
			current-speed = <115200>;
			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
			interrupt-names = "rx_err", "rx", "tx", "tx_end";
			status = "disabled";
		};

		pinctrl: pinctrl@800a0000 {
			compatible = "renesas,rzt2m-pinctrl";
			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
			reg-names = "port_nsr", "ptadr";
			#address-cells = <1>;
			#size-cells = <0>;

			gpio19: gpio@13 {
				compatible = "renesas,rzt2m-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <8>;
				reg = <0x13>;
			};

			gpio20: gpio@14 {
				compatible = "renesas,rzt2m-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <8>;
				reg = <0x14>;
			};

			gpio23: gpio@17 {
				compatible = "renesas,rzt2m-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				ngpios = <8>;
				reg = <0x17>;
			};
		};
	};
};