# Copyright (c) 2023, STMicroelectronics
# SPDX-License-Identifier: Apache-2.0

description: |
  PLL node binding for STM32WBA devices

  It can be used to describe PLL1

  This PLL could take one of clk_hse or clk_hsi as input clock, with
  an input frequency from 4 to 16 MHz. PLLM factor is used to set the input
  clock in this acceptable range.

  PLL1 can have up to 3 output clocks and for each output clock, the
  frequency can be computed with the following formula:

    f(PLL_P) = f(VCO clock) / PLLP
    f(PLL_Q) = f(VCO clock) / PLLQ
    f(PLL_R) = f(VCO clock) / PLLR

      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)

  Note: VCOx frequency range is 128 to 544 MHz. To reduce the power consumption,
        it is recommended to configure the VCO to the lowest frequency.

  The PLL output frequency must not exceed 100 MHz.

compatible: "st,stm32wba-pll-clock"

include: [clock-controller.yaml, base.yaml]

properties:

  "#clock-cells":
    const: 0

  clocks:
    required: true

  div-m:
    type: int
    required: true
    description: |
        Prescaler for PLLx
        input clock
        Valid range: 1 - 8

  mul-n:
    type: int
    required: true
    description: |
        PLLx multiplication factor for VCO
        Valid range: 4 - 512

  div-q:
    type: int
    description: |
        PLLx DIVQ division factor
        Valid range: 1 - 128

  div-r:
    type: int
    required: true
    description: |
        PLLx DIVR division factor
        Valid range: 1 - 128