# Raytac MDBT53-DB-40 nRF5340 board configuration

# Copyright (c) 2019-2020 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

if  BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

config BOARD
	default "raytac_mdbt53_db_40_nrf5340_cpuapp"

# By default, if we build for a Non-Secure version of the board,
# enable building with TF-M as the Secure Execution Environment.
config BUILD_WITH_TFM
	default n if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

if BUILD_WITH_TFM

# By default, if we build with TF-M, instruct build system to
# flash the combined TF-M (Secure) & Zephyr (Non Secure) image
config TFM_FLASH_MERGED_BINARY
	bool
	default n

endif # BUILD_WITH_TFM

# Code Partition:
#
# For the secure version of the board the firmware is linked at the beginning
# of the flash, or into the code-partition defined in DT if it is intended to
# be loaded by MCUboot. If the secure firmware is to be combined with a non-
# secure image (TRUSTED_EXECUTION_SECURE=y), the secure FW image shall always
# be restricted to the size of its code partition.
#
# For the non-secure version of the board, the firmware
# must be linked into the code-partition (non-secure) defined in DT, regardless.
# Apply this configuration below by setting the Kconfig symbols used by
# the linker according to the information extracted from DT partitions.

# SRAM Partition:
#
# If the secure firmware is to be combined with a non-secure image
# (TRUSTED_EXECUTION_SECURE=y), the secure FW image SRAM shall always
# be restricted to the secure image SRAM partition (sram-secure-partition).
# Otherwise (if TRUSTED_EXECUTION_SECURE is not set) the whole zephyr,sram
# may be used by the image.
#
# For the non-secure version of the board, the firmware image SRAM is
# always restricted to the allocated non-secure SRAM partition.
#
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition

if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE

config FLASH_LOAD_SIZE
	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))

config SRAM_SIZE
	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM_PARTITION),0,K)

endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP && TRUSTED_EXECUTION_SECURE

if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

config FLASH_LOAD_OFFSET
	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))

config FLASH_LOAD_SIZE
	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))

endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

config BOARD
	default "raytac_mdbt53_dv_40_nrf5340_cpunet" if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET

config IPM_NRFX
	default IPM

config MBOX_NRFX_IPC
	default MBOX

if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

choice BT_HCI_BUS_TYPE
	default BT_RPMSG if BT
endchoice

config HEAP_MEM_POOL_SIZE
	default 4096 if BT_RPMSG

endif #  BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP || BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUAPP_NS

if BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET

config BT_CTLR
	default y if BT

endif # BOARD_RAYTAC_MDBT53_DB_40_NRF5340_CPUNET