ext: cc3220sdk: Import HAL for TI CC3220S SoC
The CC3220 SDK provides a peripheral driver library and hardware
register access header files for the Texas Instruments SimpleLink
CC3220S and CC3220SF SoCs.
The current version supported in Zephyr is CC3220 SDK 1.30.01.03,
downloaded from:
http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK
Jira: ZEP-1958
Change-Id: Ib278a6e067a621c589d6efd17cda6f75dc2a9cdb
Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
diff --git a/ext/hal/ti/cc3220sdk/Kbuild b/ext/hal/ti/cc3220sdk/Kbuild
new file mode 100644
index 0000000..6298bf6
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/Kbuild
@@ -0,0 +1,4 @@
+ccflags-$(CONFIG_HAS_CC3220SDK) += -D$(COMPILER)
+# Need to build prcm and utils for PRCMCC3220MCUInit, which is not in ROM
+obj-$(CONFIG_HAS_CC3220SDK) += driverlib/utils.o
+obj-$(CONFIG_HAS_CC3220SDK) += driverlib/prcm.o
diff --git a/ext/hal/ti/cc3220sdk/Kconfig b/ext/hal/ti/cc3220sdk/Kconfig
new file mode 100644
index 0000000..a7d7943
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/Kconfig
@@ -0,0 +1,11 @@
+# Kconfig - CC3220 SDK HAL configuration
+
+config HAS_CC3220SDK
+ bool
+
+menuconfig CC3220SDK
+ bool "TI CC3220 SDK support"
+ default n
+ depends on HAS_CC3220SDK
+ help
+ Build required peripheral driverlib files from the CC3220 SDK
diff --git a/ext/hal/ti/cc3220sdk/Makefile b/ext/hal/ti/cc3220sdk/Makefile
new file mode 100644
index 0000000..64a41fc
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/Makefile
@@ -0,0 +1,6 @@
+ifdef CONFIG_HAS_CC3220SDK
+ZEPHYRINCLUDE +=-I$(srctree)/ext/hal/ti/cc3220sdk
+ZEPHYRINCLUDE +=-I$(srctree)/ext/hal/ti/cc3220sdk/inc
+ZEPHYRINCLUDE +=-I$(srctree)/ext/hal/ti/cc3220sdk/driverlib
+KBUILD_CFLAGS += -DUSE_CC3200_ROM_DRV_API
+endif # CONFIG_HAS_CC3220SDK
diff --git a/ext/hal/ti/cc3220sdk/README b/ext/hal/ti/cc3220sdk/README
new file mode 100644
index 0000000..669684e
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/README
@@ -0,0 +1,26 @@
+The CC3220 SDK provides a peripheral driver library and hardware
+register access header files for the Texas Instruments SimpleLink
+CC3220S and CC3220SF SoCs.
+
+The current version supported in Zephyr is CC3220 SDK 1.30.01.03,
+downloaded from:
+
+ http://www.ti.com/tool/download/SIMPLELINK-CC3220-SDK
+
+A subset of the files in driverlib/ and inc/ are copied from a
+Linux CC3220 SDK installation without modification.
+
+TI provides the driver library functions burned into ROM at the factory,
+or updated via a service pack patch, thus saving application code space.
+
+Calling driverlib APIs prefixed by "MAP_" will vector to those functions
+already existing in ROM.
+
+For the zephyr shell sample, for example, using these ROM functions
+results in a savings of about 2Kb in code space.
+
+After setting CONFIG_HAS_CC3220SDK=y in Kconfig, most of the
+peripheral driver library functions will be accessible from ROM,
+except for the following modules:
+- driverlib/prcm.c
+- driverlib/utils.c
diff --git a/ext/hal/ti/cc3220sdk/driverlib/cpu.h b/ext/hal/ti/cc3220sdk/driverlib/cpu.h
new file mode 100644
index 0000000..4e8840e
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/cpu.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// cpu.h
+//
+// Prototypes for the CPU instruction wrapper functions.
+//
+//*****************************************************************************
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Prototypes.
+//
+//*****************************************************************************
+extern unsigned long CPUcpsid(void);
+extern unsigned long CPUcpsie(void);
+extern unsigned long CPUprimask(void);
+extern void CPUwfi(void);
+extern unsigned long CPUbasepriGet(void);
+extern void CPUbasepriSet(unsigned long ulNewBasepri);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __CPU_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/flash.h b/ext/hal/ti/cc3220sdk/driverlib/flash.h
new file mode 100644
index 0000000..e9f0a00
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/flash.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// flash.h
+//
+// Prototypes for the flash driver.
+//
+//*****************************************************************************
+
+#ifndef __FLASH_H__
+#define __FLASH_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to FlashProtectSet(), and returned by
+// FlashProtectGet().
+//
+//*****************************************************************************
+typedef enum
+{
+ FlashReadWrite, // Flash can be read and written
+ FlashReadOnly, // Flash can only be read
+ FlashExecuteOnly // Flash can only be executed
+}
+tFlashProtection;
+
+//*****************************************************************************
+//
+// Values passed to FlashIntEnable(), FlashIntDisable() and FlashIntClear() and
+// returned from FlashIntStatus().
+//
+//*****************************************************************************
+#define FLASH_INT_PROGRAM 0x00000002 // Programming Interrupt Mask
+#define FLASH_INT_ACCESS 0x00000001 // Access Interrupt Mask
+#define FLASH_INT_EEPROM 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_INT_VOLTAGE_ERR 0x00000200 // Voltage Error Interrupt Mask
+#define FLASH_INT_DATA_ERR 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_INT_ERASE_ERR 0x00000800 // Erase Error Interrupt Mask
+#define FLASH_INT_PROGRAM_ERR 0x00002000 // Program Verify Error Interrupt Mask
+
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void FlashDisable(void);
+extern long FlashErase(unsigned long ulAddress);
+extern void FlashEraseNonBlocking(unsigned long ulAddress);
+extern long FlashMassErase(void);
+extern void FlashMassEraseNonBlocking(void);
+extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress,
+ unsigned long ulCount);
+extern long FlashProgramNonBlocking(unsigned long *pulData,
+ unsigned long ulAddress,
+ unsigned long ulCount);
+extern void FlashIntRegister(void (*pfnHandler)(void));
+extern void FlashIntUnregister(void);
+extern void FlashIntEnable(unsigned long ulIntFlags);
+extern void FlashIntDisable(unsigned long ulIntFlags);
+extern unsigned long FlashIntStatus(tBoolean bMasked);
+extern void FlashIntClear(unsigned long ulIntFlags);
+extern tFlashProtection FlashProtectGet(unsigned long ulAddress);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __FLASH_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/gpio.h b/ext/hal/ti/cc3220sdk/driverlib/gpio.h
new file mode 100644
index 0000000..d62bae6
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/gpio.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// gpio.h
+//
+// Defines and Macros for GPIO API.
+//
+//*****************************************************************************
+
+#ifndef __GPIO_H__
+#define __GPIO_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// The following values define the bit field for the ucPins argument to several
+// of the APIs.
+//
+//*****************************************************************************
+#define GPIO_PIN_0 0x00000001 // GPIO pin 0
+#define GPIO_PIN_1 0x00000002 // GPIO pin 1
+#define GPIO_PIN_2 0x00000004 // GPIO pin 2
+#define GPIO_PIN_3 0x00000008 // GPIO pin 3
+#define GPIO_PIN_4 0x00000010 // GPIO pin 4
+#define GPIO_PIN_5 0x00000020 // GPIO pin 5
+#define GPIO_PIN_6 0x00000040 // GPIO pin 6
+#define GPIO_PIN_7 0x00000080 // GPIO pin 7
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and
+// returned from GPIODirModeGet.
+//
+//*****************************************************************************
+#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input
+#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and
+// returned from GPIOIntTypeGet.
+//
+//*****************************************************************************
+#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge
+#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge
+#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges
+#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level
+#define GPIO_HIGH_LEVEL 0x00000006 // Interrupt on high level
+
+//*****************************************************************************
+//
+// Values that can be passed to GPIOIntEnable() and GPIOIntDisable() functions
+// in the ulIntFlags parameter.
+//
+//*****************************************************************************
+#define GPIO_INT_DMA 0x00000100
+#define GPIO_INT_PIN_0 0x00000001
+#define GPIO_INT_PIN_1 0x00000002
+#define GPIO_INT_PIN_2 0x00000004
+#define GPIO_INT_PIN_3 0x00000008
+#define GPIO_INT_PIN_4 0x00000010
+#define GPIO_INT_PIN_5 0x00000020
+#define GPIO_INT_PIN_6 0x00000040
+#define GPIO_INT_PIN_7 0x00000080
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulPinIO);
+extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins,
+ unsigned long ulIntType);
+extern void GPIODMATriggerEnable(unsigned long ulPort);
+extern void GPIODMATriggerDisable(unsigned long ulPort);
+extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin);
+extern void GPIOIntEnable(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntDisable(unsigned long ulPort, unsigned long ulIntFlags);
+extern long GPIOIntStatus(unsigned long ulPort, tBoolean bMasked);
+extern void GPIOIntClear(unsigned long ulPort, unsigned long ulIntFlags);
+extern void GPIOIntRegister(unsigned long ulPort,
+ void (*pfnIntHandler)(void));
+extern void GPIOIntUnregister(unsigned long ulPort);
+extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins);
+extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins,
+ unsigned char ucVal);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __GPIO_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/interrupt.h b/ext/hal/ti/cc3220sdk/driverlib/interrupt.h
new file mode 100644
index 0000000..999bd37
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/interrupt.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// interrupt.h
+//
+// Prototypes for the NVIC Interrupt Controller Driver.
+//
+//*****************************************************************************
+
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// A union that describes the entries of the vector table. The union is needed
+// since the first entry is the stack pointer and the remainder are function
+// pointers.
+//
+//*****************************************************************************
+typedef union
+{
+ void (*pfnHandler)(void);
+ unsigned long ulPtr;
+}
+uVectorEntry;
+
+
+//*****************************************************************************
+//
+// Macro to generate an interrupt priority mask based on the number of bits
+// of priority supported by the hardware.
+//
+//*****************************************************************************
+#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF)
+
+//*****************************************************************************
+// Interrupt priority levels
+//*****************************************************************************
+#define INT_PRIORITY_LVL_0 0x00
+#define INT_PRIORITY_LVL_1 0x20
+#define INT_PRIORITY_LVL_2 0x40
+#define INT_PRIORITY_LVL_3 0x60
+#define INT_PRIORITY_LVL_4 0x80
+#define INT_PRIORITY_LVL_5 0xA0
+#define INT_PRIORITY_LVL_6 0xC0
+#define INT_PRIORITY_LVL_7 0xE0
+
+//*****************************************************************************
+//
+// Prototypes for the APIs.
+//
+//*****************************************************************************
+extern tBoolean IntMasterEnable(void);
+extern tBoolean IntMasterDisable(void);
+extern void IntVTableBaseSet(unsigned long ulVtableBase);
+extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void));
+extern void IntUnregister(unsigned long ulInterrupt);
+extern void IntPriorityGroupingSet(unsigned long ulBits);
+extern unsigned long IntPriorityGroupingGet(void);
+extern void IntPrioritySet(unsigned long ulInterrupt,
+ unsigned char ucPriority);
+extern long IntPriorityGet(unsigned long ulInterrupt);
+extern void IntEnable(unsigned long ulInterrupt);
+extern void IntDisable(unsigned long ulInterrupt);
+extern void IntPendSet(unsigned long ulInterrupt);
+extern void IntPendClear(unsigned long ulInterrupt);
+extern void IntPriorityMaskSet(unsigned long ulPriorityMask);
+extern unsigned long IntPriorityMaskGet(void);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __INTERRUPT_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/pin.h b/ext/hal/ti/cc3220sdk/driverlib/pin.h
new file mode 100644
index 0000000..fa946fb
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/pin.h
@@ -0,0 +1,191 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// pin.h
+//
+// Defines and Macros for the pin mux module
+//
+//*****************************************************************************
+
+#ifndef __PIN_H__
+#define __PIN_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+// Macros Defining Pins
+//*****************************************************************************
+
+#define PIN_01 0x00000000
+#define PIN_02 0x00000001
+#define PIN_03 0x00000002
+#define PIN_04 0x00000003
+#define PIN_05 0x00000004
+#define PIN_06 0x00000005
+#define PIN_07 0x00000006
+#define PIN_08 0x00000007
+#define PIN_11 0x0000000A
+#define PIN_12 0x0000000B
+#define PIN_13 0x0000000C
+#define PIN_14 0x0000000D
+#define PIN_15 0x0000000E
+#define PIN_16 0x0000000F
+#define PIN_17 0x00000010
+#define PIN_18 0x00000011
+#define PIN_19 0x00000012
+#define PIN_20 0x00000013
+#define PIN_21 0x00000014
+#define PIN_45 0x0000002C
+#define PIN_46 0x0000002D
+#define PIN_47 0x0000002E
+#define PIN_48 0x0000002F
+#define PIN_49 0x00000030
+#define PIN_50 0x00000031
+#define PIN_52 0x00000033
+#define PIN_53 0x00000034
+#define PIN_55 0x00000036
+#define PIN_56 0x00000037
+#define PIN_57 0x00000038
+#define PIN_58 0x00000039
+#define PIN_59 0x0000003A
+#define PIN_60 0x0000003B
+#define PIN_61 0x0000003C
+#define PIN_62 0x0000003D
+#define PIN_63 0x0000003E
+#define PIN_64 0x0000003F
+
+
+
+//*****************************************************************************
+// Macros that can be used with PinConfigSet(), PinTypeGet(), PinStrengthGet()
+//*****************************************************************************
+
+#define PIN_MODE_0 0x00000000
+#define PIN_MODE_1 0x00000001
+#define PIN_MODE_2 0x00000002
+#define PIN_MODE_3 0x00000003
+#define PIN_MODE_4 0x00000004
+#define PIN_MODE_5 0x00000005
+#define PIN_MODE_6 0x00000006
+#define PIN_MODE_7 0x00000007
+#define PIN_MODE_8 0x00000008
+#define PIN_MODE_9 0x00000009
+#define PIN_MODE_10 0x0000000A
+#define PIN_MODE_11 0x0000000B
+#define PIN_MODE_12 0x0000000C
+#define PIN_MODE_13 0x0000000D
+#define PIN_MODE_14 0x0000000E
+#define PIN_MODE_15 0x0000000F
+// Note : PIN_MODE_255 is a dummy define for pinmux utility code generation
+// PIN_MODE_255 should never be used in any user code.
+#define PIN_MODE_255 0x000000FF
+
+//*****************************************************************************
+// Macros that can be used with PinDirModeSet() and returned from
+// PinDirModeGet().
+//*****************************************************************************
+#define PIN_DIR_MODE_IN 0x00000C00 // Pin is input
+#define PIN_DIR_MODE_OUT 0x00000800 // Pin is output
+#define PIN_DIR_MODE_HW 0x00000000 // Pin is peripheral function
+
+//*****************************************************************************
+// Macros that can be used with PinConfigSet()
+//*****************************************************************************
+#define PIN_STRENGTH_2MA 0x00000020
+#define PIN_STRENGTH_4MA 0x00000040
+#define PIN_STRENGTH_6MA 0x00000060
+
+#define PIN_TYPE_STD 0x00000000
+#define PIN_TYPE_STD_PU 0x00000100
+#define PIN_TYPE_STD_PD 0x00000200
+
+#define PIN_TYPE_OD 0x00000010
+#define PIN_TYPE_OD_PU 0x00000110
+#define PIN_TYPE_OD_PD 0x00000210
+#define PIN_TYPE_ANALOG 0x10000000
+
+//*****************************************************************************
+// Macros that can be used with PinHysteresisSet()
+//*****************************************************************************
+#define PIN_HYSTERESIS_OFF 0x00000000
+#define PIN_HYSTERESIS_10 0x00000004
+#define PIN_HYSTERESIS_20 0x0000000C
+#define PIN_HYSTERESIS_30 0x00000014
+#define PIN_HYSTERESIS_40 0x0000001C
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PinModeSet(unsigned long ulPin, unsigned long ulPinMode);
+extern void PinDirModeSet(unsigned long ulPin, unsigned long ulPinIO);
+extern unsigned long PinDirModeGet(unsigned long ulPin);
+extern unsigned long PinModeGet(unsigned long ulPin);
+extern void PinConfigGet(unsigned long ulPin,unsigned long *pulPinStrength,
+ unsigned long *pulPinType);
+extern void PinConfigSet(unsigned long ulPin,unsigned long ulPinStrength,
+ unsigned long ulPinType);
+extern void PinTypeUART(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeI2C(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeSPI(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeI2S(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeTimer(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeCamera(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeGPIO(unsigned long ulPin,unsigned long ulPinMode,
+ tBoolean bOpenDrain);
+extern void PinTypeADC(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinTypeSDHost(unsigned long ulPin,unsigned long ulPinMode);
+extern void PinHysteresisSet(unsigned long ulHysteresis);
+extern void PinLockLevelSet(unsigned long ulPin, unsigned char ucLevel);
+extern void PinLock(unsigned long ulOutEnable);
+extern void PinUnlock(void);
+extern unsigned long PinToPadGet(unsigned long ulPin);
+extern unsigned long PinFromPadGet(unsigned long ulPad);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__PIN_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/prcm.c b/ext/hal/ti/cc3220sdk/driverlib/prcm.c
new file mode 100644
index 0000000..3019c71
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/prcm.c
@@ -0,0 +1,2715 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+//*****************************************************************************
+//
+//! \addtogroup PRCM_Power_Reset_Clock_Module_api
+//! @{
+//
+//*****************************************************************************
+
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "inc/hw_memmap.h"
+#include "inc/hw_apps_rcm.h"
+#include "inc/hw_gprcm.h"
+#include "inc/hw_hib1p2.h"
+#include "inc/hw_hib3p3.h"
+#include "inc/hw_ocp_shared.h"
+#include "inc/hw_common_reg.h"
+#include "prcm.h"
+#include "interrupt.h"
+#include "cpu.h"
+#include "flash.h"
+#include "utils.h"
+
+
+//*****************************************************************************
+// Macro definition
+//*****************************************************************************
+#define PRCM_SOFT_RESET 0x00000001
+#define PRCM_ENABLE_STATUS 0x00000002
+#define SYS_CLK 80000000
+#define XTAL_CLK 40000000
+
+
+//*****************************************************************************
+// CC3200 does not have a true RTC capability. However, API(s) in this file
+// provide an effective mechanism to support RTC feature in the device.
+//
+// The implementation to support RTC has been kept very simple. A set of
+// HIB Memory Registers in conjunction with Slow Clock Counter are used
+// to render RTC information to users. Core principle of design involves
+// two steps (a) establish an association between user provided wall-clock
+// and slow clock counter. (b) store reference value of this associattion
+// in HIB Registers. This reference value and SCC value are then combined
+// to create real-world calendar time.
+//
+// Across HIB cycles, value stored in HIB Registers is retained and slow
+// clock counter continues to tick, thereby, this arragement is relevant
+// and valid as long as device has a (tickle) battery power.
+//
+// Further, provision also has been made to set an alarm. When it RTC value
+// matches that of set for alarm, an interrupt is generated.
+//
+// HIB MEM REG0 and REG1 are reserved for TI.
+//
+// If RTC feature is not used, then HIB REG2 & REG3 are available to user.
+//
+// Lower half of REG0 is used for TI HW ECO.
+//*****************************************************************************
+#define RTC_U64MSEC_MK(u32Secs, u16Msec) (((unsigned long long)u32Secs << 10)|\
+ (u16Msec & 0x3FF))
+
+#define RTC_SECS_IN_U64MSEC(u64Msec) ((unsigned long)(u64Msec >> 10))
+#define RTC_MSEC_IN_U64MSEC(u64Msec) ((unsigned short)(u64Msec & 0x3FF))
+
+#define RTC_SECS_U32_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG3)
+#define RTC_MSEC_U16_REG_ADDR (HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2+2)
+
+#define RTC_U32SECS_REG (HWREG(RTC_SECS_U32_REG_ADDR))
+#define RTC_U16MSEC_REG (*(unsigned short*)RTC_MSEC_U16_REG_ADDR)
+
+//*****************************************************************************
+// Register Access and Updates
+//
+// Tick of SCC has a resolution of 32768Hz, meaning 1 sec is equal to 32768
+// clock ticks. Ideal way of getting time in millisecond will involve floating
+// point arithmetic (division by 32.768). To avoid this, we simply divide it by
+// 32, which will give a range from 0 -1023(instead of 0-999). To use this
+// output correctly we have to take care of this inaccuracy externally.
+// following wrapper can be used to convert the value from cycles to
+// millisecond:
+//
+// CYCLES_U16MS(cycles) ((cycles *1000)/ 1024),
+//
+// Similarly, before setting the value, it must be first converted (from ms to
+// cycles).
+//
+// U16MS_CYCLES(msec) ((msec *1024)/1000)
+//
+// Note: There is a precision loss of 1 ms with the above scheme.
+//
+//*****************************************************************************
+#define SCC_U64MSEC_GET() (PRCMSlowClkCtrGet() >> 5)
+#define SCC_U64MSEC_MATCH_SET(u64Msec) (PRCMSlowClkCtrMatchSet(u64Msec << 5))
+#define SCC_U64MSEC_MATCH_GET() (PRCMSlowClkCtrMatchGet() >> 5)
+
+//*****************************************************************************
+//
+// Bit: 31 is used to indicate use of RTC. If set as '1', RTC feature is used.
+// Bits: 30 to 26 are reserved, available to software for use
+// Bits: 25 to 16 are used to save millisecond part of RTC reference.
+// Bits: 15 to 0 are being used for HW Changes / ECO
+//
+//*****************************************************************************
+
+//*****************************************************************************
+// Set RTC USE Bit
+//*****************************************************************************
+static void RTCUseSet(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG | (1 << 15);
+
+ UtilsDelay((80*200)/3);
+
+ RTC_U16MSEC_REG = usRegValue;
+}
+
+//*****************************************************************************
+// Checks if RTC-USE bit is set
+//*****************************************************************************
+static tBoolean IsRTCUsed(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ return ((usRegValue & (1 << 15))? true : false);
+}
+
+//*****************************************************************************
+// Read 16-bit mSecs
+//*****************************************************************************
+static unsigned short RTCU16MSecRegRead(void)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ return (usRegValue & 0x3FF);
+}
+
+//*****************************************************************************
+// Write 16-bit mSecs
+//*****************************************************************************
+static void RTCU16MSecRegWrite(unsigned short u16Msec)
+{
+ unsigned short usRegValue;
+
+ usRegValue = RTC_U16MSEC_REG;
+
+ UtilsDelay((80*200)/3);
+
+ RTC_U16MSEC_REG = ((usRegValue & ~0x3FF) |u16Msec);
+}
+
+//*****************************************************************************
+// Read 32-bit Secs
+//*****************************************************************************
+static unsigned long RTCU32SecRegRead(void)
+{
+ return (PRCMHIBRegRead(RTC_SECS_U32_REG_ADDR));
+}
+
+//*****************************************************************************
+// Write 32-bit Secs
+//*****************************************************************************
+static void RTCU32SecRegWrite(unsigned long u32Msec)
+{
+ PRCMHIBRegWrite(RTC_SECS_U32_REG_ADDR, u32Msec);
+}
+
+//*****************************************************************************
+// Macros
+//*****************************************************************************
+#define IS_RTC_USED() IsRTCUsed()
+#define RTC_USE_SET() RTCUseSet()
+
+#define RTC_U16MSEC_REG_RD() RTCU16MSecRegRead()
+#define RTC_U16MSEC_REG_WR(u16Msec) RTCU16MSecRegWrite(u16Msec)
+
+#define RTC_U32SECS_REG_RD() RTCU32SecRegRead()
+#define RTC_U32SECS_REG_WR(u32Secs) RTCU32SecRegWrite(u32Secs)
+
+#define SELECT_SCC_U42BITS(u64Msec) (u64Msec & 0x3ffffffffff)
+
+//*****************************************************************************
+// Global Peripheral clock and rest Registers
+//*****************************************************************************
+static const PRCM_PeriphRegs_t PRCM_PeriphRegsList[] =
+{
+
+ {APPS_RCM_O_CAMERA_CLK_GATING, APPS_RCM_O_CAMERA_SOFT_RESET },
+ {APPS_RCM_O_MCASP_CLK_GATING, APPS_RCM_O_MCASP_SOFT_RESET },
+ {APPS_RCM_O_MMCHS_CLK_GATING, APPS_RCM_O_MMCHS_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_A1_CLK_GATING, APPS_RCM_O_MCSPI_A1_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_A2_CLK_GATING, APPS_RCM_O_MCSPI_A2_SOFT_RESET },
+ {APPS_RCM_O_UDMA_A_CLK_GATING, APPS_RCM_O_UDMA_A_SOFT_RESET },
+ {APPS_RCM_O_GPIO_A_CLK_GATING, APPS_RCM_O_GPIO_A_SOFT_RESET },
+ {APPS_RCM_O_GPIO_B_CLK_GATING, APPS_RCM_O_GPIO_B_SOFT_RESET },
+ {APPS_RCM_O_GPIO_C_CLK_GATING, APPS_RCM_O_GPIO_C_SOFT_RESET },
+ {APPS_RCM_O_GPIO_D_CLK_GATING, APPS_RCM_O_GPIO_D_SOFT_RESET },
+ {APPS_RCM_O_GPIO_E_CLK_GATING, APPS_RCM_O_GPIO_E_SOFT_RESET },
+ {APPS_RCM_O_WDOG_A_CLK_GATING, APPS_RCM_O_WDOG_A_SOFT_RESET },
+ {APPS_RCM_O_UART_A0_CLK_GATING, APPS_RCM_O_UART_A0_SOFT_RESET },
+ {APPS_RCM_O_UART_A1_CLK_GATING, APPS_RCM_O_UART_A1_SOFT_RESET },
+ {APPS_RCM_O_GPT_A0_CLK_GATING , APPS_RCM_O_GPT_A0_SOFT_RESET },
+ {APPS_RCM_O_GPT_A1_CLK_GATING, APPS_RCM_O_GPT_A1_SOFT_RESET },
+ {APPS_RCM_O_GPT_A2_CLK_GATING, APPS_RCM_O_GPT_A2_SOFT_RESET },
+ {APPS_RCM_O_GPT_A3_CLK_GATING, APPS_RCM_O_GPT_A3_SOFT_RESET },
+ {APPS_RCM_O_CRYPTO_CLK_GATING, APPS_RCM_O_CRYPTO_SOFT_RESET },
+ {APPS_RCM_O_MCSPI_S0_CLK_GATING, APPS_RCM_O_MCSPI_S0_SOFT_RESET },
+ {APPS_RCM_O_I2C_CLK_GATING, APPS_RCM_O_I2C_SOFT_RESET }
+
+};
+
+//*****************************************************************************
+//
+//! Performs a software reset of a MCU and associated peripherals
+//!
+//! \param bIncludeSubsystem is \b true to reset associated peripherals.
+//!
+//! This function performs a software reset of a MCU and associated peripherals.
+//! To reset the associated peripheral, the parameter \e bIncludeSubsystem
+//! should be set to \b true.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMMCUReset(tBoolean bIncludeSubsystem)
+{
+ if(bIncludeSubsystem)
+ {
+ //
+ // Reset Apps processor and associated peripheral
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x2;
+ }
+ else
+ {
+ //
+ // Reset Apps processor only
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SOFT_RESET) = 0x1;
+ }
+
+ //
+ // Wait for system to enter hibernate
+ //
+ __asm(" wfi\n");
+
+ //
+ // Infinite loop
+ //
+ while(1)
+ {
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the reason for a reset.
+//!
+//! This function returns the reason(s) for a reset. The reset reason are:-
+//! -\b PRCM_POWER_ON - Device is powering up.
+//! -\b PRCM_LPDS_EXIT - Device is exiting from LPDS.
+//! -\b PRCM_CORE_RESET - Device is exiting soft core only reset
+//! -\b PRCM_MCU_RESET - Device is exiting soft subsystem reset.
+//! -\b PRCM_WDT_RESET - Device was reset by watchdog.
+//! -\b PRCM_SOC_RESET - Device is exting SOC reset.
+//! -\b PRCM_HIB_EXIT - Device is exiting hibernate.
+//!
+//! \return Returns one of the cause defined above.
+//
+//*****************************************************************************
+unsigned long PRCMSysResetCauseGet()
+{
+ unsigned long ulWakeupStatus;
+
+ //
+ // Read the Reset status
+ //
+ ulWakeupStatus = (HWREG(GPRCM_BASE+ GPRCM_O_APPS_RESET_CAUSE) & 0xFF);
+
+ //
+ // For hibernate do additional check.
+ //
+ if(ulWakeupStatus == PRCM_POWER_ON)
+ {
+ if(PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_WAKE_STATUS) & 0x1)
+ {
+ ulWakeupStatus = PRCM_HIB_EXIT;
+
+ if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000280)) == 0x00000280 )
+ {
+ ulWakeupStatus = PRCM_WDT_RESET;
+ }
+ }
+ }
+ else if((ulWakeupStatus == PRCM_LPDS_EXIT) &&
+ !(HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG1) & (1 <<2)) )
+ {
+ if(HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x1<<8))
+ {
+ ulWakeupStatus = PRCM_POWER_ON;
+ }
+ }
+
+ //
+ // Return status.
+ //
+ return ulWakeupStatus;
+}
+
+//*****************************************************************************
+//
+//! Enable clock(s) to peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals
+//! \param ulClkFlags are bitmask of clock(s) to be enabled.
+//!
+//! This function enables the clock for the specified peripheral. Peripherals
+//! are by default clock gated (disabled) and generates a bus fault if
+//! accessed.
+//!
+//! The parameter \e ulClkFlags can be logical OR of the following:
+//! -\b PRCM_RUN_MODE_CLK - Ungates clock to the peripheral
+//! -\b PRCM_SLP_MODE_CLK - Keeps the clocks ungated in sleep.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralClkEnable(unsigned long ulPeripheral, unsigned long ulClkFlags)
+{
+ //
+ // Enable the specified peripheral clocks, Nothing to be done for PRCM_ADC
+ // as it is a dummy define for pinmux utility code generation
+ //
+ if(ulPeripheral != PRCM_ADC)
+ {
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) |= ulClkFlags;
+ }
+
+ //
+ // Checking ROM Version less than 2.x.x.
+ // Only for driverlib backward compatibility
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) < 2 )
+ {
+ //
+ // Set the default clock for camera
+ //
+ if(ulPeripheral == PRCM_CAMERA)
+ {
+ HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) = 0x0404;
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables clock(s) to peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals
+//! \param ulClkFlags are bitmask of clock(s) to be enabled.
+//!
+//! This function disable the clock for the specified peripheral. Peripherals
+//! are by default clock gated (disabled) and generated a bus fault if
+//! accessed.
+//!
+//! The parameter \e ulClkFlags can be logical OR bit fields as defined in
+//! PRCMEnablePeripheral().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralClkDisable(unsigned long ulPeripheral, unsigned long ulClkFlags)
+{
+ //
+ // Disable the specified peripheral clocks
+ //
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulClkReg) &= ~ulClkFlags;
+}
+
+//*****************************************************************************
+//
+//! Gets the input clock for the specified peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripherals.
+//!
+//! This function gets the input clock for the specified peripheral.
+//!
+//! The parameter \e ulPeripheral has the same definition as that in
+//! PRCMPeripheralClkEnable();
+//!
+//! \return Returns input clock frequency for specified peripheral.
+//
+//*****************************************************************************
+unsigned long
+PRCMPeripheralClockGet(unsigned long ulPeripheral)
+{
+ unsigned long ulClockFreq;
+ unsigned long ulHiPulseDiv;
+ unsigned long ulLoPulseDiv;
+
+ //
+ // Get the clock based on specified peripheral.
+ //
+ if(((ulPeripheral == PRCM_SSPI) | (ulPeripheral == PRCM_LSPI)
+ | (ulPeripheral == PRCM_GSPI)))
+ {
+ return XTAL_CLK;
+ }
+ else if(ulPeripheral == PRCM_CAMERA)
+ {
+ ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN) >> 8) & 0x07);
+ ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_CAMERA_CLK_GEN)& 0xFF);
+ }
+ else if(ulPeripheral == PRCM_SDHOST)
+ {
+ ulHiPulseDiv = ((HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN) >> 8) & 0x07);
+ ulLoPulseDiv = (HWREG(ARCM_BASE + APPS_RCM_O_MMCHS_CLK_GEN)& 0xFF);
+ }
+ else
+ {
+ return SYS_CLK;
+ }
+
+ //
+ // Compute the clock freq. from the divider value
+ //
+ ulClockFreq = (240000000/((ulHiPulseDiv + 1) + (ulLoPulseDiv + 1)));
+
+ //
+ // Return the clock rate.
+ //
+ return ulClockFreq;
+}
+
+//*****************************************************************************
+//
+//! Performs a software reset of a peripheral.
+//!
+//! \param ulPeripheral is one of the valid peripheral.
+//!
+//! This function does soft reset of the specified peripheral
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMPeripheralReset(unsigned long ulPeripheral)
+{
+ volatile unsigned long ulDelay;
+
+ if( ulPeripheral != PRCM_DTHE)
+ {
+ //
+ // Assert the reset
+ //
+ HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
+ |= PRCM_SOFT_RESET;
+ //
+ // Delay a little bit.
+ //
+ for(ulDelay = 0; ulDelay < 16; ulDelay++)
+ {
+ }
+
+ //
+ // Deassert the reset
+ //
+ HWREG(ARCM_BASE+PRCM_PeriphRegsList[ulPeripheral].ulRstReg)
+ &= ~PRCM_SOFT_RESET;
+ }
+}
+
+//*****************************************************************************
+//
+//! Determines if a peripheral is ready.
+//!
+//! \param ulPeripheral is one of the valid modules
+//!
+//! This function determines if a particular peripheral is ready to be
+//! accessed. The peripheral may be in a non-ready state if it is not enabled,
+//! is being held in reset, or is in the process of becoming ready after being
+//! enabled or taken out of reset.
+//!
+//! \return Returns \b true if the peripheral is ready, \b false otherwise.
+//
+//*****************************************************************************
+tBoolean
+PRCMPeripheralStatusGet(unsigned long ulPeripheral)
+{
+ unsigned long ReadyBit;
+
+ //
+ // Read the ready bit status
+ //
+ ReadyBit = HWREG(ARCM_BASE + PRCM_PeriphRegsList[ulPeripheral].ulRstReg);
+ ReadyBit = ReadyBit & PRCM_ENABLE_STATUS;
+
+ if (ReadyBit)
+ {
+ //
+ // Module is ready
+ //
+ return(true);
+ }
+ else
+ {
+ //
+ // Module is not ready
+ //
+ return(false);
+ }
+}
+
+//*****************************************************************************
+//
+//! Configure I2S fracactional divider
+//!
+//! \param ulI2CClkFreq is the required input clock for McAPS module
+//!
+//! This function configures I2S fractional divider. By default this
+//! divider is set to output 24 Mhz clock to I2S module.
+//!
+//! The minimum frequency that can be obtained by configuring this divider is
+//!
+//! (240000KHz/1023.99) = 234.377 KHz
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq)
+{
+ unsigned long long ullDiv;
+ unsigned short usInteger;
+ unsigned short usFrac;
+
+ ullDiv = (((unsigned long long)240000000 * 65536)/ulI2CClkFreq);
+
+ usInteger = (ullDiv/65536);
+ usFrac = (ullDiv%65536);
+
+ HWREG(ARCM_BASE + APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0) =
+ ((usInteger & 0x3FF) << 16 | usFrac);
+}
+
+//*****************************************************************************
+//
+//! Sets the LPDS exit PC and SP restore vlaues.
+//!
+//! \param ulStackPtr is the SP restore value.
+//! \param ulProgCntr is the PC restore value
+//!
+//! This function sets the LPDS exit PC and SP restore vlaues. Setting
+//! \e ulProgCntr to a non-zero value, forces bootloader to jump to that
+//! address with Stack Pointer initialized to \e ulStackPtr on LPDS exit,
+//! otherwise the application's vector table entries are used.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSRestoreInfoSet(unsigned long ulStackPtr, unsigned long ulProgCntr)
+{
+ //
+ // ROM Version 2.x.x or greater
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
+ {
+ //
+ // Set The SP Value
+ //
+ HWREG(0x4402E160) = ulStackPtr;
+
+ //
+ // Set The PC Value
+ //
+ HWREG(0x4402E198) = ulProgCntr;
+
+ }
+ else
+ {
+ //
+ // Set The SP Value
+ //
+ HWREG(0x4402E18C) = ulStackPtr;
+
+ //
+ // Set The PC Value
+ //
+ HWREG(0x4402E190) = ulProgCntr;
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Low Power Deel Sleep (LPDS) power mode.
+//!
+//! This function puts the system into Low Power Deel Sleep (LPDS) power mode.
+//! A call to this function never returns and the execution starts from Reset.
+//! \sa PRCMLPDSRestoreInfoSet().
+//!
+//! \return None.
+//!
+//! \note External debugger will always disconnect whenever the system
+//! enters LPDS and debug interface is shutdown until next POR reset. In order
+//! to avoid this and allow for connecting back the debugger after waking up
+//! from LPDS \sa PRCMLPDSEnterKeepDebugIf().
+//!
+//
+//*****************************************************************************
+void
+PRCMLPDSEnter()
+{
+ unsigned long ulChipId;
+
+ //
+ // Read the Chip ID
+ //
+ ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F);
+
+ //
+ // Check if flash exists
+ //
+ if( (0x11 == ulChipId) || (0x19 == ulChipId))
+ {
+
+ //
+ // Disable the flash
+ //
+ FlashDisable();
+ }
+
+#ifndef KEEP_TESTPD_ALIVE
+
+ //
+ // Disable TestPD
+ //
+ HWREG(0x4402E168) |= (1<<9);
+#endif
+
+ //
+ // Set bandgap duty cycle to 1
+ //
+ HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
+
+ //
+ // Request LPDS
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ)
+ = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
+
+ //
+ // Wait for system to enter LPDS
+ //
+ __asm(" wfi\n");
+
+ //
+ // Infinite loop
+ //
+ while(1)
+ {
+
+ }
+
+}
+
+
+//*****************************************************************************
+//
+//! Puts the system into Low Power Deel Sleep (LPDS) power mode keeping
+//! debug interface alive.
+//!
+//! This function puts the system into Low Power Deel Sleep (LPDS) power mode
+//! keeping debug interface alive. A call to this function never returns and the
+//! execution starts from Reset \sa PRCMLPDSRestoreInfoSet().
+//!
+//! \return None.
+//!
+//! \note External debugger will always disconnect whenever the system
+//! enters LPDS, using this API will allow connecting back the debugger after
+//! waking up from LPDS. This API is recommended for development purposes
+//! only as it adds to the current consumption of the system.
+//!
+//
+//*****************************************************************************
+void
+PRCMLPDSEnterKeepDebugIf()
+{
+ unsigned long ulChipId;
+
+ //
+ // Read the Chip ID
+ //
+ ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F);
+
+ //
+ // Check if flash exists
+ //
+ if( (0x11 == ulChipId) || (0x19 == ulChipId))
+ {
+
+ //
+ // Disable the flash
+ //
+ FlashDisable();
+ }
+
+ //
+ // Set bandgap duty cycle to 1
+ //
+ HWREG(HIB1P2_BASE + HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG) = 0x1;
+
+ //
+ // Request LPDS
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_LPDS_REQ)
+ = APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ;
+
+ //
+ // Wait for system to enter LPDS
+ //
+ __asm(" wfi\n");
+
+ //
+ // Infinite loop
+ //
+ while(1)
+ {
+
+ }
+
+}
+
+//*****************************************************************************
+//
+//! Enable the individual LPDS wakeup source(s).
+//!
+//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
+//!
+//! This function enable the individual LPDS wakeup source(s) and following
+//! three wakeup sources (\e ulLpdsWakeupSrc ) are supported by the device.
+//! -\b PRCM_LPDS_HOST_IRQ
+//! -\b PRCM_LPDS_GPIO
+//! -\b PRCM_LPDS_TIMER
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Read the current wakup sources
+ //
+ ulRegVal = HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG);
+
+ //
+ // Enable individual wakeup source
+ //
+ ulRegVal = ((ulRegVal | ulLpdsWakeupSrc) & 0x91);
+
+ //
+ // Set the configuration in the register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) = ulRegVal;
+}
+
+//*****************************************************************************
+//
+//! Disable the individual LPDS wakeup source(s).
+//!
+//! \param ulLpdsWakeupSrc is logical OR of wakeup sources.
+//!
+//! This function enable the individual LPDS wakeup source(s) and following
+//! three wake up sources (\e ulLpdsWakeupSrc ) are supported by the device.
+//! -\b PRCM_LPDS_HOST_IRQ
+//! -\b PRCM_LPDS_GPIO
+//! -\b PRCM_LPDS_TIMER
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc)
+{
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_CFG) &= ~ulLpdsWakeupSrc;
+}
+
+
+//*****************************************************************************
+//
+//! Get LPDS wakeup cause
+//!
+//! This function gets LPDS wakeup caouse
+//!
+//! \return Returns values enumerated as described in
+//! PRCMLPDSWakeupSourceEnable().
+//
+//*****************************************************************************
+unsigned long
+PRCMLPDSWakeupCauseGet()
+{
+ return (HWREG(GPRCM_BASE+ GPRCM_O_APPS_LPDS_WAKEUP_SRC));
+}
+
+//*****************************************************************************
+//
+//! Sets LPDS wakeup Timer
+//!
+//! \param ulTicks is number of 32.768 KHz clocks
+//!
+//! This function sets internal LPDS wakeup timer running at 32.768 KHz. The
+//! timer is only configured if the parameter \e ulTicks is in valid range i.e.
+//! from 21 to 2^32.
+//!
+//! \return Returns \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+void
+PRCMLPDSIntervalSet(unsigned long ulTicks)
+{
+ //
+ // Check sleep is atleast for 21 cycles
+ // If not set the sleep time to 21 cycles
+ //
+ if( ulTicks < 21)
+ {
+ ulTicks = 21;
+ }
+
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG) = ulTicks;
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG) = ulTicks-20;
+}
+
+//*****************************************************************************
+//
+//! Selects the GPIO for LPDS wakeup
+//!
+//! \param ulGPIOPin is one of the valid GPIO fro LPDS wakeup.
+//! \param ulType is the wakeup trigger type.
+//!
+//! This function setects the wakeup GPIO for LPDS wakeup and can be
+//! used to select one out of 7 pre-defined GPIO(s).
+//!
+//! The parameter \e ulLpdsGPIOSel should be one of the following:-
+//! -\b PRCM_LPDS_GPIO2
+//! -\b PRCM_LPDS_GPIO4
+//! -\b PRCM_LPDS_GPIO13
+//! -\b PRCM_LPDS_GPIO17
+//! -\b PRCM_LPDS_GPIO11
+//! -\b PRCM_LPDS_GPIO24
+//! -\b PRCM_LPDS_GPIO26
+//!
+//! The parameter \e ulType sets the trigger type and can be one of the
+//! following:
+//! - \b PRCM_LPDS_LOW_LEVEL
+//! - \b PRCM_LPDS_HIGH_LEVEL
+//! - \b PRCM_LPDS_FALL_EDGE
+//! - \b PRCM_LPDS_RISE_EDGE
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin, unsigned long ulType)
+{
+ //
+ // Set the wakeup GPIO
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL, ulGPIOPin);
+
+ //
+ // Set the trigger type.
+ //
+ HWREG(GPRCM_BASE + GPRCM_O_APPS_GPIO_WAKE_CONF) = (ulType & 0x3);
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Sleep.
+//!
+//! This function puts the system into sleep power mode. System exits the power
+//! state on any one of the available interrupt. On exit from sleep mode the
+//! function returns to the calling function with all the processor core
+//! registers retained.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMSleepEnter()
+{
+ //
+ // Request Sleep
+ //
+ CPUwfi();
+}
+
+//*****************************************************************************
+//
+//! Enable SRAM column retention during LPDS Power mode(s)
+//!
+//! \param ulSramColSel is bit mask of valid SRAM columns.
+//! \param ulModeFlags is the bit mask of power modes.
+//!
+//! This functions enables the SRAM retention. The device supports configurable
+//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is of
+//! 64 KB size.
+//!
+//! The parameter \e ulSramColSel should be logical OR of the following:-
+//! -\b PRCM_SRAM_COL_1
+//! -\b PRCM_SRAM_COL_2
+//! -\b PRCM_SRAM_COL_3
+//! -\b PRCM_SRAM_COL_4
+//!
+//! The parameter \e ulModeFlags selects the power modes and sholud be logical
+//! OR of one or more of the following
+//! -\b PRCM_SRAM_LPDS_RET
+//!
+//! \return None.
+//
+//****************************************************************************
+void
+PRCMSRAMRetentionEnable(unsigned long ulSramColSel, unsigned long ulModeFlags)
+{
+ if(ulModeFlags & PRCM_SRAM_LPDS_RET)
+ {
+ //
+ // Configure LPDS SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) = (ulSramColSel & 0xF);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable SRAM column retention during LPDS Power mode(s).
+//!
+//! \param ulSramColSel is bit mask of valid SRAM columns.
+//! \param ulFlags is the bit mask of power modes.
+//!
+//! This functions disable the SRAM retention. The device supports configurable
+//! SRAM column retention in Low Power Deep Sleep (LPDS). Each column is
+//! of 64 KB size.
+//!
+//! The parameter \e ulSramColSel should be logical OR of the following:-
+//! -\b PRCM_SRAM_COL_1
+//! -\b PRCM_SRAM_COL_2
+//! -\b PRCM_SRAM_COL_3
+//! -\b PRCM_SRAM_COL_4
+//!
+//! The parameter \e ulFlags selects the power modes and sholud be logical OR
+//! of one or more of the following
+//! -\b PRCM_SRAM_LPDS_RET
+//!
+//! \return None.
+//
+//****************************************************************************
+void
+PRCMSRAMRetentionDisable(unsigned long ulSramColSel, unsigned long ulFlags)
+{
+ if(ulFlags & PRCM_SRAM_LPDS_RET)
+ {
+ //
+ // Configure LPDS SRAM retention register
+ //
+ HWREG(GPRCM_BASE+ GPRCM_O_APPS_SRAM_LPDS_CFG) &= ~(ulSramColSel & 0xF);
+ }
+}
+
+
+//*****************************************************************************
+//
+//! Enables individual HIB wakeup source(s).
+//!
+//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
+//!
+//! This function enables individual HIB wakeup source(s). The paramter
+//! \e ulHIBWakupSrc is the bit mask of HIB wakeup sources and should be
+//! logical OR of one or more of the follwoing :-
+//! -\b PRCM_HIB_SLOW_CLK_CTR
+//! -\b PRCM_HIB_GPIO2
+//! -\b PRCM_HIB_GPIO4
+//! -\b PRCM_HIB_GPIO13
+//! -\b PRCM_HIB_GPIO17
+//! -\b PRCM_HIB_GPIO11
+//! -\b PRCM_HIB_GPIO24
+//! -\b PRCM_HIB_GPIO26
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc)
+{
+ unsigned long ulRegValue;
+
+ //
+ // Read the RTC register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
+
+ //
+ // Enable the RTC as wakeup source if specified
+ //
+ ulRegValue |= (ulHIBWakupSrc & 0x1);
+
+ //
+ // Enable HIB wakeup sources
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
+
+ //
+ // REad the GPIO wakeup configuration register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
+
+ //
+ // Enable the specified GPIOs a wakeup sources
+ //
+ ulRegValue |= ((ulHIBWakupSrc>>16)&0xFF);
+
+ //
+ // Write the new register configuration
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
+}
+
+//*****************************************************************************
+//
+//! Disable individual HIB wakeup source(s).
+//!
+//! \param ulHIBWakupSrc is logical OR of valid HIB wakeup sources.
+//!
+//! This function disable individual HIB wakeup source(s). The paramter
+//! \e ulHIBWakupSrc is same as bit fileds defined in
+//! PRCMEnableHibernateWakeupSource()
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc)
+{
+ unsigned long ulRegValue;
+
+ //
+ // Read the RTC register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
+
+ //
+ // Disable the RTC as wakeup source if specified
+ //
+ ulRegValue &= ~(ulHIBWakupSrc & 0x1);
+
+ //
+ // Disable HIB wakeup sources
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
+
+ //
+ // Read the GPIO wakeup configuration register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN);
+
+ //
+ // Enable the specified GPIOs a wakeup sources
+ //
+ ulRegValue &= ~((ulHIBWakupSrc>>16)&0xFF);
+
+ //
+ // Write the new register configuration
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_EN,ulRegValue);
+}
+
+
+//*****************************************************************************
+//
+//! Get hibernate wakeup cause
+//!
+//! This function gets the hibernate wakeup cause.
+//!
+//! \return Returns \b PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK or
+//! \b PRCM_HIB_WAKEUP_CAUSE_GPIO
+//
+//*****************************************************************************
+unsigned long
+PRCMHibernateWakeupCauseGet()
+{
+ //
+ // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
+ {
+ return ((PRCMHIBRegRead((OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8))>>2)&0x7);
+ }
+ else
+ {
+ return(0);
+ }
+}
+
+//*****************************************************************************
+//
+//! Sets Hibernate wakeup Timer
+//!
+//! \param ullTicks is number of 32.768 KHz clocks
+//!
+//! This function sets internal hibernate wakeup timer running at 32.768 KHz.
+//!
+//! \return Returns \b true on success, \b false otherwise.
+//
+//*****************************************************************************
+void
+PRCMHibernateIntervalSet(unsigned long long ullTicks)
+{
+ unsigned long long ullRTCVal;
+
+ //
+ // Latch the RTC vlaue
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1);
+
+ //
+ // Read latched values as 2 32-bit vlaues
+ //
+ ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
+ ullRTCVal = ullRTCVal << 32;
+ ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
+
+ //
+ // Add the interval
+ //
+ ullRTCVal = ullRTCVal + ullTicks;
+
+ //
+ // Set RTC match value
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF,
+ (unsigned long)(ullRTCVal));
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF,
+ (unsigned long)(ullRTCVal>>32));
+}
+
+
+//*****************************************************************************
+//
+//! Selects the GPIO(s) for hibernate wakeup
+//!
+//! \param ulGPIOBitMap is the bit-map of valid hibernate wakeup GPIO.
+//! \param ulType is the wakeup trigger type.
+//!
+//! This function setects the wakeup GPIO for hibernate and can be
+//! used to select any combination of 7 pre-defined GPIO(s).
+//!
+//! This function enables individual HIB wakeup source(s). The paramter
+//! \e ulGPIOBitMap should be one of the follwoing :-
+//! -\b PRCM_HIB_GPIO2
+//! -\b PRCM_HIB_GPIO4
+//! -\b PRCM_HIB_GPIO13
+//! -\b PRCM_HIB_GPIO17
+//! -\b PRCM_HIB_GPIO11
+//! -\b PRCM_HIB_GPIO24
+//! -\b PRCM_HIB_GPIO26
+//!
+//! The parameter \e ulType sets the trigger type and can be one of the
+//! following:
+//! - \b PRCM_HIB_LOW_LEVEL
+//! - \b PRCM_HIB_HIGH_LEVEL
+//! - \b PRCM_HIB_FALL_EDGE
+//! - \b PRCM_HIB_RISE_EDGE
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateWakeUpGPIOSelect(unsigned long ulGPIOBitMap, unsigned long ulType)
+{
+ unsigned char ucLoop;
+ unsigned long ulRegValue;
+
+ //
+ // Shift the bits to extract the GPIO selection
+ //
+ ulGPIOBitMap >>= 16;
+
+ //
+ // Set the configuration for each GPIO
+ //
+ for(ucLoop=0; ucLoop < 7; ucLoop++)
+ {
+ if(ulGPIOBitMap & (1<<ucLoop))
+ {
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_CONF);
+ ulRegValue = (ulRegValue & (~(0x3 << (ucLoop*2)))) | (ulType <<(ucLoop*2));
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_GPIO_WAKE_CONF, ulRegValue);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Puts the system into Hibernate
+//!
+//! This function puts the system into Hibernate. The device enters HIB
+//! immediately and on exit from HIB device core starts its execution from
+//! reset thus the function never returns.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void
+PRCMHibernateEnter()
+{
+
+ //
+ // Request hibernate.
+ //
+ PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1);
+
+ //
+ // Wait for system to enter hibernate
+ //
+ __asm(" wfi\n");
+
+ //
+ // Infinite loop
+ //
+ while(1)
+ {
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the internal slow clock counter
+//!
+//! This function latches and reads the internal RTC running at 32.768 Khz
+//!
+//! \return 64-bit current counter vlaue.
+//
+//*****************************************************************************
+unsigned long long
+PRCMSlowClkCtrGet()
+{
+ unsigned long long ullRTCVal;
+
+ //
+ // Latch the RTC vlaue
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ, 0x1);
+
+ //
+ // Read latched values as 2 32-bit vlaues
+ //
+ ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
+ ullRTCVal = ullRTCVal << 32;
+ ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
+
+ return ullRTCVal;
+}
+
+//*****************************************************************************
+//
+//! Gets the current value of the internal slow clock counter
+//!
+//! This function is similar to \sa PRCMSlowClkCtrGet() but reads the counter
+//! value from a relatively faster interface using an auto-latch mechainsm.
+//!
+//! \note Due to the nature of implemetation of auto latching, when using this
+//! API, the recommendation is to read the value thrice and identify the right
+//! value (as 2 out the 3 read values will always be correct and with a max. of
+//! 1 LSB change)
+//!
+//! \return 64-bit current counter vlaue.
+//
+//*****************************************************************************
+unsigned long long PRCMSlowClkCtrFastGet(void)
+{
+ unsigned long long ullRTCVal;
+
+ //
+ // Read as 2 32-bit values
+ //
+ ullRTCVal = HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_MSW_1P2);
+ ullRTCVal = ullRTCVal << 32;
+ ullRTCVal |= HWREG(HIB1P2_BASE + HIB1P2_O_HIB_RTC_TIMER_LSW_1P2);
+
+ return ullRTCVal;
+
+}
+
+//*****************************************************************************
+//
+//! Sets slow clock counter match value to interrupt the processor.
+//!
+//! \param ullValue is the match value.
+//!
+//! This function sets the match value for slow clock counter. This is use
+//! to interrupt the processor when RTC counts to the specified value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMSlowClkCtrMatchSet(unsigned long long ullValue)
+{
+ //
+ // Set RTC match value
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF,
+ (unsigned long)(ullValue));
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF,
+ (unsigned long)(ullValue>>32));
+}
+
+//*****************************************************************************
+//
+//! Gets slow clock counter match value.
+//!
+//! This function gets the match value for slow clock counter. This is use
+//! to interrupt the processor when RTC counts to the specified value.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long long PRCMSlowClkCtrMatchGet()
+{
+ unsigned long long ullValue;
+
+ //
+ // Get RTC match value
+ //
+ ullValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF);
+ ullValue = ullValue<<32;
+ ullValue |= PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF);
+
+ //
+ // Return the value
+ //
+ return ullValue;
+}
+
+
+//*****************************************************************************
+//
+//! Write to On-Chip Retention (OCR) register.
+//!
+//! This function writes to On-Chip retention register. The device supports two
+//! 4-byte OCR register which are retained across all power mode.
+//!
+//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
+//!
+//! These registers are shared by the RTC implementation (if Driverlib RTC
+//! APIs are used), ROM, and user application.
+//!
+//! When RTC APIs in use:
+//!
+//! |-----------------------------------------------|
+//! | INDEX 1 |
+//! |-----------------------------------------------|
+//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
+//! |-----------------------------------------------|
+//! | Reserved by RTC APIs - YY |
+//! |-----------------------------------------------|
+//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+//! |-----------------------------------------------|
+//! | Reserved by RTC APIs - YY |
+//! |-----------------------------------------------|
+//!
+//!
+//! |-----------------------------------------------|
+//! | INDEX 0 |
+//! |-----------------------------------------------|
+//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
+//! |-----------------------------------------------|
+//! | Reserved by RTC APIs - YY |
+//! |-----------------------------------------------|
+//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+//! |-----------------------------------------------|
+//! |YY| For User Application |XX|
+//! |-----------------------------------------------|
+//!
+//! YY => Reserved by RTC APIs. If Driverlib RTC APIs are used
+//! XX => Reserved by ROM
+//!
+//!
+//! When RTC APIs are not in use:
+//!
+//! |-----------------------------------------------|
+//! | INDEX 1 |
+//! |-----------------------------------------------|
+//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
+//! |-----------------------------------------------|
+//! | For User Application |
+//! |-----------------------------------------------|
+//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+//! |-----------------------------------------------|
+//! | For User Application |
+//! |-----------------------------------------------|
+//!
+//!
+//! |-----------------------------------------------|
+//! | INDEX 0 |
+//! |-----------------------------------------------|
+//! |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|
+//! |-----------------------------------------------|
+//! | For User Application |
+//! |-----------------------------------------------|
+//! |15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00|
+//! |-----------------------------------------------|
+//! | For User Application |XX|
+//! |-----------------------------------------------|
+//!
+//! XX => Reserved by ROM
+//!
+//!
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMOCRRegisterWrite(unsigned char ucIndex, unsigned long ulRegValue)
+{
+ unsigned long ulVal;
+
+ //
+ // Compuitr the offset
+ //
+ ucIndex = ucIndex << 2;
+
+ //
+ // If bit 0 is reserved
+ //
+ if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) &&
+ (ucIndex == 0) )
+ {
+ ulVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex);
+ ulRegValue = ((ulRegValue << 0x1) | (ulVal & (0x1)));
+ }
+
+ //
+ // Write thr value
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2 + ucIndex,ulRegValue);
+
+}
+
+//*****************************************************************************
+//
+//! Read from On-Chip Retention (OCR) register.
+//!
+//! This function reads from On-Chip retention register. The device supports two
+//! 4-byte OCR register which are retained across all power mode.
+//!
+//! The parameter \e ucIndex is an index of the OCR and can be \b 0 or \b 1.
+//!
+//! \sa PRCMOCRRegisterWrite() for the register usage details.
+//!
+//! \return None.
+//
+//*****************************************************************************
+unsigned long PRCMOCRRegisterRead(unsigned char ucIndex)
+{
+ unsigned long ulRet;
+
+ //
+ // Read the OCR register
+ //
+ ulRet = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_REG2 + (ucIndex << 2));
+
+ //
+ // If bit 0 is reserved
+ //
+ if( (HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) & (0x00000080)) &&
+ (ucIndex == 0) )
+ {
+ ulRet = ulRet >> 0x1;
+ }
+
+ //
+ // Return the read value.
+ //
+ return ulRet;
+}
+
+//*****************************************************************************
+//
+//! Registers an interrupt handler for the PRCM.
+//!
+//! \param pfnHandler is a pointer to the function to be called when the
+//! interrupt is activated.
+//!
+//! This function does the actual registering of the interrupt handler. This
+//! function enables the global interrupt in the interrupt controller;
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntRegister(void (*pfnHandler)(void))
+{
+ //
+ // Register the interrupt handler.
+ //
+ IntRegister(INT_PRCM, pfnHandler);
+
+ //
+ // Enable the PRCM interrupt.
+ //
+ IntEnable(INT_PRCM);
+}
+
+//*****************************************************************************
+//
+//! Unregisters an interrupt handler for the PRCM.
+//!
+//! This function does the actual unregistering of the interrupt handler. It
+//! clears the handler to be called when a PRCM interrupt occurs. This
+//! function also masks off the interrupt in the interrupt controller so that
+//! the interrupt handler no longer is called.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntUnregister()
+{
+ //
+ // Enable the UART interrupt.
+ //
+ IntDisable(INT_PRCM);
+
+ //
+ // Register the interrupt handler.
+ //
+ IntUnregister(INT_PRCM);
+}
+
+//*****************************************************************************
+//
+//! Enables individual PRCM interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be enabled.
+//!
+//! This function enables the indicated ARCM interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter is the logical OR of any of the following:
+//! -\b PRCM_INT_SLOW_CLK_CTR
+//!
+//
+//*****************************************************************************
+void PRCMIntEnable(unsigned long ulIntFlags)
+{
+ unsigned long ulRegValue;
+
+ if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
+ {
+ //
+ // Enable PRCM interrupt
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) |= 0x4;
+
+ //
+ // Enable RTC interrupt
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
+ ulRegValue |= 0x1;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! Disables individual PRCM interrupt sources.
+//!
+//! \param ulIntFlags is the bit mask of the interrupt sources to be disabled.
+//!
+//! This function disables the indicated ARCM interrupt sources. Only the
+//! sources that are enabled can be reflected to the processor interrupt;
+//! disabled sources have no effect on the processor.
+//!
+//! The \e ulIntFlags parameter has the same definition as the \e ulIntFlags
+//! parameter to PRCMEnableInterrupt().
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIntDisable(unsigned long ulIntFlags)
+{
+ unsigned long ulRegValue;
+
+ if(ulIntFlags & PRCM_INT_SLOW_CLK_CTR )
+ {
+ //
+ // Disable PRCM interrupt
+ //
+ HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE) &= ~0x4;
+
+ //
+ // Disable RTC interrupt
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE);
+ ulRegValue &= ~0x1;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE, ulRegValue);
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the current interrupt status.
+//!
+//! This function returns the PRCM interrupt status of interrupts that are
+//! allowed to reflect to the processor. The interrupts are cleared on read.
+//!
+//! \return Returns the current interrupt status.
+//
+//*****************************************************************************
+unsigned long PRCMIntStatus()
+{
+ return HWREG(ARCM_BASE + APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS);
+}
+
+//*****************************************************************************
+//
+//! Mark the function of RTC as being used
+//!
+//! This function marks in HW that feature to maintain calendar time in device
+//! is being used.
+//!
+//! Specifically, this feature reserves user's HIB Register-1 accessed through
+//! PRCMOCRRegisterWrite(1) for internal work / purpose, therefore, the stated
+//! register is not available to user. Also, users must not excercise the Slow
+//! Clock Counter API(s), if RTC has been set for use.
+//!
+//! The RTC feature, if set or marked, can be only reset either through reboot
+//! or power cycle.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCInUseSet()
+{
+ RTC_USE_SET();
+ return;
+}
+
+//*****************************************************************************
+//
+//! Ascertain whether function of RTC is being used
+//!
+//! This function indicates whether function of RTC is being used on the device
+//! or not.
+//!
+//! This routine should be utilized by the application software, when returning
+//! from low-power, to confirm that RTC has been put to use and may not need to
+//! set the value of the RTC.
+//!
+//! The RTC feature, if set or marked, can be only reset either through reboot
+//! or power cycle.
+//!
+//! \return None.
+//
+//*****************************************************************************
+tBoolean PRCMRTCInUseGet()
+{
+ return IS_RTC_USED()? true : false;
+}
+
+//*****************************************************************************
+//
+//! Set the calendar time in the device.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function sets the specified calendar time in the device. The calendar
+//! time is outlined in terms of seconds and milliseconds. However, the device
+//! makes no assumption about the origin or reference of the calendar time.
+//!
+//! The device uses the indicated calendar value to update and maintain the
+//! wall-clock time across active and low power states.
+//!
+//! The function PRCMRTCInUseSet() must be invoked prior to use of this feature.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec) - SCC_U64MSEC_GET();
+
+ RTC_U32SECS_REG_WR(RTC_SECS_IN_U64MSEC(ullMsec));
+ RTC_U16MSEC_REG_WR(RTC_MSEC_IN_U64MSEC(ullMsec));
+ }
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Get the instantaneous calendar time from the device.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function fetches the instantaneous value of the ticking calendar time
+//! from the device. The calendar time is outlined in terms of seconds and
+//! milliseconds.
+//!
+//! The device provides the calendar value that has been maintained across
+//! active and low power states.
+//!
+//! The function PRCMRTCSet() must have been invoked once to set a reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ ullMsec += SCC_U64MSEC_GET();
+ }
+
+ *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
+ *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Set a calendar time alarm.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function sets an wall-clock alarm in the device to be reported for a
+//! futuristic calendar time. The calendar time is outlined in terms of seconds
+//! and milliseconds.
+//!
+//! The device provides uses the calendar value that has been maintained across
+//! active and low power states to report attainment of alarm time.
+//!
+//! The function PRCMRTCSet() must have been invoked once to set a reference.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = RTC_U64MSEC_MK(ulSecs, usMsec);
+ ullMsec -= RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ SCC_U64MSEC_MATCH_SET(SELECT_SCC_U42BITS(ullMsec));
+ }
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! Get a previously set calendar time alarm.
+//!
+//! \param ulSecs refers to the seconds part of the calendar time
+//! \param usMsec refers to the fractional (ms) part of the second
+//!
+//! This function fetches from the device a wall-clock alarm that would have
+//! been previously set in the device. The calendar time is outlined in terms
+//! of seconds and milliseconds.
+//!
+//! If no alarm was set in the past, then this function would fetch a random
+//! information.
+//!
+//! The function PRCMRTCMatchSet() must have been invoked once to set an alarm.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec)
+{
+ unsigned long long ullMsec = 0;
+
+ if(IS_RTC_USED()) {
+ ullMsec = SCC_U64MSEC_MATCH_GET();
+ ullMsec += RTC_U64MSEC_MK(RTC_U32SECS_REG_RD(),
+ RTC_U16MSEC_REG_RD());
+ }
+
+ *ulSecs = RTC_SECS_IN_U64MSEC(ullMsec);
+ *usMsec = RTC_MSEC_IN_U64MSEC(ullMsec);
+
+ return;
+}
+
+//*****************************************************************************
+//
+//! MCU Initialization Routine
+//!
+//! This function contains all the mandatory bug fixes, ECO enables,
+//! initializations for both CC3200 and CC3220.
+//!
+//! \note \b ###IMPORTANT### : This is a routine which should be one of the
+//! first things to be executed after control comes to MCU Application code.
+//!
+//! \return None
+//
+//*****************************************************************************
+void PRCMCC3200MCUInit()
+{
+
+ if( PRCMSysResetCauseGet() != PRCM_LPDS_EXIT )
+ {
+ if( 0x00010001 == HWREG(0x00000400) )
+ {
+
+#ifndef REMOVE_CC3200_ES_1_2_1_CODE
+
+ unsigned long ulRegVal;
+
+ //
+ // DIG DCDC NFET SEL and COT mode disable
+ //
+ HWREG(0x4402F010) = 0x30031820;
+ HWREG(0x4402F00C) = 0x04000000;
+
+ UtilsDelay(32000);
+
+ //
+ // ANA DCDC clock config
+ //
+ HWREG(0x4402F11C) = 0x099;
+ HWREG(0x4402F11C) = 0x0AA;
+ HWREG(0x4402F11C) = 0x1AA;
+
+ //
+ // PA DCDC clock config
+ //
+ HWREG(0x4402F124) = 0x099;
+ HWREG(0x4402F124) = 0x0AA;
+ HWREG(0x4402F124) = 0x1AA;
+
+ //
+ // TD Flash timing configurations in case of MCU WDT reset
+ //
+ if((HWREG(0x4402D00C) & 0xFF) == 0x00000005)
+ {
+ HWREG(0x400F707C) |= 0x01840082;
+ HWREG(0x400F70C4)= 0x1;
+ HWREG(0x400F70C4)= 0x0;
+ }
+
+ //
+ // Take I2C semaphore
+ //
+ ulRegVal = HWREG(0x400F7000);
+ ulRegVal = (ulRegVal & ~0x3) | 0x1;
+ HWREG(0x400F7000) = ulRegVal;
+
+ //
+ // Take GPIO semaphore
+ //
+ ulRegVal = HWREG(0x400F703C);
+ ulRegVal = (ulRegVal & ~0x3FF) | 0x155;
+ HWREG(0x400F703C) = ulRegVal;
+
+ //
+ // Enable 32KHz internal RC oscillator
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_INT_OSC_CONF, 0x00000101);
+
+ //
+ // Delay for a little bit.
+ //
+ UtilsDelay(8000);
+
+ //
+ // Enable 16MHz clock
+ //
+ HWREG(HIB1P2_BASE+HIB1P2_O_CM_OSC_16M_CONFIG) = 0x00010008;
+
+ //
+ // Delay for a little bit.
+ //
+ UtilsDelay(8000);
+
+#endif // REMOVE_CC3200_ES_1_2_1_CODE
+
+ }
+ else
+ {
+
+ unsigned long ulRegValue;
+
+ //
+ // DIG DCDC LPDS ECO Enable
+ //
+ HWREG(0x4402F064) |= 0x800000;
+
+ //
+ // Enable hibernate ECO for PG 1.32 devices only. With this ECO enabled,
+ // any hibernate wakeup source will be kept maked until the device enters
+ // hibernate completely (analog + digital)
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0);
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0, ulRegValue | (1<<4));
+
+ //
+ // Handling the clock switching (for 1.32 only)
+ //
+ HWREG(0x4402E16C) |= 0x3C;
+ }
+
+
+ //
+ // Enable uDMA
+ //
+ PRCMPeripheralClkEnable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
+
+ //
+ // Reset uDMA
+ //
+ PRCMPeripheralReset(PRCM_UDMA);
+
+ //
+ // Disable uDMA
+ //
+ PRCMPeripheralClkDisable(PRCM_UDMA,PRCM_RUN_MODE_CLK);
+
+ //
+ // Enable RTC
+ //
+ if(PRCMSysResetCauseGet()== PRCM_POWER_ON)
+ {
+ PRCMHIBRegWrite(0x4402F804,0x1);
+ }
+
+ //
+ // SWD mode
+ //
+ if(((HWREG(0x4402F0C8) & 0xFF) == 0x2))
+ {
+ HWREG(0x4402E110) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
+ HWREG(0x4402E114) = ((HWREG(0x4402E110) & ~0xC0F) | 0x2);
+ }
+
+ //
+ // Override JTAG mux
+ //
+ HWREG(0x4402E184) |= 0x2;
+
+ //
+ // Change UART pins(55,57) mode to PIN_MODE_0 if they are in PIN_MODE_1
+ //
+ if( (HWREG(0x4402E0A4) & 0xF) == 0x1)
+ {
+ HWREG(0x4402E0A4) = ((HWREG(0x4402E0A4) & ~0xF));
+ }
+
+ if( (HWREG(0x4402E0A8) & 0xF) == 0x1)
+ {
+ HWREG(0x4402E0A8) = ((HWREG(0x4402E0A8) & ~0xF));
+ }
+
+ //
+ // DIG DCDC VOUT trim settings based on PROCESS INDICATOR
+ //
+ if(((HWREG(0x4402DC78) >> 22) & 0xF) == 0xE)
+ {
+ HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x32 << 18));
+ }
+ else
+ {
+ HWREG(0x4402F0B0) = ((HWREG(0x4402F0B0) & ~(0x00FC0000))|(0x29 << 18));
+ }
+
+ //
+ // Enable SOFT RESTART in case of DIG DCDC collapse
+ //
+ HWREG(0x4402FC74) &= ~(0x10000000);
+
+ //
+ // Required only if ROM version is lower than 2.x.x
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) < 2 )
+ {
+ //
+ // Disable the sleep for ANA DCDC
+ //
+ HWREG(0x4402F0A8) |= 0x00000004 ;
+ }
+ else if( (HWREG(0x00000400) >> 16) >= 1 )
+ {
+ //
+ // Enable NWP force reset and HIB on WDT reset
+ // Enable direct boot path for flash
+ //
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= ((7<<5) | 0x1);
+ if((HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) & 0x1) )
+ {
+ HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG2) &= ~0x1;
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_SPARE_REG_8) |= (1<<9);
+
+ //
+ // Clear the RTC hib wake up source
+ //
+ HWREG(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN) &= ~0x1;
+
+ //
+ // Reset RTC match value
+ //
+ HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF) = 0;
+ HWREG(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF) = 0;
+
+ }
+ }
+
+ unsigned long efuse_reg2;
+ unsigned long ulDevMajorVer, ulDevMinorVer;
+ //
+ // Read the device identification register
+ //
+ efuse_reg2= HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2);
+
+ //
+ // Read the ROM mojor and minor version
+ //
+ ulDevMajorVer = ((efuse_reg2 >> 28) & 0xF);
+ ulDevMinorVer = ((efuse_reg2 >> 24) & 0xF);
+
+ if(((ulDevMajorVer == 0x3) && (ulDevMinorVer == 0)) || (ulDevMajorVer < 0x3))
+ {
+ unsigned int Scratch, PreRegulatedMode;
+
+ // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode.
+ PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1;
+
+ if( PreRegulatedMode)
+ {
+ Scratch = HWREG(0x4402F028);
+ Scratch &= 0xFFFFFF7F; // <7:7> = 0
+ HWREG(0x4402F028) = Scratch;
+
+ Scratch = HWREG(0x4402F010);
+ Scratch &= 0x0FFFFFFF; // <31:28> = 0
+ Scratch |= 0x10000000; // <31:28> = 1
+ HWREG(0x4402F010) = Scratch;
+ }
+ else
+ {
+ Scratch = HWREG(0x4402F024);
+
+ Scratch &= 0xFFFFFFF0; // <3:0> = 0
+ Scratch |= 0x00000001; // <3:0> = 1
+ Scratch &= 0xFFFFF0FF; // <11:8> = 0000
+ Scratch |= 0x00000500; // <11:8> = 0101
+ Scratch &= 0xFFFE7FFF; // <16:15> = 0000
+ Scratch |= 0x00010000; // <16:15> = 10
+
+ HWREG(0x4402F024) = Scratch;
+
+ Scratch = HWREG(0x4402F028);
+
+ Scratch &= 0xFFFFFF7F; // <7:7> = 0
+ Scratch &= 0x0FFFFFFF; // <31:28> = 0
+ Scratch &= 0xFF0FFFFF; // <23:20> = 0
+ Scratch |= 0x00300000; // <23:20> = 0011
+ Scratch &= 0xFFF0FFFF; // <19:16> = 0
+ Scratch |= 0x00030000; // <19:16> = 0011
+
+ HWREG(0x4402F028) = Scratch;
+ HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0
+ }
+ }
+ else
+ {
+ unsigned int Scratch, PreRegulatedMode;
+
+ // 0x4402F840 => 6th bit “1” indicates device is in pre-regulated mode.
+ PreRegulatedMode = (HWREG(0x4402F840) >> 6) & 1;
+
+ Scratch = HWREG(0x4402F028);
+ Scratch &= 0xFFFFFF7F; // <7:7> = 0
+ HWREG(0x4402F028) = Scratch;
+
+ HWREG(0x4402F010) &= 0x0FFFFFFF; // <31:28> = 0
+ if( PreRegulatedMode)
+ {
+ HWREG(0x4402F010) |= 0x10000000; // <31:28> = 1
+ }
+ }
+ }
+ else
+ {
+ unsigned long ulRegVal;
+
+ //
+ // I2C Configuration
+ //
+ ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register);
+ ulRegVal = (ulRegVal & ~0x3) | 0x1;
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_I2C_Properties_Register) = ulRegVal;
+
+ //
+ // GPIO configuration
+ //
+ ulRegVal = HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register);
+ ulRegVal = (ulRegVal & ~0x3FF) | 0x155;
+ HWREG(COMMON_REG_BASE + COMMON_REG_O_GPIO_properties_register) = ulRegVal;
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Reads 32-bit value from register at specified address
+//!
+//! \param ulRegAddr is the address of register to be read.
+//!
+//! This function reads 32-bit value from the register as specified by
+//! \e ulRegAddr.
+//!
+//! \return Return the value of the register.
+//
+//*****************************************************************************
+unsigned long PRCMHIBRegRead(unsigned long ulRegAddr)
+{
+ unsigned long ulValue;
+
+ //
+ // Read the Reg value
+ //
+ ulValue = HWREG(ulRegAddr);
+
+ //
+ // Wait for 200 uSec
+ //
+ UtilsDelay((80*200)/3);
+
+ //
+ // Return the value
+ //
+ return ulValue;
+}
+
+//*****************************************************************************
+//
+//! Writes 32-bit value to register at specified address
+//!
+//! \param ulRegAddr is the address of register to be read.
+//! \param ulValue is the 32-bit value to be written.
+//!
+//! This function writes 32-bit value passed as \e ulValue to the register as
+//! specified by \e ulRegAddr
+//!
+//! \return None
+//
+//*****************************************************************************
+void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue)
+{
+ //
+ // Read the Reg value
+ //
+ HWREG(ulRegAddr) = ulValue;
+
+ //
+ // Wait for 200 uSec
+ //
+ UtilsDelay((80*200)/3);
+}
+
+//*****************************************************************************
+//
+//! \param ulDivider is clock frequency divider value
+//! \param ulWidth is the width of the high pulse
+//!
+//! This function sets the input frequency for camera module.
+//!
+//! The frequency is calculated as follows:
+//!
+//! f_out = 240MHz/ulDivider;
+//!
+//! The parameter \e ulWidth sets the width of the high pulse.
+//!
+//! For e.g.:
+//!
+//! ulDivider = 4;
+//! ulWidth = 2;
+//!
+//! f_out = 30 MHz and 50% duty cycle
+//!
+//! And,
+//!
+//! ulDivider = 4;
+//! ulWidth = 1;
+//!
+//! f_out = 30 MHz and 25% duty cycle
+//!
+//! \return 0 on success, 1 on error
+//
+//*****************************************************************************
+unsigned long PRCMCameraFreqSet(unsigned char ulDivider, unsigned char ulWidth)
+{
+ if(ulDivider > ulWidth && ulWidth != 0 )
+ {
+ //
+ // Set the hifh pulse width
+ //
+ HWREG(ARCM_BASE +
+ APPS_RCM_O_CAMERA_CLK_GEN) = (((ulWidth & 0x07) -1) << 8);
+
+ //
+ // Set the low pulse width
+ //
+ HWREG(ARCM_BASE +
+ APPS_RCM_O_CAMERA_CLK_GEN) = ((ulDivider - ulWidth - 1) & 0x07);
+ //
+ // Return success
+ //
+ return 0;
+ }
+
+ //
+ // Success;
+ //
+ return 1;
+}
+
+//*****************************************************************************
+//
+//! Enable the IO value retention
+//!
+//! \param ulIORetGrpFlags is one of the valid IO groups.
+//!
+//! This function enables the IO retention for group of pins as specified by
+//! \e ulIORetGrpFlags parameter. Enabling retention will immediately lock the
+//! digital pins, in the specified group, to their current state (0 or 1).
+//! Output pins can only be driven when retention is disabled.
+//!
+//! The parameter \e ulIORetGrpFlags can be logical OR of one or
+//! more of the following:
+//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface
+//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14
+//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17
+//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20
+//!
+//! \note Use case is to park the pins when entering HIB.
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
+ {
+ //
+ // Disable IO Pad to ODI Path
+ //
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00001D00;
+
+ //
+ // 0b'0 in bit 5 for JTAG PADS
+ // 0b'0 in bit 0 for all other IOs
+ //
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00000023);
+
+ //
+ // Enable retention for GRP0
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF);
+ ulRegVal |= 0x5;
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal);
+ }
+
+ //
+ // Enable retention for GRP1
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0);
+ ulRegVal |= ((0x3<<5));
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal);
+ }
+
+ //
+ // Enable retention for GRP2
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF);
+ ulRegVal |= 0x00000101;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal);
+ }
+
+ //
+ // Enable retention for GRP3
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF);
+ ulRegVal |= 0x00000204;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal);
+ }
+ }
+}
+
+//*****************************************************************************
+//
+//! Disable the IO value retention
+//!
+//! \param ulIORetGrpFlags is one of the valid IO groups.
+//!
+//! This function disable the IO retention for group of pins as specified by
+//! \e ulIORetGrpFlags parameter. Disabling retention will unlock the
+//! digital pins in the specified group. Output pins can only be driven when
+//! retention is disabled.
+//!
+//! The parameter \e ulIORetGrpFlags can be logical OR of one or
+//! more of the following:
+//! -\b PRCM_IO_RET_GRP_0 - All the pins except sFlash and JTAG interface
+//! -\b PRCM_IO_RET_GRP_1 - sFlash interface pins 11,12,13,14
+//! -\b PRCM_IO_RET_GRP_2 - JTAG TDI and TDO interface pins 16,17
+//! -\b PRCM_IO_RET_GRP_3 - JTAG TCK and TMS interface pins 19,20
+//!
+//! \note Use case is to un-park the pins when exiting HIB
+//!
+//! \return None.
+//
+//*****************************************************************************
+void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags)
+{
+ unsigned long ulRegVal;
+
+ //
+ // Supported only in ES2.00 and Later devices i.e. ROM Version 2.x.x or greater
+ //
+ if( (HWREG(0x00000400) & 0xFFFF) >= 2 )
+ {
+
+ //
+ // Enable IO Pad to ODI Path
+ //
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) &= ~(0x00001D00);
+
+ //
+ // 0b'1 in bit 5 for JTAG PADS
+ // 0b'1 in bit 0 for all other IOs
+ //
+ HWREG(OCP_SHARED_BASE + OCP_SHARED_O_GPIO_PAD_CMN_CONFIG) |= 0x00000023;
+
+ //
+ // Disable retention for GRP0
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_0 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF);
+ ulRegVal &= ~0x5;
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_PAD_OEN_RET33_CONF,ulRegVal);
+ }
+
+ //
+ // Disable retention for GRP1
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_1 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0);
+ ulRegVal &= ~((0x3<<5));
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_HIB_REG0,ulRegVal);
+ }
+
+ //
+ // Disable retention for GRP2
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_2 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF);
+ ulRegVal &= ~0x00000101;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal);
+
+ }
+
+ //
+ // Disable retention for GRP3
+ //
+ if( ulIORetGrpFlags & PRCM_IO_RET_GRP_3 )
+ {
+ ulRegVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF);
+ ulRegVal &= ~0x00000204;
+ PRCMHIBRegWrite(HIB3P3_BASE + HIB3P3_O_MEM_JTAG_CONF,ulRegVal);
+ }
+
+ }
+}
+
+//*****************************************************************************
+//
+//! Gets the device type
+//!
+//! This function returns bit-packed value representing the device type
+//!
+//! The returned value is logical OR of one or more of the following:-
+//!
+//! -\b PRCM_DEV_TYPE_FLAG_R - R variant
+//! -\b PRCM_DEV_TYPE_FLAG_F - F variant
+//! -\b PRCM_DEV_TYPE_FLAG_Z - Z variant
+//! -\b PRCM_DEV_TYPE_FLAG_SECURE - Device is secure
+//! -\b PRCM_DEV_TYPE_FLAG_PRE_PROD - Device is a pre-production part
+//! -\b PRCM_DEV_TYPE_FLAG_3200 - Device is CC3200
+//! -\b PRCM_DEV_TYPE_FLAG_3220 - Device is CC3220
+//! -\b PRCM_DEV_TYPE_FLAG_REV1 - Device Rev 1
+//! -\b PRCM_DEV_TYPE_FLAG_REV2 - Device Rev 2
+//!
+//! Pre-defined helper macros:-
+//!
+//! -\b PRCM_DEV_TYPE_PRE_CC3200R - Pre-Production CC3200R
+//! -\b PRCM_DEV_TYPE_PRE_CC3200F - Pre-Production CC3200F
+//! -\b PRCM_DEV_TYPE_PRE_CC3200Z - Pre-Production CC3200Z
+//! -\b PRCM_DEV_TYPE_CC3200R - Production CC3200R
+//! -\b PRCM_DEV_TYPE_PRE_CC3220R - Pre-Production CC3220R
+//! -\b PRCM_DEV_TYPE_PRE_CC3220F - Pre-Production CC3220F
+//! -\b PRCM_DEV_TYPE_PRE_CC3220Z - Pre-Production CC3220Z
+//! -\b PRCM_DEV_TYPE_CC3220R - Production CC3220R
+//! -\b PRCM_DEV_TYPE_PRE_CC3220RS - Pre-Production CC3220RS
+//! -\b PRCM_DEV_TYPE_PRE_CC3220FS - Pre-Production CC3220FS
+//! -\b PRCM_DEV_TYPE_PRE_CC3220ZS - Pre-Production CC3220ZS
+//! -\b PRCM_DEV_TYPE_CC3220RS - Production CC3220RS
+//! -\b PRCM_DEV_TYPE_CC3220FS - Production CC3220FS
+//!
+//! \return Returns, bit-packed value representing the device type,
+//! or 0 if device is unknown
+//
+//*****************************************************************************
+unsigned long PRCMDeviceTypeGet()
+{
+ unsigned long ulDevType;
+ unsigned long ulChipId;
+ unsigned long ulDevMajorVer;
+ unsigned long ulDevMinorVer;
+
+ //
+ // Read the device identification register
+ //
+ ulChipId = HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2);
+
+ //
+ // Read the ROM mojor and minor version
+ //
+ ulDevMajorVer = ((ulChipId >> 28) & 0xF);
+ ulDevMinorVer = ((ulChipId >> 24) & 0xF);
+
+
+ ulChipId = ((HWREG(GPRCM_BASE + GPRCM_O_GPRCM_EFUSE_READ_REG2) >> 16) & 0x1F);
+
+ //
+ // Get the device variant from the chip id
+ //
+ switch((ulChipId & 0xF))
+ {
+ //
+ // It is R variant
+ //
+ case 0x0:
+ ulDevType = PRCM_DEV_TYPE_FLAG_R;
+ break;
+
+ //
+ // It is F variant, non secure F variant is always Pre-Production
+ //
+ case 0x1:
+ ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_PRE_PROD;
+ break;
+
+ //
+ // It is Z variant and is always Pre-Production
+ //
+ case 0x3:
+ ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_PRE_PROD;
+ break;
+
+ //
+ // It is Secure R
+ //
+ case 0x8:
+ ulDevType = PRCM_DEV_TYPE_FLAG_R|PRCM_DEV_TYPE_FLAG_SECURE;
+ break;
+
+ //
+ // It is Secure F
+ //
+ case 0x9:
+ ulDevType = PRCM_DEV_TYPE_FLAG_F|PRCM_DEV_TYPE_FLAG_SECURE;
+ break;
+
+ //
+ // It is secure Z variant and variant is always Pre-Production
+ //
+ case 0xB:
+ ulDevType = PRCM_DEV_TYPE_FLAG_Z|PRCM_DEV_TYPE_FLAG_SECURE|
+ PRCM_DEV_TYPE_FLAG_PRE_PROD;
+ break;
+
+ //
+ // Undefined variant
+ //
+ default:
+ ulDevType = 0x0;
+ }
+
+ if( ulDevType != 0 )
+ {
+ if( ulDevMajorVer == 0x3 )
+ {
+ ulDevType |= PRCM_DEV_TYPE_FLAG_3220;
+ }
+ else if( ulDevMajorVer == 0x2 )
+ {
+ ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220);
+
+ if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0) )
+ {
+ if((ulDevMinorVer == 0x0))
+ {
+ ulDevType |= PRCM_DEV_TYPE_FLAG_REV1;
+ }
+ else
+ {
+ ulDevType |= PRCM_DEV_TYPE_FLAG_REV2;
+ }
+ }
+ else
+ {
+ if((ulDevMinorVer == 0x1))
+ {
+ ulDevType |= PRCM_DEV_TYPE_FLAG_REV1;
+ }
+ }
+ }
+ else
+ {
+ if( (ulDevMinorVer == 0x4))
+ {
+ if( ((ulDevType & PRCM_DEV_TYPE_FLAG_Z) != 0))
+ {
+ ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3220);
+ }
+ else
+ {
+ ulDevType |= PRCM_DEV_TYPE_FLAG_3200;
+ }
+ }
+ else
+ {
+ ulDevType |= (PRCM_DEV_TYPE_FLAG_PRE_PROD|PRCM_DEV_TYPE_FLAG_3200);
+ }
+ }
+ }
+
+
+ return ulDevType;
+}
+
+
+
+//****************************************************************************
+//
+//! Used to trigger a hibernate cycle for the device using RTC
+//!
+//! This API can be used to do a clean reboot of device.
+//!
+//! \note This routine should only be exercised after all the network processing
+//! has been stopped. To stop network processing use \b sl_stop API from
+//! simplelink library.
+//!
+//! \return None
+//
+//****************************************************************************
+void PRCMHibernateCycleTrigger()
+{
+ unsigned long ulRegValue;
+ unsigned long long ullRTCVal;
+
+ //
+ // Read the RTC register
+ //
+ ulRegValue = PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN);
+
+ //
+ // Enable the RTC as wakeup source if specified
+ //
+ ulRegValue |= (PRCM_HIB_SLOW_CLK_CTR & 0x1);
+
+ //
+ // Enable HIB wakeup sources
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_EN,ulRegValue);
+
+ //
+ // Latch the RTC vlaue
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_READ ,0x1);
+
+ //
+ // Read latched values as 2 32-bit vlaues
+ //
+ ullRTCVal = PRCMHIBRegRead(HIB3P3_BASE + HIB3P3_O_MEM_HIB_RTC_TIMER_MSW);
+ ullRTCVal = ullRTCVal << 32;
+ ullRTCVal |= PRCMHIBRegRead(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_TIMER_LSW);
+
+ //
+ //Considering worst case execution times of ROM,RAM,Flash value of 160 is used
+ //
+ ullRTCVal = ullRTCVal + 160;
+
+ //
+ // Set RTC match value
+ //
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF,
+ (unsigned long)(ullRTCVal));
+ PRCMHIBRegWrite(HIB3P3_BASE+HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF,
+ (unsigned long)(ullRTCVal>>32));
+ //
+ // Note : Any addition of code after this line would need a change in
+ // ullTicks Interval currently set to 160
+ //
+
+ //
+ // Request hibernate.
+ //
+ PRCMHIBRegWrite((HIB3P3_BASE+HIB3P3_O_MEM_HIB_REQ),0x1);
+
+ //
+ // Wait for system to enter hibernate
+ //
+ __asm(" wfi\n");
+
+ //
+ // Infinite loop
+ //
+ while(1)
+ {
+
+ }
+}
+
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/cc3220sdk/driverlib/prcm.h b/ext/hal/ti/cc3220sdk/driverlib/prcm.h
new file mode 100644
index 0000000..17e24ff
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/prcm.h
@@ -0,0 +1,368 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// prcm.h
+//
+// Prototypes for the PRCM control driver.
+//
+//*****************************************************************************
+
+#ifndef __PRCM_H__
+#define __PRCM_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Peripheral clock and reset control registers
+//
+//*****************************************************************************
+typedef struct _PRCM_PeripheralRegs_
+{
+
+unsigned long ulClkReg;
+unsigned long ulRstReg;
+
+}PRCM_PeriphRegs_t;
+
+//*****************************************************************************
+// Values that can be passed to PRCMPeripheralEnable() and
+// PRCMPeripheralDisable()
+//*****************************************************************************
+#define PRCM_RUN_MODE_CLK 0x00000001
+#define PRCM_SLP_MODE_CLK 0x00000100
+
+//*****************************************************************************
+// Values that can be passed to PRCMSRAMRetentionEnable() and
+// PRCMSRAMRetentionDisable() as ulSramColSel.
+//*****************************************************************************
+#define PRCM_SRAM_COL_1 0x00000001
+#define PRCM_SRAM_COL_2 0x00000002
+#define PRCM_SRAM_COL_3 0x00000004
+#define PRCM_SRAM_COL_4 0x00000008
+
+//*****************************************************************************
+// Values that can be passed to PRCMSRAMRetentionEnable() and
+// PRCMSRAMRetentionDisable() as ulModeFlags.
+//*****************************************************************************
+#define PRCM_SRAM_LPDS_RET 0x00000002
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeupSourceEnable(),
+// PRCMLPDSWakeupCauseGet() and PRCMLPDSWakeupSourceDisable().
+//*****************************************************************************
+#define PRCM_LPDS_HOST_IRQ 0x00000080
+#define PRCM_LPDS_GPIO 0x00000010
+#define PRCM_LPDS_TIMER 0x00000001
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeUpGPIOSelect() as Type
+//*****************************************************************************
+#define PRCM_LPDS_LOW_LEVEL 0x00000002
+#define PRCM_LPDS_HIGH_LEVEL 0x00000000
+#define PRCM_LPDS_FALL_EDGE 0x00000001
+#define PRCM_LPDS_RISE_EDGE 0x00000003
+
+//*****************************************************************************
+// Values that can be passed to PRCMLPDSWakeUpGPIOSelect()
+//*****************************************************************************
+#define PRCM_LPDS_GPIO2 0x00000000
+#define PRCM_LPDS_GPIO4 0x00000001
+#define PRCM_LPDS_GPIO13 0x00000002
+#define PRCM_LPDS_GPIO17 0x00000003
+#define PRCM_LPDS_GPIO11 0x00000004
+#define PRCM_LPDS_GPIO24 0x00000005
+#define PRCM_LPDS_GPIO26 0x00000006
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
+// PRCMHibernateWakeupSourceDisable().
+//*****************************************************************************
+#define PRCM_HIB_SLOW_CLK_CTR 0x00000001
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeUpGPIOSelect() as ulType
+//*****************************************************************************
+#define PRCM_HIB_LOW_LEVEL 0x00000000
+#define PRCM_HIB_HIGH_LEVEL 0x00000001
+#define PRCM_HIB_FALL_EDGE 0x00000002
+#define PRCM_HIB_RISE_EDGE 0x00000003
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupSourceEnable(),
+// PRCMHibernateWakeupSourceDisable(), PRCMHibernateWakeUpGPIOSelect()
+//*****************************************************************************
+#define PRCM_HIB_GPIO2 0x00010000
+#define PRCM_HIB_GPIO4 0x00020000
+#define PRCM_HIB_GPIO13 0x00040000
+#define PRCM_HIB_GPIO17 0x00080000
+#define PRCM_HIB_GPIO11 0x00100000
+#define PRCM_HIB_GPIO24 0x00200000
+#define PRCM_HIB_GPIO26 0x00400000
+
+//*****************************************************************************
+// Values that will be returned from PRCMSysResetCauseGet().
+//*****************************************************************************
+#define PRCM_POWER_ON 0x00000000
+#define PRCM_LPDS_EXIT 0x00000001
+#define PRCM_CORE_RESET 0x00000003
+#define PRCM_MCU_RESET 0x00000004
+#define PRCM_WDT_RESET 0x00000005
+#define PRCM_SOC_RESET 0x00000006
+#define PRCM_HIB_EXIT 0x00000007
+
+//*****************************************************************************
+// Values that can be passed to PRCMHibernateWakeupCauseGet().
+//*****************************************************************************
+#define PRCM_HIB_WAKEUP_CAUSE_SLOW_CLOCK 0x00000002
+#define PRCM_HIB_WAKEUP_CAUSE_GPIO 0x00000004
+
+//*****************************************************************************
+// Values that can be passed to PRCMSEnableInterrupt
+//*****************************************************************************
+#define PRCM_INT_SLOW_CLK_CTR 0x00004000
+
+//*****************************************************************************
+// Values that can be passed to PRCMPeripheralClkEnable(),
+// PRCMPeripheralClkDisable(), PRCMPeripheralReset()
+//*****************************************************************************
+#define PRCM_CAMERA 0x00000000
+#define PRCM_I2S 0x00000001
+#define PRCM_SDHOST 0x00000002
+#define PRCM_GSPI 0x00000003
+#define PRCM_LSPI 0x00000004
+#define PRCM_UDMA 0x00000005
+#define PRCM_GPIOA0 0x00000006
+#define PRCM_GPIOA1 0x00000007
+#define PRCM_GPIOA2 0x00000008
+#define PRCM_GPIOA3 0x00000009
+#define PRCM_GPIOA4 0x0000000A
+#define PRCM_WDT 0x0000000B
+#define PRCM_UARTA0 0x0000000C
+#define PRCM_UARTA1 0x0000000D
+#define PRCM_TIMERA0 0x0000000E
+#define PRCM_TIMERA1 0x0000000F
+#define PRCM_TIMERA2 0x00000010
+#define PRCM_TIMERA3 0x00000011
+#define PRCM_DTHE 0x00000012
+#define PRCM_SSPI 0x00000013
+#define PRCM_I2CA0 0x00000014
+// Note : PRCM_ADC is a dummy define for pinmux utility code generation
+// PRCM_ADC should never be used in any user code.
+#define PRCM_ADC 0x000000FF
+
+
+//*****************************************************************************
+// Values that can be passed to PRCMIORetEnable() and PRCMIORetDisable()
+//*****************************************************************************
+#define PRCM_IO_RET_GRP_0 0x00000001
+#define PRCM_IO_RET_GRP_1 0x00000002
+#define PRCM_IO_RET_GRP_2 0x00000004
+#define PRCM_IO_RET_GRP_3 0x00000008
+
+//*****************************************************************************
+// Macros definig the device type
+//*****************************************************************************
+#define PRCM_DEV_TYPE_FLAG_R 0x00000001
+#define PRCM_DEV_TYPE_FLAG_F 0x00000002
+#define PRCM_DEV_TYPE_FLAG_Z 0x00000004
+#define PRCM_DEV_TYPE_FLAG_SECURE 0x00000008
+#define PRCM_DEV_TYPE_FLAG_PRE_PROD 0x00000010
+#define PRCM_DEV_TYPE_FLAG_3200 0x00000020
+#define PRCM_DEV_TYPE_FLAG_3220 0x00000040
+#define PRCM_DEV_TYPE_FLAG_REV1 0x00010000
+#define PRCM_DEV_TYPE_FLAG_REV2 0x00020000
+
+//*****************************************************************************
+// Pre-defined helper macros
+//*****************************************************************************
+#define PRCM_DEV_TYPE_PRE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3200| \
+ PRCM_DEV_TYPE_FLAG_R)
+
+#define PRCM_DEV_TYPE_PRE_CC3200F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3200| \
+ PRCM_DEV_TYPE_FLAG_F)
+
+#define PRCM_DEV_TYPE_PRE_CC3200Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3200| \
+ PRCM_DEV_TYPE_FLAG_Z)
+
+#define PRCM_DEV_TYPE_CC3200R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3200| \
+ PRCM_DEV_TYPE_FLAG_R)
+
+#define PRCM_DEV_TYPE_PRE_CC3220R (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_R)
+
+#define PRCM_DEV_TYPE_PRE_CC3220F (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_F)
+
+#define PRCM_DEV_TYPE_PRE_CC3220Z (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_Z)
+
+#define PRCM_DEV_TYPE_CC3220R (PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_R)
+
+
+#define PRCM_DEV_TYPE_PRE_CC3220RS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_R| \
+ PRCM_DEV_TYPE_FLAG_SECURE)
+
+#define PRCM_DEV_TYPE_PRE_CC3220FS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_F| \
+ PRCM_DEV_TYPE_FLAG_SECURE)
+
+#define PRCM_DEV_TYPE_PRE_CC3220ZS (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_Z| \
+ PRCM_DEV_TYPE_FLAG_SECURE)
+
+#define PRCM_DEV_TYPE_CC3220RS (PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_R| \
+ PRCM_DEV_TYPE_FLAG_SECURE)
+
+#define PRCM_DEV_TYPE_CC3220FS (PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_F| \
+ PRCM_DEV_TYPE_FLAG_SECURE)
+
+
+#define PRCM_DEV_TYPE_PRE_CC3220Z1 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_Z| \
+ PRCM_DEV_TYPE_FLAG_REV1)
+
+#define PRCM_DEV_TYPE_PRE_CC3220Z2 (PRCM_DEV_TYPE_FLAG_PRE_PROD| \
+ PRCM_DEV_TYPE_FLAG_3220| \
+ PRCM_DEV_TYPE_FLAG_Z| \
+ PRCM_DEV_TYPE_FLAG_REV2)
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void PRCMMCUReset(tBoolean bIncludeSubsystem);
+extern unsigned long PRCMSysResetCauseGet(void);
+
+extern void PRCMPeripheralClkEnable(unsigned long ulPeripheral,
+ unsigned long ulClkFlags);
+extern void PRCMPeripheralClkDisable(unsigned long ulPeripheral,
+ unsigned long ulClkFlags);
+extern void PRCMPeripheralReset(unsigned long ulPeripheral);
+extern tBoolean PRCMPeripheralStatusGet(unsigned long ulPeripheral);
+
+extern void PRCMI2SClockFreqSet(unsigned long ulI2CClkFreq);
+extern unsigned long PRCMPeripheralClockGet(unsigned long ulPeripheral);
+
+extern void PRCMSleepEnter(void);
+
+extern void PRCMSRAMRetentionEnable(unsigned long ulSramColSel,
+ unsigned long ulFlags);
+extern void PRCMSRAMRetentionDisable(unsigned long ulSramColSel,
+ unsigned long ulFlags);
+extern void PRCMLPDSRestoreInfoSet(unsigned long ulRestoreSP,
+ unsigned long ulRestorePC);
+extern void PRCMLPDSEnter(void);
+extern void PRCMLPDSIntervalSet(unsigned long ulTicks);
+extern void PRCMLPDSWakeupSourceEnable(unsigned long ulLpdsWakeupSrc);
+extern unsigned long PRCMLPDSWakeupCauseGet(void);
+extern void PRCMLPDSWakeUpGPIOSelect(unsigned long ulGPIOPin,
+ unsigned long ulType);
+extern void PRCMLPDSWakeupSourceDisable(unsigned long ulLpdsWakeupSrc);
+
+extern void PRCMHibernateEnter(void);
+extern void PRCMHibernateWakeupSourceEnable(unsigned long ulHIBWakupSrc);
+extern unsigned long PRCMHibernateWakeupCauseGet(void);
+extern void PRCMHibernateWakeUpGPIOSelect(unsigned long ulMultiGPIOBitMap,
+ unsigned long ulType);
+extern void PRCMHibernateWakeupSourceDisable(unsigned long ulHIBWakupSrc);
+extern void PRCMHibernateIntervalSet(unsigned long long ullTicks);
+
+extern unsigned long long PRCMSlowClkCtrGet(void);
+extern unsigned long long PRCMSlowClkCtrFastGet(void);
+extern void PRCMSlowClkCtrMatchSet(unsigned long long ullTicks);
+extern unsigned long long PRCMSlowClkCtrMatchGet(void);
+
+extern void PRCMOCRRegisterWrite(unsigned char ucIndex,
+ unsigned long ulRegValue);
+extern unsigned long PRCMOCRRegisterRead(unsigned char ucIndex);
+
+extern void PRCMIntRegister(void (*pfnHandler)(void));
+extern void PRCMIntUnregister(void);
+extern void PRCMIntEnable(unsigned long ulIntFlags);
+extern void PRCMIntDisable(unsigned long ulIntFlags);
+extern unsigned long PRCMIntStatus(void);
+extern void PRCMRTCInUseSet(void);
+extern tBoolean PRCMRTCInUseGet(void);
+extern void PRCMRTCSet(unsigned long ulSecs, unsigned short usMsec);
+extern void PRCMRTCGet(unsigned long *ulSecs, unsigned short *usMsec);
+extern void PRCMRTCMatchSet(unsigned long ulSecs, unsigned short usMsec);
+extern void PRCMRTCMatchGet(unsigned long *ulSecs, unsigned short *usMsec);
+extern void PRCMCC3200MCUInit(void);
+extern unsigned long PRCMHIBRegRead(unsigned long ulRegAddr);
+extern void PRCMHIBRegWrite(unsigned long ulRegAddr, unsigned long ulValue);
+extern unsigned long PRCMCameraFreqSet(unsigned char ulDivider,
+ unsigned char ulWidth);
+extern void PRCMIORetentionEnable(unsigned long ulIORetGrpFlags);
+extern void PRCMIORetentionDisable(unsigned long ulIORetGrpFlags);
+extern unsigned long PRCMDeviceTypeGet(void);
+extern void PRCMLPDSEnterKeepDebugIf(void);
+extern void PRCMHibernateCycleTrigger(void);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __PRCM_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/rom.h b/ext/hal/ti/cc3220sdk/driverlib/rom.h
new file mode 100644
index 0000000..98938cf
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/rom.h
@@ -0,0 +1,2787 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// rom.h - Macros to facilitate calling functions in the ROM.
+//
+//
+//*****************************************************************************
+//
+// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND.
+//
+//*****************************************************************************
+
+#ifndef __ROM_H__
+#define __ROM_H__
+
+//*****************************************************************************
+//
+// For backward compatibility with older Driverlib versions
+//
+//*****************************************************************************
+#ifdef TARGET_IS_CC3200
+#define USE_CC3200_ROM_DRV_API
+#endif
+
+//*****************************************************************************
+//
+// Pointers to the main API tables.
+//
+//*****************************************************************************
+#define ROM_APITABLE ((unsigned long *)0x0000040C)
+#define ROM_VERSION (ROM_APITABLE[0])
+#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1]))
+#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[2]))
+#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[3]))
+#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[4]))
+#define ROM_UDMATABLE ((unsigned long *)(ROM_APITABLE[5]))
+#define ROM_PRCMTABLE ((unsigned long *)(ROM_APITABLE[6]))
+#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[7]))
+#define ROM_SPITABLE ((unsigned long *)(ROM_APITABLE[8]))
+#define ROM_CAMERATABLE ((unsigned long *)(ROM_APITABLE[9]))
+#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[10]))
+#define ROM_PINTABLE ((unsigned long *)(ROM_APITABLE[11]))
+#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[12]))
+#define ROM_UTILSTABLE ((unsigned long *)(ROM_APITABLE[13]))
+#define ROM_I2STABLE ((unsigned long *)(ROM_APITABLE[14]))
+#define ROM_HWSPINLOCKTABLE ((unsigned long *)(ROM_APITABLE[15]))
+#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[16]))
+#define ROM_AESTABLE ((unsigned long *)(ROM_APITABLE[17]))
+#define ROM_DESTABLE ((unsigned long *)(ROM_APITABLE[18]))
+#define ROM_SHAMD5TABLE ((unsigned long *)(ROM_APITABLE[19]))
+#define ROM_CRCTABLE ((unsigned long *)(ROM_APITABLE[20]))
+#define ROM_SDHOSTTABLE ((unsigned long *)(ROM_APITABLE[21]))
+#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[22]))
+#define ROM_CPUTABLE ((unsigned long *)(ROM_APITABLE[23]))
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Interrupt API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntEnable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntMasterEnable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntMasterDisable \
+ ((tBoolean (*)(void))ROM_INTERRUPTTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntDisable \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPriorityGroupingSet \
+ ((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPriorityGroupingGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPrioritySet \
+ ((void (*)(unsigned long ulInterrupt, \
+ unsigned char ucPriority))ROM_INTERRUPTTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPriorityGet \
+ ((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPendSet \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPendClear \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPriorityMaskSet \
+ ((void (*)(unsigned long ulPriorityMask))ROM_INTERRUPTTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntPriorityMaskGet \
+ ((unsigned long (*)(void))ROM_INTERRUPTTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntRegister \
+ ((void (*)(unsigned long ulInterrupt, \
+ void (*pfnHandler)(void)))ROM_INTERRUPTTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntUnregister \
+ ((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_IntVTableBaseSet \
+ ((void (*)(unsigned long ulVtableBase))ROM_INTERRUPTTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Timer API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerConfigure \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulConfig))ROM_TIMERTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerControlLevel \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bInvert))ROM_TIMERTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerControlEvent \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulEvent))ROM_TIMERTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerControlStall \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ tBoolean bStall))ROM_TIMERTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerPrescaleSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerPrescaleGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerPrescaleMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerPrescaleMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerLoadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerLoadGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerMatchSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerMatchGet \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ void (*pfnHandler)(void)))ROM_TIMERTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntUnregister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer))ROM_TIMERTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_TIMERTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_TIMERTABLE[20])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerValueSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTimer, \
+ unsigned long ulValue))ROM_TIMERTABLE[22])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerDMAEventSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAEvent))ROM_TIMERTABLE[23])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_TimerDMAEventGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_TIMERTABLE[24])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UART API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTParityModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulParity))ROM_UARTTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTParityModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_UARTTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_UARTTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long ulBaud, \
+ unsigned long ulConfig))ROM_UARTTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTConfigGetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulUARTClk, \
+ unsigned long *pulBaud, \
+ unsigned long *pulConfig))ROM_UARTTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTDisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFIFOEnable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTCharsAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTSpaceAvail \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTCharGetNonBlocking \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTCharGet \
+ ((long (*)(unsigned long ulBase))ROM_UARTTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTCharPutNonBlocking \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTCharPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char ucData))ROM_UARTTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTBreakCtl \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bBreakState))ROM_UARTTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTBusy \
+ ((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_UARTTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_UARTTABLE[22])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_UARTTABLE[23])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[24])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDMAFlags))ROM_UARTTABLE[25])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTRxErrorGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[26])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTRxErrorClear \
+ ((void (*)(unsigned long ulBase))ROM_UARTTABLE[27])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTModemControlSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulControl))ROM_UARTTABLE[28])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTModemControlClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulControl))ROM_UARTTABLE[29])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTModemControlGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[30])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTModemStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[31])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFlowControlSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_UARTTABLE[32])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTFlowControlGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[33])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTTxIntModeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_UARTTABLE[34])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UARTTxIntModeGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[35])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the uDMA API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelTransferSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulMode, \
+ void *pvSrcAddr, \
+ void *pvDstAddr, \
+ unsigned long ulTransferSize))ROM_UDMATABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAEnable \
+ ((void (*)(void))ROM_UDMATABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMADisable \
+ ((void (*)(void))ROM_UDMATABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAErrorStatusGet \
+ ((unsigned long (*)(void))ROM_UDMATABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAErrorStatusClear \
+ ((void (*)(void))ROM_UDMATABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelEnable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelDisable \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelIsEnabled \
+ ((tBoolean (*)(unsigned long ulChannelNum))ROM_UDMATABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAControlBaseSet \
+ ((void (*)(void *pControlTable))ROM_UDMATABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAControlBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelRequest \
+ ((void (*)(unsigned long ulChannelNum))ROM_UDMATABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelAttributeEnable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelAttributeDisable \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned long ulAttr))ROM_UDMATABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelAttributeGet \
+ ((unsigned long (*)(unsigned long ulChannelNum))ROM_UDMATABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelControlSet \
+ ((void (*)(unsigned long ulChannelStructIndex, \
+ unsigned long ulControl))ROM_UDMATABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelSizeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelModeGet \
+ ((unsigned long (*)(unsigned long ulChannelStructIndex))ROM_UDMATABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAIntStatus \
+ ((unsigned long (*)(void))ROM_UDMATABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAIntClear \
+ ((void (*)(unsigned long ulChanMask))ROM_UDMATABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAControlAlternateBaseGet \
+ ((void * (*)(void))ROM_UDMATABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelScatterGatherSet \
+ ((void (*)(unsigned long ulChannelNum, \
+ unsigned ulTaskCount, \
+ void *pvTaskList, \
+ unsigned long ulIsPeriphSG))ROM_UDMATABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAChannelAssign \
+ ((void (*)(unsigned long ulMapping))ROM_UDMATABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAIntRegister \
+ ((void (*)(unsigned long ulIntChannel, \
+ void (*pfnHandler)(void)))ROM_UDMATABLE[22])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_uDMAIntUnregister \
+ ((void (*)(unsigned long ulIntChannel))ROM_UDMATABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Watchdog API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogIntClear \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogRunning \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogLock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogUnlock \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogLockState \
+ ((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogReloadSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulLoadVal))ROM_WATCHDOGTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogReloadGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_WATCHDOGTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogStallEnable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogStallDisable \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_WATCHDOGTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_WatchdogIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2C API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(pfnHandler)(void)))ROM_I2CTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CTxFIFOConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CTxFIFOFlush \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CRxFIFOConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CRxFIFOFlush \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CFIFOStatus \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CFIFODataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CFIFODataPutNonBlocking \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CFIFODataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CFIFODataGetNonBlocking \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ uint8_t *pui8Data))ROM_I2CTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterBurstLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Length))ROM_I2CTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterBurstCountGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterGlitchFilterConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveFIFOEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_I2CTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveFIFODisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterBusBusy \
+ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterBusy \
+ ((bool (*)(uint32_t ui32Base))ROM_I2CTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterControl \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Cmd))ROM_I2CTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterDataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterDataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[22])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterErr \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[23])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntClear \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[24])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[25])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[26])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntStatus \
+ ((bool (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[27])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntEnableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[28])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntDisableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[29])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntStatusEx \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[30])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterIntClearEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[31])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterTimeoutSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Value))ROM_I2CTABLE[32])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveACKOverride \
+ ((void (*)(uint32_t ui32Base, \
+ bool bEnable))ROM_I2CTABLE[33])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveACKValueSet \
+ ((void (*)(uint32_t ui32Base, \
+ bool bACK))ROM_I2CTABLE[34])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterLineStateGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[35])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterSlaveAddrSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8SlaveAddr, \
+ bool bReceive))ROM_I2CTABLE[36])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveDataGet \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[37])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveDataPut \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8Data))ROM_I2CTABLE[38])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[39])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[40])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveInit \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8SlaveAddr))ROM_I2CTABLE[41])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveAddressSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t ui8AddrNum, \
+ uint8_t ui8SlaveAddr))ROM_I2CTABLE[42])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntClear \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[43])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntDisable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[44])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntEnable \
+ ((void (*)(uint32_t ui32Base))ROM_I2CTABLE[45])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntClearEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[46])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntDisableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[47])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntEnableEx \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_I2CTABLE[48])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntStatus \
+ ((bool (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[49])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveIntStatusEx \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_I2CTABLE[50])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CSlaveStatus \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_I2CTABLE[51])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2CMasterInitExpClk \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32I2CClk, \
+ bool bFast))ROM_I2CTABLE[52])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SPI API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIEnable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDisable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIReset \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSPIClk, \
+ unsigned long ulBitRate, \
+ unsigned long ulMode, \
+ unsigned long ulSubMode, \
+ unsigned long ulConfig))ROM_SPITABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long * pulData))ROM_SPITABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SPITABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SPITABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SPITABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIFIFODisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIFIFOLevelSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulRxLevel))ROM_SPITABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIFIFOLevelGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pulTxLevel, \
+ unsigned long *pulRxLevel))ROM_SPITABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIWordCountSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulWordCount))ROM_SPITABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void(*pfnHandler)(void)))ROM_SPITABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ tBoolean bMasked))ROM_SPITABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SPITABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDmaEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPIDmaDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulFlags))ROM_SPITABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPICSEnable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPICSDisable \
+ ((void (*)(unsigned long ulBase))ROM_SPITABLE[22])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SPITransfer \
+ ((long (*)(unsigned long ulBase, \
+ unsigned char *ucDout, \
+ unsigned char *ucDin, \
+ unsigned long ulSize, \
+ unsigned long ulFlags))ROM_SPITABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CAM API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraReset \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraParamsConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulHSPol, \
+ unsigned long ulVSPol, \
+ unsigned long ulFlags))ROM_CAMERATABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraXClkConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulCamClkIn, \
+ unsigned long ulXClk))ROM_CAMERATABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraXClkSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned char bXClkFlags))ROM_CAMERATABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraDMAEnable \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraDMADisable \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraThresholdSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulThreshold))ROM_CAMERATABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_CAMERATABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_CAMERATABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_CAMERATABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraCaptureStop \
+ ((void (*)(unsigned long ulBase, \
+ tBoolean bImmediate))ROM_CAMERATABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraCaptureStart \
+ ((void (*)(unsigned long ulBase))ROM_CAMERATABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CameraBufferRead \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *pBuffer, \
+ unsigned char ucSize))ROM_CAMERATABLE[15])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the FLASH API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashDisable \
+ ((void (*)(void))ROM_FLASHTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashErase \
+ ((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashMassErase \
+ ((long (*)(void))ROM_FLASHTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashMassEraseNonBlocking \
+ ((void (*)(void))ROM_FLASHTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashEraseNonBlocking \
+ ((void (*)(unsigned long ulAddress))ROM_FLASHTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashProgram \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashProgramNonBlocking \
+ ((long (*)(unsigned long *pulData, \
+ unsigned long ulAddress, \
+ unsigned long ulCount))ROM_FLASHTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_FLASHTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntUnregister \
+ ((void (*)(void))ROM_FLASHTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntStatus \
+ ((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashIntClear \
+ ((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_FlashProtectGet \
+ ((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the Pin API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinModeSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinDirModeSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinIO))ROM_PINTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinDirModeGet \
+ ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinModeGet \
+ ((unsigned long (*)(unsigned long ulPin))ROM_PINTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinConfigGet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long *pulPinStrength, \
+ unsigned long *pulPinType))ROM_PINTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinConfigSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinStrength, \
+ unsigned long ulPinType))ROM_PINTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeUART \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeI2C \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeSPI \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeI2S \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeTimer \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeCamera \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeGPIO \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode, \
+ tBoolean bOpenDrain))ROM_PINTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeADC \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinTypeSDHost \
+ ((void (*)(unsigned long ulPin, \
+ unsigned long ulPinMode))ROM_PINTABLE[14])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinHysteresisSet \
+ ((void (*)(unsigned long ulHysteresis))ROM_PINTABLE[15])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinLockLevelSet \
+ ((void (*)(unsigned long ulPin, \
+ unsigned char ucLevel))ROM_PINTABLE[16])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinLock \
+ ((void (*)(unsigned long ulOutEnable))ROM_PINTABLE[17])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PinUnlock \
+ ((void (*)(void))ROM_PINTABLE[18])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SYSTICK API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_SYSTICKTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickIntUnregister \
+ ((void (*)(void))ROM_SYSTICKTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickIntEnable \
+ ((void (*)(void))ROM_SYSTICKTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickIntDisable \
+ ((void (*)(void))ROM_SYSTICKTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickPeriodSet \
+ ((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickPeriodGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SysTickValueGet \
+ ((unsigned long (*)(void))ROM_SYSTICKTABLE[8])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the UTILS API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_UtilsDelay \
+ ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the I2S API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulMode))ROM_I2STABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SDisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SDataPut \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulData))ROM_I2STABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SDataPutNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulData))ROM_I2STABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SDataGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long *pulData))ROM_I2STABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SDataGetNonBlocking \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long *pulData))ROM_I2STABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SConfigSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulI2SClk, \
+ unsigned long ulBitClk, \
+ unsigned long ulConfig))ROM_I2STABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2STxFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulTxLevel, \
+ unsigned long ulWordsPerTransfer))ROM_I2STABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2STxFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SRxFIFOEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRxLevel, \
+ unsigned long ulWordsPerTransfer))ROM_I2STABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SRxFIFODisable \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2STxFIFOStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SRxFIFOStatusGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SSerializerConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulDataLine, \
+ unsigned long ulSerMode, \
+ unsigned long ulInActState))ROM_I2STABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_I2STABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_I2STABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_I2STABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_I2STABLE[19])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2STxActiveSlotSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulActSlot))ROM_I2STABLE[20])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_I2SRxActiveSlotSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulActSlot))ROM_I2STABLE[21])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the GPIO API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIODirModeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulPinIO))ROM_GPIOTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIODirModeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntTypeSet \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned long ulIntType))ROM_GPIOTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIODMATriggerEnable \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIODMATriggerDisable \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntTypeGet \
+ ((unsigned long (*)(unsigned long ulPort, \
+ unsigned char ucPin))ROM_GPIOTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntEnable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntDisable \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntStatus \
+ ((long (*)(unsigned long ulPort, \
+ tBoolean bMasked))ROM_GPIOTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntClear \
+ ((void (*)(unsigned long ulPort, \
+ unsigned long ulIntFlags))ROM_GPIOTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntRegister \
+ ((void (*)(unsigned long ulPort, \
+ void (*pfnIntHandler)(void)))ROM_GPIOTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOIntUnregister \
+ ((void (*)(unsigned long ulPort))ROM_GPIOTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOPinRead \
+ ((long (*)(unsigned long ulPort, \
+ unsigned char ucPins))ROM_GPIOTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_GPIOPinWrite \
+ ((void (*)(unsigned long ulPort, \
+ unsigned char ucPins, \
+ unsigned char ucVal))ROM_GPIOTABLE[13])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the AES API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_AESTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESKey1Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint32_t ui32Keysize))ROM_AESTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESKey2Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint32_t ui32Keysize))ROM_AESTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESKey3Set \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key))ROM_AESTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIVSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8IVdata))ROM_AESTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESTagRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8TagData))ROM_AESTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint64_t ui64Length))ROM_AESTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESAuthDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_AESTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataReadNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_AESTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_AESTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_AESTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_AESTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length))ROM_AESTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataMAC \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint32_t ui32Length, \
+ uint8_t *pui8Tag))ROM_AESTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDataProcessAE \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length, \
+ uint8_t *pui8AuthSrc, \
+ uint32_t ui32AuthLength, \
+ uint8_t *pui8Tag))ROM_AESTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_AESTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_AESTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_AESTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_AESTABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDMAEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_AESTABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESDMADisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_AESTABLE[22])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_AESIVGet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8IVdata))ROM_AESTABLE[23])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the DES API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Config))ROM_DESTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_DESTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataReadNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest, \
+ uint8_t ui8Length))ROM_DESTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t *pui8Dest, \
+ uint32_t ui32Length))ROM_DESTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_DESTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src, \
+ uint8_t ui8Length))ROM_DESTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDMADisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_DESTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDMAEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Flags))ROM_DESTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_DESTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_DESTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_DESTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_DESTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESIVSet \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8IVdata))ROM_DESTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key))ROM_DESTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_DESDataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_DESTABLE[16])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SHAMD5 API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5ConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Mode))ROM_SHAMD5TABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DataProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8DataSrc, \
+ uint32_t ui32DataLength, \
+ uint8_t *pui8HashResult))ROM_SHAMD5TABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DataWriteNonBlocking \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DMADisable \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DMAEnable \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5DataLengthSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Length))ROM_SHAMD5TABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5HMACKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5HMACPPKeyGenerate \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Key, \
+ uint8_t *pui8PPKey))ROM_SHAMD5TABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5HMACPPKeySet \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Src))ROM_SHAMD5TABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5HMACProcess \
+ ((bool (*)(uint32_t ui32Base, \
+ uint8_t *pui8DataSrc, \
+ uint32_t ui32DataLength, \
+ uint8_t *pui8HashResult))ROM_SHAMD5TABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntClear \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntDisable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntEnable \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32IntFlags))ROM_SHAMD5TABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntRegister \
+ ((void (*)(uint32_t ui32Base, \
+ void(*pfnHandler)(void)))ROM_SHAMD5TABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntStatus \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ bool bMasked))ROM_SHAMD5TABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5IntUnregister \
+ ((void (*)(uint32_t ui32Base))ROM_SHAMD5TABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SHAMD5ResultRead \
+ ((void (*)(uint32_t ui32Base, \
+ uint8_t *pui8Dest))ROM_SHAMD5TABLE[17])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CRC API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CRCConfigSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32CRCConfig))ROM_CRCTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CRCDataProcess \
+ ((uint32_t (*)(uint32_t ui32Base, \
+ void *puiDataIn, \
+ uint32_t ui32DataLength, \
+ uint32_t ui32Config))ROM_CRCTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CRCDataWrite \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Data))ROM_CRCTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CRCResultRead \
+ ((uint32_t (*)(uint32_t ui32Base))ROM_CRCTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CRCSeedSet \
+ ((void (*)(uint32_t ui32Base, \
+ uint32_t ui32Seed))ROM_CRCTABLE[4])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the SDHOST API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostCmdReset \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostInit \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostCmdSend \
+ ((long (*)(unsigned long ulBase, \
+ unsigned long ulCmd, \
+ unsigned ulArg))ROM_SDHOSTTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ void (*pfnHandler)(void)))ROM_SDHOSTTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntUnregister \
+ ((void (*)(unsigned long ulBase))ROM_SDHOSTTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntStatus \
+ ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulIntFlags))ROM_SDHOSTTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostRespGet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulRespnse[4]))ROM_SDHOSTTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostBlockSizeSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned short ulBlkSize))ROM_SDHOSTTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostBlockCountSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned short ulBlkCount))ROM_SDHOSTTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostDataNonBlockingWrite \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SDHOSTTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostDataNonBlockingRead \
+ ((tBoolean (*)(unsigned long ulBase, \
+ unsigned long *pulData))ROM_SDHOSTTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostDataWrite \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulData))ROM_SDHOSTTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostDataRead \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long *ulData))ROM_SDHOSTTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostSetExpClk \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulSDHostClk, \
+ unsigned long ulCardClk))ROM_SDHOSTTABLE[17])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostCardErrorMaskSet \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulErrMask))ROM_SDHOSTTABLE[18])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_SDHostCardErrorMaskGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_SDHOSTTABLE[19])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the PRCM API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMMCUReset \
+ ((void (*)(tBoolean bIncludeSubsystem))ROM_PRCMTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSysResetCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMPeripheralClkEnable \
+ ((void (*)(unsigned long ulPeripheral, \
+ unsigned long ulClkFlags))ROM_PRCMTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMPeripheralClkDisable \
+ ((void (*)(unsigned long ulPeripheral, \
+ unsigned long ulClkFlags))ROM_PRCMTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMPeripheralReset \
+ ((void (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMPeripheralStatusGet \
+ ((tBoolean (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMI2SClockFreqSet \
+ ((void (*)(unsigned long ulI2CClkFreq))ROM_PRCMTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMPeripheralClockGet \
+ ((unsigned long (*)(unsigned long ulPeripheral))ROM_PRCMTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSleepEnter \
+ ((void (*)(void))ROM_PRCMTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSRAMRetentionEnable \
+ ((void (*)(unsigned long ulSramColSel, \
+ unsigned long ulFlags))ROM_PRCMTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSRAMRetentionDisable \
+ ((void (*)(unsigned long ulSramColSel, \
+ unsigned long ulFlags))ROM_PRCMTABLE[12])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSEnter \
+ ((void (*)(void))ROM_PRCMTABLE[13])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSIntervalSet \
+ ((void (*)(unsigned long ulTicks))ROM_PRCMTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSWakeupSourceEnable \
+ ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSWakeupCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSWakeUpGPIOSelect \
+ ((void (*)(unsigned long ulGPIOPin, \
+ unsigned long ulType))ROM_PRCMTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSWakeupSourceDisable \
+ ((void (*)(unsigned long ulLpdsWakeupSrc))ROM_PRCMTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateEnter \
+ ((void (*)(void))ROM_PRCMTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateWakeupSourceEnable \
+ ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[20])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateWakeupCauseGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[21])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateWakeUpGPIOSelect \
+ ((void (*)(unsigned long ulMultiGPIOBitMap, \
+ unsigned long ulType))ROM_PRCMTABLE[22])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateWakeupSourceDisable \
+ ((void (*)(unsigned long ulHIBWakupSrc))ROM_PRCMTABLE[23])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateIntervalSet \
+ ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[24])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSlowClkCtrGet \
+ ((unsigned long long (*)(void))ROM_PRCMTABLE[25])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSlowClkCtrMatchSet \
+ ((void (*)(unsigned long long ullTicks))ROM_PRCMTABLE[26])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSlowClkCtrMatchGet \
+ ((unsigned long long (*)(void))ROM_PRCMTABLE[27])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMOCRRegisterWrite \
+ ((void (*)(unsigned char ucIndex, \
+ unsigned long ulRegValue))ROM_PRCMTABLE[28])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMOCRRegisterRead \
+ ((unsigned long (*)(unsigned char ucIndex))ROM_PRCMTABLE[29])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIntRegister \
+ ((void (*)(void (*pfnHandler)(void)))ROM_PRCMTABLE[30])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIntUnregister \
+ ((void (*)(void))ROM_PRCMTABLE[31])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIntEnable \
+ ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[32])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIntDisable \
+ ((void (*)(unsigned long ulIntFlags))ROM_PRCMTABLE[33])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIntStatus \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[34])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCInUseSet \
+ ((void (*)(void))ROM_PRCMTABLE[35])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCInUseGet \
+ ((tBoolean (*)(void))ROM_PRCMTABLE[36])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCSet \
+ ((void (*)(unsigned long ulSecs, \
+ unsigned short usMsec))ROM_PRCMTABLE[37])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCGet \
+ ((void (*)(unsigned long *ulSecs, \
+ unsigned short *usMsec))ROM_PRCMTABLE[38])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCMatchSet \
+ ((void (*)(unsigned long ulSecs, \
+ unsigned short usMsec))ROM_PRCMTABLE[39])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMRTCMatchGet \
+ ((void (*)(unsigned long *ulSecs, \
+ unsigned short *usMsec))ROM_PRCMTABLE[40])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSRestoreInfoSet \
+ ((void (*)(unsigned long ulRestoreSP, \
+ unsigned long ulRestorePC))ROM_PRCMTABLE[41])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMSlowClkCtrFastGet \
+ ((unsigned long long (*)(void))ROM_PRCMTABLE[42])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMCC3200MCUInit \
+ ((void (*)(void))ROM_PRCMTABLE[43])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHIBRegRead \
+ ((unsigned long (*)(unsigned long ulRegAddr))ROM_PRCMTABLE[44])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHIBRegWrite \
+ ((void (*)(unsigned long ulRegAddr, \
+ unsigned long ulValue))ROM_PRCMTABLE[45])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMCameraFreqSet \
+ ((unsigned long (*)(unsigned char ulDivider, \
+ unsigned char ulWidth))ROM_PRCMTABLE[46])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIORetentionEnable \
+ ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[47])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMIORetentionDisable \
+ ((void (*)(unsigned long ulIORetGrpFlags))ROM_PRCMTABLE[48])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMDeviceTypeGet \
+ ((unsigned long (*)(void))ROM_PRCMTABLE[49])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMLPDSEnterKeepDebugIf \
+ ((void (*)(void))ROM_PRCMTABLE[50])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_PRCMHibernateCycleTrigger \
+ ((void (*)(void))ROM_PRCMTABLE[51])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the HWSPINLOCK API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_HwSpinLockAcquire \
+ ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_HwSpinLockTryAcquire \
+ ((int32_t (*)(uint32_t ui32LockID, \
+ uint32_t ui32Retry))ROM_HWSPINLOCKTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_HwSpinLockRelease \
+ ((void (*)(uint32_t ui32LockID))ROM_HWSPINLOCKTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_HwSpinLockTest \
+ ((uint32_t (*)(uint32_t ui32LockID, \
+ bool bCurrentStatus))ROM_HWSPINLOCKTABLE[3])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the ADC API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCEnable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[0])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCDisable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[1])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCChannelEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[2])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCChannelDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[3])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntRegister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ void (*pfnHandler)(void)))ROM_ADCTABLE[4])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntUnregister \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[5])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[6])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntDisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[7])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntStatus \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[8])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCIntClear \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel, \
+ unsigned long ulIntFlags))ROM_ADCTABLE[9])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCDMAEnable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[10])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCDMADisable \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[11])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCTimerConfig \
+ ((void (*)(unsigned long ulBase, \
+ unsigned long ulValue))ROM_ADCTABLE[14])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCTimerEnable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[15])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCTimerDisable \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[16])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCTimerReset \
+ ((void (*)(unsigned long ulBase))ROM_ADCTABLE[17])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCTimerValueGet \
+ ((unsigned long (*)(unsigned long ulBase))ROM_ADCTABLE[18])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCFIFOLvlGet \
+ ((unsigned char (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[19])
+#endif
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define ROM_ADCFIFORead \
+ ((unsigned long (*)(unsigned long ulBase, \
+ unsigned long ulChannel))ROM_ADCTABLE[20])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions in the CPU API.
+//
+//*****************************************************************************
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUcpsid \
+ ((unsigned long (*)(void))ROM_CPUTABLE[0])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUcpsie \
+ ((unsigned long (*)(void))ROM_CPUTABLE[1])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUprimask \
+ ((unsigned long (*)(void))ROM_CPUTABLE[2])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUwfi \
+ ((void (*)(void))ROM_CPUTABLE[3])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUbasepriGet \
+ ((unsigned long (*)(void))ROM_CPUTABLE[4])
+#endif
+#if defined(USE_CC3220_ROM_DRV_API)
+#define ROM_CPUbasepriSet \
+ ((void (*)(unsigned long ulNewBasepri))ROM_CPUTABLE[5])
+#endif
+
+//*****************************************************************************
+//
+// Macros for calling ROM functions Directly.
+//
+//*****************************************************************************
+#define ROM_UtilsDelayDirect \
+ ((void (*)(unsigned long ulCount))ROM_UTILSTABLE[0])
+
+#define ROM_PRCMLPDSEnterDirect \
+ ((void (*)(void))ROM_PRCMTABLE[13])
+
+#define ROM_PRCMLPDSEnterKeepDebugIfDirect \
+ ((void (*)(void))ROM_PRCMTABLE[50])
+
+#endif // __ROM_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/rom_map.h b/ext/hal/ti/cc3220sdk/driverlib/rom_map.h
new file mode 100644
index 0000000..3fb6838
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/rom_map.h
@@ -0,0 +1,3321 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// rom_map.h - Macros to facilitate calling functions in the ROM when they are
+// available.
+//
+//*****************************************************************************
+//*****************************************************************************
+//
+// THIS IS AN AUTO-GENERATED FILE. DO NOT EDIT BY HAND.
+//
+//*****************************************************************************
+
+#ifndef __ROM_MAP_H__
+#define __ROM_MAP_H__
+
+//*****************************************************************************
+// Patched ROM APIs
+//*****************************************************************************
+#include "rom_patch.h"
+
+//*****************************************************************************
+//
+// Macros for the Interrupt API.
+//
+//*****************************************************************************
+#ifdef ROM_IntEnable
+#define MAP_IntEnable \
+ ROM_IntEnable
+#else
+#define MAP_IntEnable \
+ IntEnable
+#endif
+#ifdef ROM_IntMasterEnable
+#define MAP_IntMasterEnable \
+ ROM_IntMasterEnable
+#else
+#define MAP_IntMasterEnable \
+ IntMasterEnable
+#endif
+#ifdef ROM_IntMasterDisable
+#define MAP_IntMasterDisable \
+ ROM_IntMasterDisable
+#else
+#define MAP_IntMasterDisable \
+ IntMasterDisable
+#endif
+#ifdef ROM_IntDisable
+#define MAP_IntDisable \
+ ROM_IntDisable
+#else
+#define MAP_IntDisable \
+ IntDisable
+#endif
+#ifdef ROM_IntPriorityGroupingSet
+#define MAP_IntPriorityGroupingSet \
+ ROM_IntPriorityGroupingSet
+#else
+#define MAP_IntPriorityGroupingSet \
+ IntPriorityGroupingSet
+#endif
+#ifdef ROM_IntPriorityGroupingGet
+#define MAP_IntPriorityGroupingGet \
+ ROM_IntPriorityGroupingGet
+#else
+#define MAP_IntPriorityGroupingGet \
+ IntPriorityGroupingGet
+#endif
+#ifdef ROM_IntPrioritySet
+#define MAP_IntPrioritySet \
+ ROM_IntPrioritySet
+#else
+#define MAP_IntPrioritySet \
+ IntPrioritySet
+#endif
+#ifdef ROM_IntPriorityGet
+#define MAP_IntPriorityGet \
+ ROM_IntPriorityGet
+#else
+#define MAP_IntPriorityGet \
+ IntPriorityGet
+#endif
+#ifdef ROM_IntPendSet
+#define MAP_IntPendSet \
+ ROM_IntPendSet
+#else
+#define MAP_IntPendSet \
+ IntPendSet
+#endif
+#ifdef ROM_IntPendClear
+#define MAP_IntPendClear \
+ ROM_IntPendClear
+#else
+#define MAP_IntPendClear \
+ IntPendClear
+#endif
+#ifdef ROM_IntPriorityMaskSet
+#define MAP_IntPriorityMaskSet \
+ ROM_IntPriorityMaskSet
+#else
+#define MAP_IntPriorityMaskSet \
+ IntPriorityMaskSet
+#endif
+#ifdef ROM_IntPriorityMaskGet
+#define MAP_IntPriorityMaskGet \
+ ROM_IntPriorityMaskGet
+#else
+#define MAP_IntPriorityMaskGet \
+ IntPriorityMaskGet
+#endif
+#ifdef ROM_IntRegister
+#define MAP_IntRegister \
+ ROM_IntRegister
+#else
+#define MAP_IntRegister \
+ IntRegister
+#endif
+#ifdef ROM_IntUnregister
+#define MAP_IntUnregister \
+ ROM_IntUnregister
+#else
+#define MAP_IntUnregister \
+ IntUnregister
+#endif
+#ifdef ROM_IntVTableBaseSet
+#define MAP_IntVTableBaseSet \
+ ROM_IntVTableBaseSet
+#else
+#define MAP_IntVTableBaseSet \
+ IntVTableBaseSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Timer API.
+//
+//*****************************************************************************
+#ifdef ROM_TimerEnable
+#define MAP_TimerEnable \
+ ROM_TimerEnable
+#else
+#define MAP_TimerEnable \
+ TimerEnable
+#endif
+#ifdef ROM_TimerDisable
+#define MAP_TimerDisable \
+ ROM_TimerDisable
+#else
+#define MAP_TimerDisable \
+ TimerDisable
+#endif
+#ifdef ROM_TimerConfigure
+#define MAP_TimerConfigure \
+ ROM_TimerConfigure
+#else
+#define MAP_TimerConfigure \
+ TimerConfigure
+#endif
+#ifdef ROM_TimerControlLevel
+#define MAP_TimerControlLevel \
+ ROM_TimerControlLevel
+#else
+#define MAP_TimerControlLevel \
+ TimerControlLevel
+#endif
+#ifdef ROM_TimerControlEvent
+#define MAP_TimerControlEvent \
+ ROM_TimerControlEvent
+#else
+#define MAP_TimerControlEvent \
+ TimerControlEvent
+#endif
+#ifdef ROM_TimerControlStall
+#define MAP_TimerControlStall \
+ ROM_TimerControlStall
+#else
+#define MAP_TimerControlStall \
+ TimerControlStall
+#endif
+#ifdef ROM_TimerPrescaleSet
+#define MAP_TimerPrescaleSet \
+ ROM_TimerPrescaleSet
+#else
+#define MAP_TimerPrescaleSet \
+ TimerPrescaleSet
+#endif
+#ifdef ROM_TimerPrescaleGet
+#define MAP_TimerPrescaleGet \
+ ROM_TimerPrescaleGet
+#else
+#define MAP_TimerPrescaleGet \
+ TimerPrescaleGet
+#endif
+#ifdef ROM_TimerPrescaleMatchSet
+#define MAP_TimerPrescaleMatchSet \
+ ROM_TimerPrescaleMatchSet
+#else
+#define MAP_TimerPrescaleMatchSet \
+ TimerPrescaleMatchSet
+#endif
+#ifdef ROM_TimerPrescaleMatchGet
+#define MAP_TimerPrescaleMatchGet \
+ ROM_TimerPrescaleMatchGet
+#else
+#define MAP_TimerPrescaleMatchGet \
+ TimerPrescaleMatchGet
+#endif
+#ifdef ROM_TimerLoadSet
+#define MAP_TimerLoadSet \
+ ROM_TimerLoadSet
+#else
+#define MAP_TimerLoadSet \
+ TimerLoadSet
+#endif
+#ifdef ROM_TimerLoadGet
+#define MAP_TimerLoadGet \
+ ROM_TimerLoadGet
+#else
+#define MAP_TimerLoadGet \
+ TimerLoadGet
+#endif
+#ifdef ROM_TimerValueGet
+#define MAP_TimerValueGet \
+ ROM_TimerValueGet
+#else
+#define MAP_TimerValueGet \
+ TimerValueGet
+#endif
+#ifdef ROM_TimerMatchSet
+#define MAP_TimerMatchSet \
+ ROM_TimerMatchSet
+#else
+#define MAP_TimerMatchSet \
+ TimerMatchSet
+#endif
+#ifdef ROM_TimerMatchGet
+#define MAP_TimerMatchGet \
+ ROM_TimerMatchGet
+#else
+#define MAP_TimerMatchGet \
+ TimerMatchGet
+#endif
+#ifdef ROM_TimerIntRegister
+#define MAP_TimerIntRegister \
+ ROM_TimerIntRegister
+#else
+#define MAP_TimerIntRegister \
+ TimerIntRegister
+#endif
+#ifdef ROM_TimerIntUnregister
+#define MAP_TimerIntUnregister \
+ ROM_TimerIntUnregister
+#else
+#define MAP_TimerIntUnregister \
+ TimerIntUnregister
+#endif
+#ifdef ROM_TimerIntEnable
+#define MAP_TimerIntEnable \
+ ROM_TimerIntEnable
+#else
+#define MAP_TimerIntEnable \
+ TimerIntEnable
+#endif
+#ifdef ROM_TimerIntDisable
+#define MAP_TimerIntDisable \
+ ROM_TimerIntDisable
+#else
+#define MAP_TimerIntDisable \
+ TimerIntDisable
+#endif
+#ifdef ROM_TimerIntStatus
+#define MAP_TimerIntStatus \
+ ROM_TimerIntStatus
+#else
+#define MAP_TimerIntStatus \
+ TimerIntStatus
+#endif
+#ifdef ROM_TimerIntClear
+#define MAP_TimerIntClear \
+ ROM_TimerIntClear
+#else
+#define MAP_TimerIntClear \
+ TimerIntClear
+#endif
+#ifdef ROM_TimerValueSet
+#define MAP_TimerValueSet \
+ ROM_TimerValueSet
+#else
+#define MAP_TimerValueSet \
+ TimerValueSet
+#endif
+#ifdef ROM_TimerDMAEventSet
+#define MAP_TimerDMAEventSet \
+ ROM_TimerDMAEventSet
+#else
+#define MAP_TimerDMAEventSet \
+ TimerDMAEventSet
+#endif
+#ifdef ROM_TimerDMAEventGet
+#define MAP_TimerDMAEventGet \
+ ROM_TimerDMAEventGet
+#else
+#define MAP_TimerDMAEventGet \
+ TimerDMAEventGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UART API.
+//
+//*****************************************************************************
+#ifdef ROM_UARTParityModeSet
+#define MAP_UARTParityModeSet \
+ ROM_UARTParityModeSet
+#else
+#define MAP_UARTParityModeSet \
+ UARTParityModeSet
+#endif
+#ifdef ROM_UARTParityModeGet
+#define MAP_UARTParityModeGet \
+ ROM_UARTParityModeGet
+#else
+#define MAP_UARTParityModeGet \
+ UARTParityModeGet
+#endif
+#ifdef ROM_UARTFIFOLevelSet
+#define MAP_UARTFIFOLevelSet \
+ ROM_UARTFIFOLevelSet
+#else
+#define MAP_UARTFIFOLevelSet \
+ UARTFIFOLevelSet
+#endif
+#ifdef ROM_UARTFIFOLevelGet
+#define MAP_UARTFIFOLevelGet \
+ ROM_UARTFIFOLevelGet
+#else
+#define MAP_UARTFIFOLevelGet \
+ UARTFIFOLevelGet
+#endif
+#ifdef ROM_UARTConfigSetExpClk
+#define MAP_UARTConfigSetExpClk \
+ ROM_UARTConfigSetExpClk
+#else
+#define MAP_UARTConfigSetExpClk \
+ UARTConfigSetExpClk
+#endif
+#ifdef ROM_UARTConfigGetExpClk
+#define MAP_UARTConfigGetExpClk \
+ ROM_UARTConfigGetExpClk
+#else
+#define MAP_UARTConfigGetExpClk \
+ UARTConfigGetExpClk
+#endif
+#ifdef ROM_UARTEnable
+#define MAP_UARTEnable \
+ ROM_UARTEnable
+#else
+#define MAP_UARTEnable \
+ UARTEnable
+#endif
+#ifdef ROM_UARTDisable
+#define MAP_UARTDisable \
+ ROM_UARTDisable
+#else
+#define MAP_UARTDisable \
+ UARTDisable
+#endif
+#ifdef ROM_UARTFIFOEnable
+#define MAP_UARTFIFOEnable \
+ ROM_UARTFIFOEnable
+#else
+#define MAP_UARTFIFOEnable \
+ UARTFIFOEnable
+#endif
+#ifdef ROM_UARTFIFODisable
+#define MAP_UARTFIFODisable \
+ ROM_UARTFIFODisable
+#else
+#define MAP_UARTFIFODisable \
+ UARTFIFODisable
+#endif
+#ifdef ROM_UARTCharsAvail
+#define MAP_UARTCharsAvail \
+ ROM_UARTCharsAvail
+#else
+#define MAP_UARTCharsAvail \
+ UARTCharsAvail
+#endif
+#ifdef ROM_UARTSpaceAvail
+#define MAP_UARTSpaceAvail \
+ ROM_UARTSpaceAvail
+#else
+#define MAP_UARTSpaceAvail \
+ UARTSpaceAvail
+#endif
+#ifdef ROM_UARTCharGetNonBlocking
+#define MAP_UARTCharGetNonBlocking \
+ ROM_UARTCharGetNonBlocking
+#else
+#define MAP_UARTCharGetNonBlocking \
+ UARTCharGetNonBlocking
+#endif
+#ifdef ROM_UARTCharGet
+#define MAP_UARTCharGet \
+ ROM_UARTCharGet
+#else
+#define MAP_UARTCharGet \
+ UARTCharGet
+#endif
+#ifdef ROM_UARTCharPutNonBlocking
+#define MAP_UARTCharPutNonBlocking \
+ ROM_UARTCharPutNonBlocking
+#else
+#define MAP_UARTCharPutNonBlocking \
+ UARTCharPutNonBlocking
+#endif
+#ifdef ROM_UARTCharPut
+#define MAP_UARTCharPut \
+ ROM_UARTCharPut
+#else
+#define MAP_UARTCharPut \
+ UARTCharPut
+#endif
+#ifdef ROM_UARTBreakCtl
+#define MAP_UARTBreakCtl \
+ ROM_UARTBreakCtl
+#else
+#define MAP_UARTBreakCtl \
+ UARTBreakCtl
+#endif
+#ifdef ROM_UARTBusy
+#define MAP_UARTBusy \
+ ROM_UARTBusy
+#else
+#define MAP_UARTBusy \
+ UARTBusy
+#endif
+#ifdef ROM_UARTIntRegister
+#define MAP_UARTIntRegister \
+ ROM_UARTIntRegister
+#else
+#define MAP_UARTIntRegister \
+ UARTIntRegister
+#endif
+#ifdef ROM_UARTIntUnregister
+#define MAP_UARTIntUnregister \
+ ROM_UARTIntUnregister
+#else
+#define MAP_UARTIntUnregister \
+ UARTIntUnregister
+#endif
+#ifdef ROM_UARTIntEnable
+#define MAP_UARTIntEnable \
+ ROM_UARTIntEnable
+#else
+#define MAP_UARTIntEnable \
+ UARTIntEnable
+#endif
+#ifdef ROM_UARTIntDisable
+#define MAP_UARTIntDisable \
+ ROM_UARTIntDisable
+#else
+#define MAP_UARTIntDisable \
+ UARTIntDisable
+#endif
+#ifdef ROM_UARTIntStatus
+#define MAP_UARTIntStatus \
+ ROM_UARTIntStatus
+#else
+#define MAP_UARTIntStatus \
+ UARTIntStatus
+#endif
+#ifdef ROM_UARTIntClear
+#define MAP_UARTIntClear \
+ ROM_UARTIntClear
+#else
+#define MAP_UARTIntClear \
+ UARTIntClear
+#endif
+#ifdef ROM_UARTDMAEnable
+#define MAP_UARTDMAEnable \
+ ROM_UARTDMAEnable
+#else
+#define MAP_UARTDMAEnable \
+ UARTDMAEnable
+#endif
+#ifdef ROM_UARTDMADisable
+#define MAP_UARTDMADisable \
+ ROM_UARTDMADisable
+#else
+#define MAP_UARTDMADisable \
+ UARTDMADisable
+#endif
+#ifdef ROM_UARTRxErrorGet
+#define MAP_UARTRxErrorGet \
+ ROM_UARTRxErrorGet
+#else
+#define MAP_UARTRxErrorGet \
+ UARTRxErrorGet
+#endif
+#ifdef ROM_UARTRxErrorClear
+#define MAP_UARTRxErrorClear \
+ ROM_UARTRxErrorClear
+#else
+#define MAP_UARTRxErrorClear \
+ UARTRxErrorClear
+#endif
+#ifdef ROM_UARTModemControlSet
+#define MAP_UARTModemControlSet \
+ ROM_UARTModemControlSet
+#else
+#define MAP_UARTModemControlSet \
+ UARTModemControlSet
+#endif
+#ifdef ROM_UARTModemControlClear
+#define MAP_UARTModemControlClear \
+ ROM_UARTModemControlClear
+#else
+#define MAP_UARTModemControlClear \
+ UARTModemControlClear
+#endif
+#ifdef ROM_UARTModemControlGet
+#define MAP_UARTModemControlGet \
+ ROM_UARTModemControlGet
+#else
+#define MAP_UARTModemControlGet \
+ UARTModemControlGet
+#endif
+#ifdef ROM_UARTModemStatusGet
+#define MAP_UARTModemStatusGet \
+ ROM_UARTModemStatusGet
+#else
+#define MAP_UARTModemStatusGet \
+ UARTModemStatusGet
+#endif
+#ifdef ROM_UARTFlowControlSet
+#define MAP_UARTFlowControlSet \
+ ROM_UARTFlowControlSet
+#else
+#define MAP_UARTFlowControlSet \
+ UARTFlowControlSet
+#endif
+#ifdef ROM_UARTFlowControlGet
+#define MAP_UARTFlowControlGet \
+ ROM_UARTFlowControlGet
+#else
+#define MAP_UARTFlowControlGet \
+ UARTFlowControlGet
+#endif
+#ifdef ROM_UARTTxIntModeSet
+#define MAP_UARTTxIntModeSet \
+ ROM_UARTTxIntModeSet
+#else
+#define MAP_UARTTxIntModeSet \
+ UARTTxIntModeSet
+#endif
+#ifdef ROM_UARTTxIntModeGet
+#define MAP_UARTTxIntModeGet \
+ ROM_UARTTxIntModeGet
+#else
+#define MAP_UARTTxIntModeGet \
+ UARTTxIntModeGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the uDMA API.
+//
+//*****************************************************************************
+#ifdef ROM_uDMAChannelTransferSet
+#define MAP_uDMAChannelTransferSet \
+ ROM_uDMAChannelTransferSet
+#else
+#define MAP_uDMAChannelTransferSet \
+ uDMAChannelTransferSet
+#endif
+#ifdef ROM_uDMAEnable
+#define MAP_uDMAEnable \
+ ROM_uDMAEnable
+#else
+#define MAP_uDMAEnable \
+ uDMAEnable
+#endif
+#ifdef ROM_uDMADisable
+#define MAP_uDMADisable \
+ ROM_uDMADisable
+#else
+#define MAP_uDMADisable \
+ uDMADisable
+#endif
+#ifdef ROM_uDMAErrorStatusGet
+#define MAP_uDMAErrorStatusGet \
+ ROM_uDMAErrorStatusGet
+#else
+#define MAP_uDMAErrorStatusGet \
+ uDMAErrorStatusGet
+#endif
+#ifdef ROM_uDMAErrorStatusClear
+#define MAP_uDMAErrorStatusClear \
+ ROM_uDMAErrorStatusClear
+#else
+#define MAP_uDMAErrorStatusClear \
+ uDMAErrorStatusClear
+#endif
+#ifdef ROM_uDMAChannelEnable
+#define MAP_uDMAChannelEnable \
+ ROM_uDMAChannelEnable
+#else
+#define MAP_uDMAChannelEnable \
+ uDMAChannelEnable
+#endif
+#ifdef ROM_uDMAChannelDisable
+#define MAP_uDMAChannelDisable \
+ ROM_uDMAChannelDisable
+#else
+#define MAP_uDMAChannelDisable \
+ uDMAChannelDisable
+#endif
+#ifdef ROM_uDMAChannelIsEnabled
+#define MAP_uDMAChannelIsEnabled \
+ ROM_uDMAChannelIsEnabled
+#else
+#define MAP_uDMAChannelIsEnabled \
+ uDMAChannelIsEnabled
+#endif
+#ifdef ROM_uDMAControlBaseSet
+#define MAP_uDMAControlBaseSet \
+ ROM_uDMAControlBaseSet
+#else
+#define MAP_uDMAControlBaseSet \
+ uDMAControlBaseSet
+#endif
+#ifdef ROM_uDMAControlBaseGet
+#define MAP_uDMAControlBaseGet \
+ ROM_uDMAControlBaseGet
+#else
+#define MAP_uDMAControlBaseGet \
+ uDMAControlBaseGet
+#endif
+#ifdef ROM_uDMAChannelRequest
+#define MAP_uDMAChannelRequest \
+ ROM_uDMAChannelRequest
+#else
+#define MAP_uDMAChannelRequest \
+ uDMAChannelRequest
+#endif
+#ifdef ROM_uDMAChannelAttributeEnable
+#define MAP_uDMAChannelAttributeEnable \
+ ROM_uDMAChannelAttributeEnable
+#else
+#define MAP_uDMAChannelAttributeEnable \
+ uDMAChannelAttributeEnable
+#endif
+#ifdef ROM_uDMAChannelAttributeDisable
+#define MAP_uDMAChannelAttributeDisable \
+ ROM_uDMAChannelAttributeDisable
+#else
+#define MAP_uDMAChannelAttributeDisable \
+ uDMAChannelAttributeDisable
+#endif
+#ifdef ROM_uDMAChannelAttributeGet
+#define MAP_uDMAChannelAttributeGet \
+ ROM_uDMAChannelAttributeGet
+#else
+#define MAP_uDMAChannelAttributeGet \
+ uDMAChannelAttributeGet
+#endif
+#ifdef ROM_uDMAChannelControlSet
+#define MAP_uDMAChannelControlSet \
+ ROM_uDMAChannelControlSet
+#else
+#define MAP_uDMAChannelControlSet \
+ uDMAChannelControlSet
+#endif
+#ifdef ROM_uDMAChannelSizeGet
+#define MAP_uDMAChannelSizeGet \
+ ROM_uDMAChannelSizeGet
+#else
+#define MAP_uDMAChannelSizeGet \
+ uDMAChannelSizeGet
+#endif
+#ifdef ROM_uDMAChannelModeGet
+#define MAP_uDMAChannelModeGet \
+ ROM_uDMAChannelModeGet
+#else
+#define MAP_uDMAChannelModeGet \
+ uDMAChannelModeGet
+#endif
+#ifdef ROM_uDMAIntStatus
+#define MAP_uDMAIntStatus \
+ ROM_uDMAIntStatus
+#else
+#define MAP_uDMAIntStatus \
+ uDMAIntStatus
+#endif
+#ifdef ROM_uDMAIntClear
+#define MAP_uDMAIntClear \
+ ROM_uDMAIntClear
+#else
+#define MAP_uDMAIntClear \
+ uDMAIntClear
+#endif
+#ifdef ROM_uDMAControlAlternateBaseGet
+#define MAP_uDMAControlAlternateBaseGet \
+ ROM_uDMAControlAlternateBaseGet
+#else
+#define MAP_uDMAControlAlternateBaseGet \
+ uDMAControlAlternateBaseGet
+#endif
+#ifdef ROM_uDMAChannelScatterGatherSet
+#define MAP_uDMAChannelScatterGatherSet \
+ ROM_uDMAChannelScatterGatherSet
+#else
+#define MAP_uDMAChannelScatterGatherSet \
+ uDMAChannelScatterGatherSet
+#endif
+#ifdef ROM_uDMAChannelAssign
+#define MAP_uDMAChannelAssign \
+ ROM_uDMAChannelAssign
+#else
+#define MAP_uDMAChannelAssign \
+ uDMAChannelAssign
+#endif
+#ifdef ROM_uDMAIntRegister
+#define MAP_uDMAIntRegister \
+ ROM_uDMAIntRegister
+#else
+#define MAP_uDMAIntRegister \
+ uDMAIntRegister
+#endif
+#ifdef ROM_uDMAIntUnregister
+#define MAP_uDMAIntUnregister \
+ ROM_uDMAIntUnregister
+#else
+#define MAP_uDMAIntUnregister \
+ uDMAIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Watchdog API.
+//
+//*****************************************************************************
+#ifdef ROM_WatchdogIntClear
+#define MAP_WatchdogIntClear \
+ ROM_WatchdogIntClear
+#else
+#define MAP_WatchdogIntClear \
+ WatchdogIntClear
+#endif
+#ifdef ROM_WatchdogRunning
+#define MAP_WatchdogRunning \
+ ROM_WatchdogRunning
+#else
+#define MAP_WatchdogRunning \
+ WatchdogRunning
+#endif
+#ifdef ROM_WatchdogEnable
+#define MAP_WatchdogEnable \
+ ROM_WatchdogEnable
+#else
+#define MAP_WatchdogEnable \
+ WatchdogEnable
+#endif
+#ifdef ROM_WatchdogLock
+#define MAP_WatchdogLock \
+ ROM_WatchdogLock
+#else
+#define MAP_WatchdogLock \
+ WatchdogLock
+#endif
+#ifdef ROM_WatchdogUnlock
+#define MAP_WatchdogUnlock \
+ ROM_WatchdogUnlock
+#else
+#define MAP_WatchdogUnlock \
+ WatchdogUnlock
+#endif
+#ifdef ROM_WatchdogLockState
+#define MAP_WatchdogLockState \
+ ROM_WatchdogLockState
+#else
+#define MAP_WatchdogLockState \
+ WatchdogLockState
+#endif
+#ifdef ROM_WatchdogReloadSet
+#define MAP_WatchdogReloadSet \
+ ROM_WatchdogReloadSet
+#else
+#define MAP_WatchdogReloadSet \
+ WatchdogReloadSet
+#endif
+#ifdef ROM_WatchdogReloadGet
+#define MAP_WatchdogReloadGet \
+ ROM_WatchdogReloadGet
+#else
+#define MAP_WatchdogReloadGet \
+ WatchdogReloadGet
+#endif
+#ifdef ROM_WatchdogValueGet
+#define MAP_WatchdogValueGet \
+ ROM_WatchdogValueGet
+#else
+#define MAP_WatchdogValueGet \
+ WatchdogValueGet
+#endif
+#ifdef ROM_WatchdogIntStatus
+#define MAP_WatchdogIntStatus \
+ ROM_WatchdogIntStatus
+#else
+#define MAP_WatchdogIntStatus \
+ WatchdogIntStatus
+#endif
+#ifdef ROM_WatchdogStallEnable
+#define MAP_WatchdogStallEnable \
+ ROM_WatchdogStallEnable
+#else
+#define MAP_WatchdogStallEnable \
+ WatchdogStallEnable
+#endif
+#ifdef ROM_WatchdogStallDisable
+#define MAP_WatchdogStallDisable \
+ ROM_WatchdogStallDisable
+#else
+#define MAP_WatchdogStallDisable \
+ WatchdogStallDisable
+#endif
+#ifdef ROM_WatchdogIntRegister
+#define MAP_WatchdogIntRegister \
+ ROM_WatchdogIntRegister
+#else
+#define MAP_WatchdogIntRegister \
+ WatchdogIntRegister
+#endif
+#ifdef ROM_WatchdogIntUnregister
+#define MAP_WatchdogIntUnregister \
+ ROM_WatchdogIntUnregister
+#else
+#define MAP_WatchdogIntUnregister \
+ WatchdogIntUnregister
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2C API.
+//
+//*****************************************************************************
+#ifdef ROM_I2CIntRegister
+#define MAP_I2CIntRegister \
+ ROM_I2CIntRegister
+#else
+#define MAP_I2CIntRegister \
+ I2CIntRegister
+#endif
+#ifdef ROM_I2CIntUnregister
+#define MAP_I2CIntUnregister \
+ ROM_I2CIntUnregister
+#else
+#define MAP_I2CIntUnregister \
+ I2CIntUnregister
+#endif
+#ifdef ROM_I2CTxFIFOConfigSet
+#define MAP_I2CTxFIFOConfigSet \
+ ROM_I2CTxFIFOConfigSet
+#else
+#define MAP_I2CTxFIFOConfigSet \
+ I2CTxFIFOConfigSet
+#endif
+#ifdef ROM_I2CTxFIFOFlush
+#define MAP_I2CTxFIFOFlush \
+ ROM_I2CTxFIFOFlush
+#else
+#define MAP_I2CTxFIFOFlush \
+ I2CTxFIFOFlush
+#endif
+#ifdef ROM_I2CRxFIFOConfigSet
+#define MAP_I2CRxFIFOConfigSet \
+ ROM_I2CRxFIFOConfigSet
+#else
+#define MAP_I2CRxFIFOConfigSet \
+ I2CRxFIFOConfigSet
+#endif
+#ifdef ROM_I2CRxFIFOFlush
+#define MAP_I2CRxFIFOFlush \
+ ROM_I2CRxFIFOFlush
+#else
+#define MAP_I2CRxFIFOFlush \
+ I2CRxFIFOFlush
+#endif
+#ifdef ROM_I2CFIFOStatus
+#define MAP_I2CFIFOStatus \
+ ROM_I2CFIFOStatus
+#else
+#define MAP_I2CFIFOStatus \
+ I2CFIFOStatus
+#endif
+#ifdef ROM_I2CFIFODataPut
+#define MAP_I2CFIFODataPut \
+ ROM_I2CFIFODataPut
+#else
+#define MAP_I2CFIFODataPut \
+ I2CFIFODataPut
+#endif
+#ifdef ROM_I2CFIFODataPutNonBlocking
+#define MAP_I2CFIFODataPutNonBlocking \
+ ROM_I2CFIFODataPutNonBlocking
+#else
+#define MAP_I2CFIFODataPutNonBlocking \
+ I2CFIFODataPutNonBlocking
+#endif
+#ifdef ROM_I2CFIFODataGet
+#define MAP_I2CFIFODataGet \
+ ROM_I2CFIFODataGet
+#else
+#define MAP_I2CFIFODataGet \
+ I2CFIFODataGet
+#endif
+#ifdef ROM_I2CFIFODataGetNonBlocking
+#define MAP_I2CFIFODataGetNonBlocking \
+ ROM_I2CFIFODataGetNonBlocking
+#else
+#define MAP_I2CFIFODataGetNonBlocking \
+ I2CFIFODataGetNonBlocking
+#endif
+#ifdef ROM_I2CMasterBurstLengthSet
+#define MAP_I2CMasterBurstLengthSet \
+ ROM_I2CMasterBurstLengthSet
+#else
+#define MAP_I2CMasterBurstLengthSet \
+ I2CMasterBurstLengthSet
+#endif
+#ifdef ROM_I2CMasterBurstCountGet
+#define MAP_I2CMasterBurstCountGet \
+ ROM_I2CMasterBurstCountGet
+#else
+#define MAP_I2CMasterBurstCountGet \
+ I2CMasterBurstCountGet
+#endif
+#ifdef ROM_I2CMasterGlitchFilterConfigSet
+#define MAP_I2CMasterGlitchFilterConfigSet \
+ ROM_I2CMasterGlitchFilterConfigSet
+#else
+#define MAP_I2CMasterGlitchFilterConfigSet \
+ I2CMasterGlitchFilterConfigSet
+#endif
+#ifdef ROM_I2CSlaveFIFOEnable
+#define MAP_I2CSlaveFIFOEnable \
+ ROM_I2CSlaveFIFOEnable
+#else
+#define MAP_I2CSlaveFIFOEnable \
+ I2CSlaveFIFOEnable
+#endif
+#ifdef ROM_I2CSlaveFIFODisable
+#define MAP_I2CSlaveFIFODisable \
+ ROM_I2CSlaveFIFODisable
+#else
+#define MAP_I2CSlaveFIFODisable \
+ I2CSlaveFIFODisable
+#endif
+#ifdef ROM_I2CMasterBusBusy
+#define MAP_I2CMasterBusBusy \
+ ROM_I2CMasterBusBusy
+#else
+#define MAP_I2CMasterBusBusy \
+ I2CMasterBusBusy
+#endif
+#ifdef ROM_I2CMasterBusy
+#define MAP_I2CMasterBusy \
+ ROM_I2CMasterBusy
+#else
+#define MAP_I2CMasterBusy \
+ I2CMasterBusy
+#endif
+#ifdef ROM_I2CMasterControl
+#define MAP_I2CMasterControl \
+ ROM_I2CMasterControl
+#else
+#define MAP_I2CMasterControl \
+ I2CMasterControl
+#endif
+#ifdef ROM_I2CMasterDataGet
+#define MAP_I2CMasterDataGet \
+ ROM_I2CMasterDataGet
+#else
+#define MAP_I2CMasterDataGet \
+ I2CMasterDataGet
+#endif
+#ifdef ROM_I2CMasterDataPut
+#define MAP_I2CMasterDataPut \
+ ROM_I2CMasterDataPut
+#else
+#define MAP_I2CMasterDataPut \
+ I2CMasterDataPut
+#endif
+#ifdef ROM_I2CMasterDisable
+#define MAP_I2CMasterDisable \
+ ROM_I2CMasterDisable
+#else
+#define MAP_I2CMasterDisable \
+ I2CMasterDisable
+#endif
+#ifdef ROM_I2CMasterEnable
+#define MAP_I2CMasterEnable \
+ ROM_I2CMasterEnable
+#else
+#define MAP_I2CMasterEnable \
+ I2CMasterEnable
+#endif
+#ifdef ROM_I2CMasterErr
+#define MAP_I2CMasterErr \
+ ROM_I2CMasterErr
+#else
+#define MAP_I2CMasterErr \
+ I2CMasterErr
+#endif
+#ifdef ROM_I2CMasterIntClear
+#define MAP_I2CMasterIntClear \
+ ROM_I2CMasterIntClear
+#else
+#define MAP_I2CMasterIntClear \
+ I2CMasterIntClear
+#endif
+#ifdef ROM_I2CMasterIntDisable
+#define MAP_I2CMasterIntDisable \
+ ROM_I2CMasterIntDisable
+#else
+#define MAP_I2CMasterIntDisable \
+ I2CMasterIntDisable
+#endif
+#ifdef ROM_I2CMasterIntEnable
+#define MAP_I2CMasterIntEnable \
+ ROM_I2CMasterIntEnable
+#else
+#define MAP_I2CMasterIntEnable \
+ I2CMasterIntEnable
+#endif
+#ifdef ROM_I2CMasterIntStatus
+#define MAP_I2CMasterIntStatus \
+ ROM_I2CMasterIntStatus
+#else
+#define MAP_I2CMasterIntStatus \
+ I2CMasterIntStatus
+#endif
+#ifdef ROM_I2CMasterIntEnableEx
+#define MAP_I2CMasterIntEnableEx \
+ ROM_I2CMasterIntEnableEx
+#else
+#define MAP_I2CMasterIntEnableEx \
+ I2CMasterIntEnableEx
+#endif
+#ifdef ROM_I2CMasterIntDisableEx
+#define MAP_I2CMasterIntDisableEx \
+ ROM_I2CMasterIntDisableEx
+#else
+#define MAP_I2CMasterIntDisableEx \
+ I2CMasterIntDisableEx
+#endif
+#ifdef ROM_I2CMasterIntStatusEx
+#define MAP_I2CMasterIntStatusEx \
+ ROM_I2CMasterIntStatusEx
+#else
+#define MAP_I2CMasterIntStatusEx \
+ I2CMasterIntStatusEx
+#endif
+#ifdef ROM_I2CMasterIntClearEx
+#define MAP_I2CMasterIntClearEx \
+ ROM_I2CMasterIntClearEx
+#else
+#define MAP_I2CMasterIntClearEx \
+ I2CMasterIntClearEx
+#endif
+#ifdef ROM_I2CMasterTimeoutSet
+#define MAP_I2CMasterTimeoutSet \
+ ROM_I2CMasterTimeoutSet
+#else
+#define MAP_I2CMasterTimeoutSet \
+ I2CMasterTimeoutSet
+#endif
+#ifdef ROM_I2CSlaveACKOverride
+#define MAP_I2CSlaveACKOverride \
+ ROM_I2CSlaveACKOverride
+#else
+#define MAP_I2CSlaveACKOverride \
+ I2CSlaveACKOverride
+#endif
+#ifdef ROM_I2CSlaveACKValueSet
+#define MAP_I2CSlaveACKValueSet \
+ ROM_I2CSlaveACKValueSet
+#else
+#define MAP_I2CSlaveACKValueSet \
+ I2CSlaveACKValueSet
+#endif
+#ifdef ROM_I2CMasterLineStateGet
+#define MAP_I2CMasterLineStateGet \
+ ROM_I2CMasterLineStateGet
+#else
+#define MAP_I2CMasterLineStateGet \
+ I2CMasterLineStateGet
+#endif
+#ifdef ROM_I2CMasterSlaveAddrSet
+#define MAP_I2CMasterSlaveAddrSet \
+ ROM_I2CMasterSlaveAddrSet
+#else
+#define MAP_I2CMasterSlaveAddrSet \
+ I2CMasterSlaveAddrSet
+#endif
+#ifdef ROM_I2CSlaveDataGet
+#define MAP_I2CSlaveDataGet \
+ ROM_I2CSlaveDataGet
+#else
+#define MAP_I2CSlaveDataGet \
+ I2CSlaveDataGet
+#endif
+#ifdef ROM_I2CSlaveDataPut
+#define MAP_I2CSlaveDataPut \
+ ROM_I2CSlaveDataPut
+#else
+#define MAP_I2CSlaveDataPut \
+ I2CSlaveDataPut
+#endif
+#ifdef ROM_I2CSlaveDisable
+#define MAP_I2CSlaveDisable \
+ ROM_I2CSlaveDisable
+#else
+#define MAP_I2CSlaveDisable \
+ I2CSlaveDisable
+#endif
+#ifdef ROM_I2CSlaveEnable
+#define MAP_I2CSlaveEnable \
+ ROM_I2CSlaveEnable
+#else
+#define MAP_I2CSlaveEnable \
+ I2CSlaveEnable
+#endif
+#ifdef ROM_I2CSlaveInit
+#define MAP_I2CSlaveInit \
+ ROM_I2CSlaveInit
+#else
+#define MAP_I2CSlaveInit \
+ I2CSlaveInit
+#endif
+#ifdef ROM_I2CSlaveAddressSet
+#define MAP_I2CSlaveAddressSet \
+ ROM_I2CSlaveAddressSet
+#else
+#define MAP_I2CSlaveAddressSet \
+ I2CSlaveAddressSet
+#endif
+#ifdef ROM_I2CSlaveIntClear
+#define MAP_I2CSlaveIntClear \
+ ROM_I2CSlaveIntClear
+#else
+#define MAP_I2CSlaveIntClear \
+ I2CSlaveIntClear
+#endif
+#ifdef ROM_I2CSlaveIntDisable
+#define MAP_I2CSlaveIntDisable \
+ ROM_I2CSlaveIntDisable
+#else
+#define MAP_I2CSlaveIntDisable \
+ I2CSlaveIntDisable
+#endif
+#ifdef ROM_I2CSlaveIntEnable
+#define MAP_I2CSlaveIntEnable \
+ ROM_I2CSlaveIntEnable
+#else
+#define MAP_I2CSlaveIntEnable \
+ I2CSlaveIntEnable
+#endif
+#ifdef ROM_I2CSlaveIntClearEx
+#define MAP_I2CSlaveIntClearEx \
+ ROM_I2CSlaveIntClearEx
+#else
+#define MAP_I2CSlaveIntClearEx \
+ I2CSlaveIntClearEx
+#endif
+#ifdef ROM_I2CSlaveIntDisableEx
+#define MAP_I2CSlaveIntDisableEx \
+ ROM_I2CSlaveIntDisableEx
+#else
+#define MAP_I2CSlaveIntDisableEx \
+ I2CSlaveIntDisableEx
+#endif
+#ifdef ROM_I2CSlaveIntEnableEx
+#define MAP_I2CSlaveIntEnableEx \
+ ROM_I2CSlaveIntEnableEx
+#else
+#define MAP_I2CSlaveIntEnableEx \
+ I2CSlaveIntEnableEx
+#endif
+#ifdef ROM_I2CSlaveIntStatus
+#define MAP_I2CSlaveIntStatus \
+ ROM_I2CSlaveIntStatus
+#else
+#define MAP_I2CSlaveIntStatus \
+ I2CSlaveIntStatus
+#endif
+#ifdef ROM_I2CSlaveIntStatusEx
+#define MAP_I2CSlaveIntStatusEx \
+ ROM_I2CSlaveIntStatusEx
+#else
+#define MAP_I2CSlaveIntStatusEx \
+ I2CSlaveIntStatusEx
+#endif
+#ifdef ROM_I2CSlaveStatus
+#define MAP_I2CSlaveStatus \
+ ROM_I2CSlaveStatus
+#else
+#define MAP_I2CSlaveStatus \
+ I2CSlaveStatus
+#endif
+#ifdef ROM_I2CMasterInitExpClk
+#define MAP_I2CMasterInitExpClk \
+ ROM_I2CMasterInitExpClk
+#else
+#define MAP_I2CMasterInitExpClk \
+ I2CMasterInitExpClk
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SPI API.
+//
+//*****************************************************************************
+#ifdef ROM_SPIEnable
+#define MAP_SPIEnable \
+ ROM_SPIEnable
+#else
+#define MAP_SPIEnable \
+ SPIEnable
+#endif
+#ifdef ROM_SPIDisable
+#define MAP_SPIDisable \
+ ROM_SPIDisable
+#else
+#define MAP_SPIDisable \
+ SPIDisable
+#endif
+#ifdef ROM_SPIReset
+#define MAP_SPIReset \
+ ROM_SPIReset
+#else
+#define MAP_SPIReset \
+ SPIReset
+#endif
+#ifdef ROM_SPIConfigSetExpClk
+#define MAP_SPIConfigSetExpClk \
+ ROM_SPIConfigSetExpClk
+#else
+#define MAP_SPIConfigSetExpClk \
+ SPIConfigSetExpClk
+#endif
+#ifdef ROM_SPIDataGetNonBlocking
+#define MAP_SPIDataGetNonBlocking \
+ ROM_SPIDataGetNonBlocking
+#else
+#define MAP_SPIDataGetNonBlocking \
+ SPIDataGetNonBlocking
+#endif
+#ifdef ROM_SPIDataGet
+#define MAP_SPIDataGet \
+ ROM_SPIDataGet
+#else
+#define MAP_SPIDataGet \
+ SPIDataGet
+#endif
+#ifdef ROM_SPIDataPutNonBlocking
+#define MAP_SPIDataPutNonBlocking \
+ ROM_SPIDataPutNonBlocking
+#else
+#define MAP_SPIDataPutNonBlocking \
+ SPIDataPutNonBlocking
+#endif
+#ifdef ROM_SPIDataPut
+#define MAP_SPIDataPut \
+ ROM_SPIDataPut
+#else
+#define MAP_SPIDataPut \
+ SPIDataPut
+#endif
+#ifdef ROM_SPIFIFOEnable
+#define MAP_SPIFIFOEnable \
+ ROM_SPIFIFOEnable
+#else
+#define MAP_SPIFIFOEnable \
+ SPIFIFOEnable
+#endif
+#ifdef ROM_SPIFIFODisable
+#define MAP_SPIFIFODisable \
+ ROM_SPIFIFODisable
+#else
+#define MAP_SPIFIFODisable \
+ SPIFIFODisable
+#endif
+#ifdef ROM_SPIFIFOLevelSet
+#define MAP_SPIFIFOLevelSet \
+ ROM_SPIFIFOLevelSet
+#else
+#define MAP_SPIFIFOLevelSet \
+ SPIFIFOLevelSet
+#endif
+#ifdef ROM_SPIFIFOLevelGet
+#define MAP_SPIFIFOLevelGet \
+ ROM_SPIFIFOLevelGet
+#else
+#define MAP_SPIFIFOLevelGet \
+ SPIFIFOLevelGet
+#endif
+#ifdef ROM_SPIWordCountSet
+#define MAP_SPIWordCountSet \
+ ROM_SPIWordCountSet
+#else
+#define MAP_SPIWordCountSet \
+ SPIWordCountSet
+#endif
+#ifdef ROM_SPIIntRegister
+#define MAP_SPIIntRegister \
+ ROM_SPIIntRegister
+#else
+#define MAP_SPIIntRegister \
+ SPIIntRegister
+#endif
+#ifdef ROM_SPIIntUnregister
+#define MAP_SPIIntUnregister \
+ ROM_SPIIntUnregister
+#else
+#define MAP_SPIIntUnregister \
+ SPIIntUnregister
+#endif
+#ifdef ROM_SPIIntEnable
+#define MAP_SPIIntEnable \
+ ROM_SPIIntEnable
+#else
+#define MAP_SPIIntEnable \
+ SPIIntEnable
+#endif
+#ifdef ROM_SPIIntDisable
+#define MAP_SPIIntDisable \
+ ROM_SPIIntDisable
+#else
+#define MAP_SPIIntDisable \
+ SPIIntDisable
+#endif
+#ifdef ROM_SPIIntStatus
+#define MAP_SPIIntStatus \
+ ROM_SPIIntStatus
+#else
+#define MAP_SPIIntStatus \
+ SPIIntStatus
+#endif
+#ifdef ROM_SPIIntClear
+#define MAP_SPIIntClear \
+ ROM_SPIIntClear
+#else
+#define MAP_SPIIntClear \
+ SPIIntClear
+#endif
+#ifdef ROM_SPIDmaEnable
+#define MAP_SPIDmaEnable \
+ ROM_SPIDmaEnable
+#else
+#define MAP_SPIDmaEnable \
+ SPIDmaEnable
+#endif
+#ifdef ROM_SPIDmaDisable
+#define MAP_SPIDmaDisable \
+ ROM_SPIDmaDisable
+#else
+#define MAP_SPIDmaDisable \
+ SPIDmaDisable
+#endif
+#ifdef ROM_SPICSEnable
+#define MAP_SPICSEnable \
+ ROM_SPICSEnable
+#else
+#define MAP_SPICSEnable \
+ SPICSEnable
+#endif
+#ifdef ROM_SPICSDisable
+#define MAP_SPICSDisable \
+ ROM_SPICSDisable
+#else
+#define MAP_SPICSDisable \
+ SPICSDisable
+#endif
+#ifdef ROM_SPITransfer
+#define MAP_SPITransfer \
+ ROM_SPITransfer
+#else
+#define MAP_SPITransfer \
+ SPITransfer
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CAM API.
+//
+//*****************************************************************************
+#ifdef ROM_CameraReset
+#define MAP_CameraReset \
+ ROM_CameraReset
+#else
+#define MAP_CameraReset \
+ CameraReset
+#endif
+#ifdef ROM_CameraParamsConfig
+#define MAP_CameraParamsConfig \
+ ROM_CameraParamsConfig
+#else
+#define MAP_CameraParamsConfig \
+ CameraParamsConfig
+#endif
+#ifdef ROM_CameraXClkConfig
+#define MAP_CameraXClkConfig \
+ ROM_CameraXClkConfig
+#else
+#define MAP_CameraXClkConfig \
+ CameraXClkConfig
+#endif
+#ifdef ROM_CameraXClkSet
+#define MAP_CameraXClkSet \
+ ROM_CameraXClkSet
+#else
+#define MAP_CameraXClkSet \
+ CameraXClkSet
+#endif
+#ifdef ROM_CameraDMAEnable
+#define MAP_CameraDMAEnable \
+ ROM_CameraDMAEnable
+#else
+#define MAP_CameraDMAEnable \
+ CameraDMAEnable
+#endif
+#ifdef ROM_CameraDMADisable
+#define MAP_CameraDMADisable \
+ ROM_CameraDMADisable
+#else
+#define MAP_CameraDMADisable \
+ CameraDMADisable
+#endif
+#ifdef ROM_CameraThresholdSet
+#define MAP_CameraThresholdSet \
+ ROM_CameraThresholdSet
+#else
+#define MAP_CameraThresholdSet \
+ CameraThresholdSet
+#endif
+#ifdef ROM_CameraIntRegister
+#define MAP_CameraIntRegister \
+ ROM_CameraIntRegister
+#else
+#define MAP_CameraIntRegister \
+ CameraIntRegister
+#endif
+#ifdef ROM_CameraIntUnregister
+#define MAP_CameraIntUnregister \
+ ROM_CameraIntUnregister
+#else
+#define MAP_CameraIntUnregister \
+ CameraIntUnregister
+#endif
+#ifdef ROM_CameraIntEnable
+#define MAP_CameraIntEnable \
+ ROM_CameraIntEnable
+#else
+#define MAP_CameraIntEnable \
+ CameraIntEnable
+#endif
+#ifdef ROM_CameraIntDisable
+#define MAP_CameraIntDisable \
+ ROM_CameraIntDisable
+#else
+#define MAP_CameraIntDisable \
+ CameraIntDisable
+#endif
+#ifdef ROM_CameraIntStatus
+#define MAP_CameraIntStatus \
+ ROM_CameraIntStatus
+#else
+#define MAP_CameraIntStatus \
+ CameraIntStatus
+#endif
+#ifdef ROM_CameraIntClear
+#define MAP_CameraIntClear \
+ ROM_CameraIntClear
+#else
+#define MAP_CameraIntClear \
+ CameraIntClear
+#endif
+#ifdef ROM_CameraCaptureStop
+#define MAP_CameraCaptureStop \
+ ROM_CameraCaptureStop
+#else
+#define MAP_CameraCaptureStop \
+ CameraCaptureStop
+#endif
+#ifdef ROM_CameraCaptureStart
+#define MAP_CameraCaptureStart \
+ ROM_CameraCaptureStart
+#else
+#define MAP_CameraCaptureStart \
+ CameraCaptureStart
+#endif
+#ifdef ROM_CameraBufferRead
+#define MAP_CameraBufferRead \
+ ROM_CameraBufferRead
+#else
+#define MAP_CameraBufferRead \
+ CameraBufferRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the FLASH API.
+//
+//*****************************************************************************
+#ifdef ROM_FlashDisable
+#define MAP_FlashDisable \
+ ROM_FlashDisable
+#else
+#define MAP_FlashDisable \
+ FlashDisable
+#endif
+#ifdef ROM_FlashErase
+#define MAP_FlashErase \
+ ROM_FlashErase
+#else
+#define MAP_FlashErase \
+ FlashErase
+#endif
+#ifdef ROM_FlashMassErase
+#define MAP_FlashMassErase \
+ ROM_FlashMassErase
+#else
+#define MAP_FlashMassErase \
+ FlashMassErase
+#endif
+#ifdef ROM_FlashMassEraseNonBlocking
+#define MAP_FlashMassEraseNonBlocking \
+ ROM_FlashMassEraseNonBlocking
+#else
+#define MAP_FlashMassEraseNonBlocking \
+ FlashMassEraseNonBlocking
+#endif
+#ifdef ROM_FlashEraseNonBlocking
+#define MAP_FlashEraseNonBlocking \
+ ROM_FlashEraseNonBlocking
+#else
+#define MAP_FlashEraseNonBlocking \
+ FlashEraseNonBlocking
+#endif
+#ifdef ROM_FlashProgram
+#define MAP_FlashProgram \
+ ROM_FlashProgram
+#else
+#define MAP_FlashProgram \
+ FlashProgram
+#endif
+#ifdef ROM_FlashProgramNonBlocking
+#define MAP_FlashProgramNonBlocking \
+ ROM_FlashProgramNonBlocking
+#else
+#define MAP_FlashProgramNonBlocking \
+ FlashProgramNonBlocking
+#endif
+#ifdef ROM_FlashIntRegister
+#define MAP_FlashIntRegister \
+ ROM_FlashIntRegister
+#else
+#define MAP_FlashIntRegister \
+ FlashIntRegister
+#endif
+#ifdef ROM_FlashIntUnregister
+#define MAP_FlashIntUnregister \
+ ROM_FlashIntUnregister
+#else
+#define MAP_FlashIntUnregister \
+ FlashIntUnregister
+#endif
+#ifdef ROM_FlashIntEnable
+#define MAP_FlashIntEnable \
+ ROM_FlashIntEnable
+#else
+#define MAP_FlashIntEnable \
+ FlashIntEnable
+#endif
+#ifdef ROM_FlashIntDisable
+#define MAP_FlashIntDisable \
+ ROM_FlashIntDisable
+#else
+#define MAP_FlashIntDisable \
+ FlashIntDisable
+#endif
+#ifdef ROM_FlashIntStatus
+#define MAP_FlashIntStatus \
+ ROM_FlashIntStatus
+#else
+#define MAP_FlashIntStatus \
+ FlashIntStatus
+#endif
+#ifdef ROM_FlashIntClear
+#define MAP_FlashIntClear \
+ ROM_FlashIntClear
+#else
+#define MAP_FlashIntClear \
+ FlashIntClear
+#endif
+#ifdef ROM_FlashProtectGet
+#define MAP_FlashProtectGet \
+ ROM_FlashProtectGet
+#else
+#define MAP_FlashProtectGet \
+ FlashProtectGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the Pin API.
+//
+//*****************************************************************************
+#ifdef ROM_PinModeSet
+#define MAP_PinModeSet \
+ ROM_PinModeSet
+#else
+#define MAP_PinModeSet \
+ PinModeSet
+#endif
+#ifdef ROM_PinDirModeSet
+#define MAP_PinDirModeSet \
+ ROM_PinDirModeSet
+#else
+#define MAP_PinDirModeSet \
+ PinDirModeSet
+#endif
+#ifdef ROM_PinDirModeGet
+#define MAP_PinDirModeGet \
+ ROM_PinDirModeGet
+#else
+#define MAP_PinDirModeGet \
+ PinDirModeGet
+#endif
+#ifdef ROM_PinModeGet
+#define MAP_PinModeGet \
+ ROM_PinModeGet
+#else
+#define MAP_PinModeGet \
+ PinModeGet
+#endif
+#ifdef ROM_PinConfigGet
+#define MAP_PinConfigGet \
+ ROM_PinConfigGet
+#else
+#define MAP_PinConfigGet \
+ PinConfigGet
+#endif
+#ifdef ROM_PinConfigSet
+#define MAP_PinConfigSet \
+ ROM_PinConfigSet
+#else
+#define MAP_PinConfigSet \
+ PinConfigSet
+#endif
+#ifdef ROM_PinTypeUART
+#define MAP_PinTypeUART \
+ ROM_PinTypeUART
+#else
+#define MAP_PinTypeUART \
+ PinTypeUART
+#endif
+#ifdef ROM_PinTypeI2C
+#define MAP_PinTypeI2C \
+ ROM_PinTypeI2C
+#else
+#define MAP_PinTypeI2C \
+ PinTypeI2C
+#endif
+#ifdef ROM_PinTypeSPI
+#define MAP_PinTypeSPI \
+ ROM_PinTypeSPI
+#else
+#define MAP_PinTypeSPI \
+ PinTypeSPI
+#endif
+#ifdef ROM_PinTypeI2S
+#define MAP_PinTypeI2S \
+ ROM_PinTypeI2S
+#else
+#define MAP_PinTypeI2S \
+ PinTypeI2S
+#endif
+#ifdef ROM_PinTypeTimer
+#define MAP_PinTypeTimer \
+ ROM_PinTypeTimer
+#else
+#define MAP_PinTypeTimer \
+ PinTypeTimer
+#endif
+#ifdef ROM_PinTypeCamera
+#define MAP_PinTypeCamera \
+ ROM_PinTypeCamera
+#else
+#define MAP_PinTypeCamera \
+ PinTypeCamera
+#endif
+#ifdef ROM_PinTypeGPIO
+#define MAP_PinTypeGPIO \
+ ROM_PinTypeGPIO
+#else
+#define MAP_PinTypeGPIO \
+ PinTypeGPIO
+#endif
+#ifdef ROM_PinTypeADC
+#define MAP_PinTypeADC \
+ ROM_PinTypeADC
+#else
+#define MAP_PinTypeADC \
+ PinTypeADC
+#endif
+#ifdef ROM_PinTypeSDHost
+#define MAP_PinTypeSDHost \
+ ROM_PinTypeSDHost
+#else
+#define MAP_PinTypeSDHost \
+ PinTypeSDHost
+#endif
+#ifdef ROM_PinHysteresisSet
+#define MAP_PinHysteresisSet \
+ ROM_PinHysteresisSet
+#else
+#define MAP_PinHysteresisSet \
+ PinHysteresisSet
+#endif
+#ifdef ROM_PinLockLevelSet
+#define MAP_PinLockLevelSet \
+ ROM_PinLockLevelSet
+#else
+#define MAP_PinLockLevelSet \
+ PinLockLevelSet
+#endif
+#ifdef ROM_PinLock
+#define MAP_PinLock \
+ ROM_PinLock
+#else
+#define MAP_PinLock \
+ PinLock
+#endif
+#ifdef ROM_PinUnlock
+#define MAP_PinUnlock \
+ ROM_PinUnlock
+#else
+#define MAP_PinUnlock \
+ PinUnlock
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SYSTICK API.
+//
+//*****************************************************************************
+#ifdef ROM_SysTickEnable
+#define MAP_SysTickEnable \
+ ROM_SysTickEnable
+#else
+#define MAP_SysTickEnable \
+ SysTickEnable
+#endif
+#ifdef ROM_SysTickDisable
+#define MAP_SysTickDisable \
+ ROM_SysTickDisable
+#else
+#define MAP_SysTickDisable \
+ SysTickDisable
+#endif
+#ifdef ROM_SysTickIntRegister
+#define MAP_SysTickIntRegister \
+ ROM_SysTickIntRegister
+#else
+#define MAP_SysTickIntRegister \
+ SysTickIntRegister
+#endif
+#ifdef ROM_SysTickIntUnregister
+#define MAP_SysTickIntUnregister \
+ ROM_SysTickIntUnregister
+#else
+#define MAP_SysTickIntUnregister \
+ SysTickIntUnregister
+#endif
+#ifdef ROM_SysTickIntEnable
+#define MAP_SysTickIntEnable \
+ ROM_SysTickIntEnable
+#else
+#define MAP_SysTickIntEnable \
+ SysTickIntEnable
+#endif
+#ifdef ROM_SysTickIntDisable
+#define MAP_SysTickIntDisable \
+ ROM_SysTickIntDisable
+#else
+#define MAP_SysTickIntDisable \
+ SysTickIntDisable
+#endif
+#ifdef ROM_SysTickPeriodSet
+#define MAP_SysTickPeriodSet \
+ ROM_SysTickPeriodSet
+#else
+#define MAP_SysTickPeriodSet \
+ SysTickPeriodSet
+#endif
+#ifdef ROM_SysTickPeriodGet
+#define MAP_SysTickPeriodGet \
+ ROM_SysTickPeriodGet
+#else
+#define MAP_SysTickPeriodGet \
+ SysTickPeriodGet
+#endif
+#ifdef ROM_SysTickValueGet
+#define MAP_SysTickValueGet \
+ ROM_SysTickValueGet
+#else
+#define MAP_SysTickValueGet \
+ SysTickValueGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the UTILS API.
+//
+//*****************************************************************************
+#if defined(USE_CC3200_ROM_DRV_API) || \
+ defined(USE_CC3220_ROM_DRV_API)
+#define MAP_UtilsDelay \
+ ROM_UtilsDelay
+#else
+#define MAP_UtilsDelay \
+ UtilsDelay
+#endif
+
+//*****************************************************************************
+//
+// Macros for the I2S API.
+//
+//*****************************************************************************
+#ifdef ROM_I2SEnable
+#define MAP_I2SEnable \
+ ROM_I2SEnable
+#else
+#define MAP_I2SEnable \
+ I2SEnable
+#endif
+#ifdef ROM_I2SDisable
+#define MAP_I2SDisable \
+ ROM_I2SDisable
+#else
+#define MAP_I2SDisable \
+ I2SDisable
+#endif
+#ifdef ROM_I2SDataPut
+#define MAP_I2SDataPut \
+ ROM_I2SDataPut
+#else
+#define MAP_I2SDataPut \
+ I2SDataPut
+#endif
+#ifdef ROM_I2SDataPutNonBlocking
+#define MAP_I2SDataPutNonBlocking \
+ ROM_I2SDataPutNonBlocking
+#else
+#define MAP_I2SDataPutNonBlocking \
+ I2SDataPutNonBlocking
+#endif
+#ifdef ROM_I2SDataGet
+#define MAP_I2SDataGet \
+ ROM_I2SDataGet
+#else
+#define MAP_I2SDataGet \
+ I2SDataGet
+#endif
+#ifdef ROM_I2SDataGetNonBlocking
+#define MAP_I2SDataGetNonBlocking \
+ ROM_I2SDataGetNonBlocking
+#else
+#define MAP_I2SDataGetNonBlocking \
+ I2SDataGetNonBlocking
+#endif
+#ifdef ROM_I2SConfigSetExpClk
+#define MAP_I2SConfigSetExpClk \
+ ROM_I2SConfigSetExpClk
+#else
+#define MAP_I2SConfigSetExpClk \
+ I2SConfigSetExpClk
+#endif
+#ifdef ROM_I2STxFIFOEnable
+#define MAP_I2STxFIFOEnable \
+ ROM_I2STxFIFOEnable
+#else
+#define MAP_I2STxFIFOEnable \
+ I2STxFIFOEnable
+#endif
+#ifdef ROM_I2STxFIFODisable
+#define MAP_I2STxFIFODisable \
+ ROM_I2STxFIFODisable
+#else
+#define MAP_I2STxFIFODisable \
+ I2STxFIFODisable
+#endif
+#ifdef ROM_I2SRxFIFOEnable
+#define MAP_I2SRxFIFOEnable \
+ ROM_I2SRxFIFOEnable
+#else
+#define MAP_I2SRxFIFOEnable \
+ I2SRxFIFOEnable
+#endif
+#ifdef ROM_I2SRxFIFODisable
+#define MAP_I2SRxFIFODisable \
+ ROM_I2SRxFIFODisable
+#else
+#define MAP_I2SRxFIFODisable \
+ I2SRxFIFODisable
+#endif
+#ifdef ROM_I2STxFIFOStatusGet
+#define MAP_I2STxFIFOStatusGet \
+ ROM_I2STxFIFOStatusGet
+#else
+#define MAP_I2STxFIFOStatusGet \
+ I2STxFIFOStatusGet
+#endif
+#ifdef ROM_I2SRxFIFOStatusGet
+#define MAP_I2SRxFIFOStatusGet \
+ ROM_I2SRxFIFOStatusGet
+#else
+#define MAP_I2SRxFIFOStatusGet \
+ I2SRxFIFOStatusGet
+#endif
+#ifdef ROM_I2SSerializerConfig
+#define MAP_I2SSerializerConfig \
+ ROM_I2SSerializerConfig
+#else
+#define MAP_I2SSerializerConfig \
+ I2SSerializerConfig
+#endif
+#ifdef ROM_I2SIntEnable
+#define MAP_I2SIntEnable \
+ ROM_I2SIntEnable
+#else
+#define MAP_I2SIntEnable \
+ I2SIntEnable
+#endif
+#ifdef ROM_I2SIntDisable
+#define MAP_I2SIntDisable \
+ ROM_I2SIntDisable
+#else
+#define MAP_I2SIntDisable \
+ I2SIntDisable
+#endif
+#ifdef ROM_I2SIntStatus
+#define MAP_I2SIntStatus \
+ ROM_I2SIntStatus
+#else
+#define MAP_I2SIntStatus \
+ I2SIntStatus
+#endif
+#ifdef ROM_I2SIntClear
+#define MAP_I2SIntClear \
+ ROM_I2SIntClear
+#else
+#define MAP_I2SIntClear \
+ I2SIntClear
+#endif
+#ifdef ROM_I2SIntRegister
+#define MAP_I2SIntRegister \
+ ROM_I2SIntRegister
+#else
+#define MAP_I2SIntRegister \
+ I2SIntRegister
+#endif
+#ifdef ROM_I2SIntUnregister
+#define MAP_I2SIntUnregister \
+ ROM_I2SIntUnregister
+#else
+#define MAP_I2SIntUnregister \
+ I2SIntUnregister
+#endif
+#ifdef ROM_I2STxActiveSlotSet
+#define MAP_I2STxActiveSlotSet \
+ ROM_I2STxActiveSlotSet
+#else
+#define MAP_I2STxActiveSlotSet \
+ I2STxActiveSlotSet
+#endif
+#ifdef ROM_I2SRxActiveSlotSet
+#define MAP_I2SRxActiveSlotSet \
+ ROM_I2SRxActiveSlotSet
+#else
+#define MAP_I2SRxActiveSlotSet \
+ I2SRxActiveSlotSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the GPIO API.
+//
+//*****************************************************************************
+#ifdef ROM_GPIODirModeSet
+#define MAP_GPIODirModeSet \
+ ROM_GPIODirModeSet
+#else
+#define MAP_GPIODirModeSet \
+ GPIODirModeSet
+#endif
+#ifdef ROM_GPIODirModeGet
+#define MAP_GPIODirModeGet \
+ ROM_GPIODirModeGet
+#else
+#define MAP_GPIODirModeGet \
+ GPIODirModeGet
+#endif
+#ifdef ROM_GPIOIntTypeSet
+#define MAP_GPIOIntTypeSet \
+ ROM_GPIOIntTypeSet
+#else
+#define MAP_GPIOIntTypeSet \
+ GPIOIntTypeSet
+#endif
+#ifdef ROM_GPIODMATriggerEnable
+#define MAP_GPIODMATriggerEnable \
+ ROM_GPIODMATriggerEnable
+#else
+#define MAP_GPIODMATriggerEnable \
+ GPIODMATriggerEnable
+#endif
+#ifdef ROM_GPIODMATriggerDisable
+#define MAP_GPIODMATriggerDisable \
+ ROM_GPIODMATriggerDisable
+#else
+#define MAP_GPIODMATriggerDisable \
+ GPIODMATriggerDisable
+#endif
+#ifdef ROM_GPIOIntTypeGet
+#define MAP_GPIOIntTypeGet \
+ ROM_GPIOIntTypeGet
+#else
+#define MAP_GPIOIntTypeGet \
+ GPIOIntTypeGet
+#endif
+#ifdef ROM_GPIOIntEnable
+#define MAP_GPIOIntEnable \
+ ROM_GPIOIntEnable
+#else
+#define MAP_GPIOIntEnable \
+ GPIOIntEnable
+#endif
+#ifdef ROM_GPIOIntDisable
+#define MAP_GPIOIntDisable \
+ ROM_GPIOIntDisable
+#else
+#define MAP_GPIOIntDisable \
+ GPIOIntDisable
+#endif
+#ifdef ROM_GPIOIntStatus
+#define MAP_GPIOIntStatus \
+ ROM_GPIOIntStatus
+#else
+#define MAP_GPIOIntStatus \
+ GPIOIntStatus
+#endif
+#ifdef ROM_GPIOIntClear
+#define MAP_GPIOIntClear \
+ ROM_GPIOIntClear
+#else
+#define MAP_GPIOIntClear \
+ GPIOIntClear
+#endif
+#ifdef ROM_GPIOIntRegister
+#define MAP_GPIOIntRegister \
+ ROM_GPIOIntRegister
+#else
+#define MAP_GPIOIntRegister \
+ GPIOIntRegister
+#endif
+#ifdef ROM_GPIOIntUnregister
+#define MAP_GPIOIntUnregister \
+ ROM_GPIOIntUnregister
+#else
+#define MAP_GPIOIntUnregister \
+ GPIOIntUnregister
+#endif
+#ifdef ROM_GPIOPinRead
+#define MAP_GPIOPinRead \
+ ROM_GPIOPinRead
+#else
+#define MAP_GPIOPinRead \
+ GPIOPinRead
+#endif
+#ifdef ROM_GPIOPinWrite
+#define MAP_GPIOPinWrite \
+ ROM_GPIOPinWrite
+#else
+#define MAP_GPIOPinWrite \
+ GPIOPinWrite
+#endif
+
+//*****************************************************************************
+//
+// Macros for the AES API.
+//
+//*****************************************************************************
+#ifdef ROM_AESConfigSet
+#define MAP_AESConfigSet \
+ ROM_AESConfigSet
+#else
+#define MAP_AESConfigSet \
+ AESConfigSet
+#endif
+#ifdef ROM_AESKey1Set
+#define MAP_AESKey1Set \
+ ROM_AESKey1Set
+#else
+#define MAP_AESKey1Set \
+ AESKey1Set
+#endif
+#ifdef ROM_AESKey2Set
+#define MAP_AESKey2Set \
+ ROM_AESKey2Set
+#else
+#define MAP_AESKey2Set \
+ AESKey2Set
+#endif
+#ifdef ROM_AESKey3Set
+#define MAP_AESKey3Set \
+ ROM_AESKey3Set
+#else
+#define MAP_AESKey3Set \
+ AESKey3Set
+#endif
+#ifdef ROM_AESIVSet
+#define MAP_AESIVSet \
+ ROM_AESIVSet
+#else
+#define MAP_AESIVSet \
+ AESIVSet
+#endif
+#ifdef ROM_AESTagRead
+#define MAP_AESTagRead \
+ ROM_AESTagRead
+#else
+#define MAP_AESTagRead \
+ AESTagRead
+#endif
+#ifdef ROM_AESDataLengthSet
+#define MAP_AESDataLengthSet \
+ ROM_AESDataLengthSet
+#else
+#define MAP_AESDataLengthSet \
+ AESDataLengthSet
+#endif
+#ifdef ROM_AESAuthDataLengthSet
+#define MAP_AESAuthDataLengthSet \
+ ROM_AESAuthDataLengthSet
+#else
+#define MAP_AESAuthDataLengthSet \
+ AESAuthDataLengthSet
+#endif
+#ifdef ROM_AESDataReadNonBlocking
+#define MAP_AESDataReadNonBlocking \
+ ROM_AESDataReadNonBlocking
+#else
+#define MAP_AESDataReadNonBlocking \
+ AESDataReadNonBlocking
+#endif
+#ifdef ROM_AESDataRead
+#define MAP_AESDataRead \
+ ROM_AESDataRead
+#else
+#define MAP_AESDataRead \
+ AESDataRead
+#endif
+#ifdef ROM_AESDataWriteNonBlocking
+#define MAP_AESDataWriteNonBlocking \
+ ROM_AESDataWriteNonBlocking
+#else
+#define MAP_AESDataWriteNonBlocking \
+ AESDataWriteNonBlocking
+#endif
+#ifdef ROM_AESDataWrite
+#define MAP_AESDataWrite \
+ ROM_AESDataWrite
+#else
+#define MAP_AESDataWrite \
+ AESDataWrite
+#endif
+#ifdef ROM_AESDataProcess
+#define MAP_AESDataProcess \
+ ROM_AESDataProcess
+#else
+#define MAP_AESDataProcess \
+ AESDataProcess
+#endif
+#ifdef ROM_AESDataMAC
+#define MAP_AESDataMAC \
+ ROM_AESDataMAC
+#else
+#define MAP_AESDataMAC \
+ AESDataMAC
+#endif
+#ifdef ROM_AESDataProcessAE
+#define MAP_AESDataProcessAE \
+ ROM_AESDataProcessAE
+#else
+#define MAP_AESDataProcessAE \
+ AESDataProcessAE
+#endif
+#ifdef ROM_AESIntStatus
+#define MAP_AESIntStatus \
+ ROM_AESIntStatus
+#else
+#define MAP_AESIntStatus \
+ AESIntStatus
+#endif
+#ifdef ROM_AESIntEnable
+#define MAP_AESIntEnable \
+ ROM_AESIntEnable
+#else
+#define MAP_AESIntEnable \
+ AESIntEnable
+#endif
+#ifdef ROM_AESIntDisable
+#define MAP_AESIntDisable \
+ ROM_AESIntDisable
+#else
+#define MAP_AESIntDisable \
+ AESIntDisable
+#endif
+#ifdef ROM_AESIntClear
+#define MAP_AESIntClear \
+ ROM_AESIntClear
+#else
+#define MAP_AESIntClear \
+ AESIntClear
+#endif
+#ifdef ROM_AESIntRegister
+#define MAP_AESIntRegister \
+ ROM_AESIntRegister
+#else
+#define MAP_AESIntRegister \
+ AESIntRegister
+#endif
+#ifdef ROM_AESIntUnregister
+#define MAP_AESIntUnregister \
+ ROM_AESIntUnregister
+#else
+#define MAP_AESIntUnregister \
+ AESIntUnregister
+#endif
+#ifdef ROM_AESDMAEnable
+#define MAP_AESDMAEnable \
+ ROM_AESDMAEnable
+#else
+#define MAP_AESDMAEnable \
+ AESDMAEnable
+#endif
+#ifdef ROM_AESDMADisable
+#define MAP_AESDMADisable \
+ ROM_AESDMADisable
+#else
+#define MAP_AESDMADisable \
+ AESDMADisable
+#endif
+#ifdef ROM_AESIVGet
+#define MAP_AESIVGet \
+ ROM_AESIVGet
+#else
+#define MAP_AESIVGet \
+ AESIVGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the DES API.
+//
+//*****************************************************************************
+#ifdef ROM_DESConfigSet
+#define MAP_DESConfigSet \
+ ROM_DESConfigSet
+#else
+#define MAP_DESConfigSet \
+ DESConfigSet
+#endif
+#ifdef ROM_DESDataRead
+#define MAP_DESDataRead \
+ ROM_DESDataRead
+#else
+#define MAP_DESDataRead \
+ DESDataRead
+#endif
+#ifdef ROM_DESDataReadNonBlocking
+#define MAP_DESDataReadNonBlocking \
+ ROM_DESDataReadNonBlocking
+#else
+#define MAP_DESDataReadNonBlocking \
+ DESDataReadNonBlocking
+#endif
+#ifdef ROM_DESDataProcess
+#define MAP_DESDataProcess \
+ ROM_DESDataProcess
+#else
+#define MAP_DESDataProcess \
+ DESDataProcess
+#endif
+#ifdef ROM_DESDataWrite
+#define MAP_DESDataWrite \
+ ROM_DESDataWrite
+#else
+#define MAP_DESDataWrite \
+ DESDataWrite
+#endif
+#ifdef ROM_DESDataWriteNonBlocking
+#define MAP_DESDataWriteNonBlocking \
+ ROM_DESDataWriteNonBlocking
+#else
+#define MAP_DESDataWriteNonBlocking \
+ DESDataWriteNonBlocking
+#endif
+#ifdef ROM_DESDMADisable
+#define MAP_DESDMADisable \
+ ROM_DESDMADisable
+#else
+#define MAP_DESDMADisable \
+ DESDMADisable
+#endif
+#ifdef ROM_DESDMAEnable
+#define MAP_DESDMAEnable \
+ ROM_DESDMAEnable
+#else
+#define MAP_DESDMAEnable \
+ DESDMAEnable
+#endif
+#ifdef ROM_DESIntClear
+#define MAP_DESIntClear \
+ ROM_DESIntClear
+#else
+#define MAP_DESIntClear \
+ DESIntClear
+#endif
+#ifdef ROM_DESIntDisable
+#define MAP_DESIntDisable \
+ ROM_DESIntDisable
+#else
+#define MAP_DESIntDisable \
+ DESIntDisable
+#endif
+#ifdef ROM_DESIntEnable
+#define MAP_DESIntEnable \
+ ROM_DESIntEnable
+#else
+#define MAP_DESIntEnable \
+ DESIntEnable
+#endif
+#ifdef ROM_DESIntRegister
+#define MAP_DESIntRegister \
+ ROM_DESIntRegister
+#else
+#define MAP_DESIntRegister \
+ DESIntRegister
+#endif
+#ifdef ROM_DESIntStatus
+#define MAP_DESIntStatus \
+ ROM_DESIntStatus
+#else
+#define MAP_DESIntStatus \
+ DESIntStatus
+#endif
+#ifdef ROM_DESIntUnregister
+#define MAP_DESIntUnregister \
+ ROM_DESIntUnregister
+#else
+#define MAP_DESIntUnregister \
+ DESIntUnregister
+#endif
+#ifdef ROM_DESIVSet
+#define MAP_DESIVSet \
+ ROM_DESIVSet
+#else
+#define MAP_DESIVSet \
+ DESIVSet
+#endif
+#ifdef ROM_DESKeySet
+#define MAP_DESKeySet \
+ ROM_DESKeySet
+#else
+#define MAP_DESKeySet \
+ DESKeySet
+#endif
+#ifdef ROM_DESDataLengthSet
+#define MAP_DESDataLengthSet \
+ ROM_DESDataLengthSet
+#else
+#define MAP_DESDataLengthSet \
+ DESDataLengthSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SHAMD5 API.
+//
+//*****************************************************************************
+#ifdef ROM_SHAMD5ConfigSet
+#define MAP_SHAMD5ConfigSet \
+ ROM_SHAMD5ConfigSet
+#else
+#define MAP_SHAMD5ConfigSet \
+ SHAMD5ConfigSet
+#endif
+#ifdef ROM_SHAMD5DataProcess
+#define MAP_SHAMD5DataProcess \
+ ROM_SHAMD5DataProcess
+#else
+#define MAP_SHAMD5DataProcess \
+ SHAMD5DataProcess
+#endif
+#ifdef ROM_SHAMD5DataWrite
+#define MAP_SHAMD5DataWrite \
+ ROM_SHAMD5DataWrite
+#else
+#define MAP_SHAMD5DataWrite \
+ SHAMD5DataWrite
+#endif
+#ifdef ROM_SHAMD5DataWriteNonBlocking
+#define MAP_SHAMD5DataWriteNonBlocking \
+ ROM_SHAMD5DataWriteNonBlocking
+#else
+#define MAP_SHAMD5DataWriteNonBlocking \
+ SHAMD5DataWriteNonBlocking
+#endif
+#ifdef ROM_SHAMD5DMADisable
+#define MAP_SHAMD5DMADisable \
+ ROM_SHAMD5DMADisable
+#else
+#define MAP_SHAMD5DMADisable \
+ SHAMD5DMADisable
+#endif
+#ifdef ROM_SHAMD5DMAEnable
+#define MAP_SHAMD5DMAEnable \
+ ROM_SHAMD5DMAEnable
+#else
+#define MAP_SHAMD5DMAEnable \
+ SHAMD5DMAEnable
+#endif
+#ifdef ROM_SHAMD5DataLengthSet
+#define MAP_SHAMD5DataLengthSet \
+ ROM_SHAMD5DataLengthSet
+#else
+#define MAP_SHAMD5DataLengthSet \
+ SHAMD5DataLengthSet
+#endif
+#ifdef ROM_SHAMD5HMACKeySet
+#define MAP_SHAMD5HMACKeySet \
+ ROM_SHAMD5HMACKeySet
+#else
+#define MAP_SHAMD5HMACKeySet \
+ SHAMD5HMACKeySet
+#endif
+#ifdef ROM_SHAMD5HMACPPKeyGenerate
+#define MAP_SHAMD5HMACPPKeyGenerate \
+ ROM_SHAMD5HMACPPKeyGenerate
+#else
+#define MAP_SHAMD5HMACPPKeyGenerate \
+ SHAMD5HMACPPKeyGenerate
+#endif
+#ifdef ROM_SHAMD5HMACPPKeySet
+#define MAP_SHAMD5HMACPPKeySet \
+ ROM_SHAMD5HMACPPKeySet
+#else
+#define MAP_SHAMD5HMACPPKeySet \
+ SHAMD5HMACPPKeySet
+#endif
+#ifdef ROM_SHAMD5HMACProcess
+#define MAP_SHAMD5HMACProcess \
+ ROM_SHAMD5HMACProcess
+#else
+#define MAP_SHAMD5HMACProcess \
+ SHAMD5HMACProcess
+#endif
+#ifdef ROM_SHAMD5IntClear
+#define MAP_SHAMD5IntClear \
+ ROM_SHAMD5IntClear
+#else
+#define MAP_SHAMD5IntClear \
+ SHAMD5IntClear
+#endif
+#ifdef ROM_SHAMD5IntDisable
+#define MAP_SHAMD5IntDisable \
+ ROM_SHAMD5IntDisable
+#else
+#define MAP_SHAMD5IntDisable \
+ SHAMD5IntDisable
+#endif
+#ifdef ROM_SHAMD5IntEnable
+#define MAP_SHAMD5IntEnable \
+ ROM_SHAMD5IntEnable
+#else
+#define MAP_SHAMD5IntEnable \
+ SHAMD5IntEnable
+#endif
+#ifdef ROM_SHAMD5IntRegister
+#define MAP_SHAMD5IntRegister \
+ ROM_SHAMD5IntRegister
+#else
+#define MAP_SHAMD5IntRegister \
+ SHAMD5IntRegister
+#endif
+#ifdef ROM_SHAMD5IntStatus
+#define MAP_SHAMD5IntStatus \
+ ROM_SHAMD5IntStatus
+#else
+#define MAP_SHAMD5IntStatus \
+ SHAMD5IntStatus
+#endif
+#ifdef ROM_SHAMD5IntUnregister
+#define MAP_SHAMD5IntUnregister \
+ ROM_SHAMD5IntUnregister
+#else
+#define MAP_SHAMD5IntUnregister \
+ SHAMD5IntUnregister
+#endif
+#ifdef ROM_SHAMD5ResultRead
+#define MAP_SHAMD5ResultRead \
+ ROM_SHAMD5ResultRead
+#else
+#define MAP_SHAMD5ResultRead \
+ SHAMD5ResultRead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CRC API.
+//
+//*****************************************************************************
+#ifdef ROM_CRCConfigSet
+#define MAP_CRCConfigSet \
+ ROM_CRCConfigSet
+#else
+#define MAP_CRCConfigSet \
+ CRCConfigSet
+#endif
+#ifdef ROM_CRCDataProcess
+#define MAP_CRCDataProcess \
+ ROM_CRCDataProcess
+#else
+#define MAP_CRCDataProcess \
+ CRCDataProcess
+#endif
+#ifdef ROM_CRCDataWrite
+#define MAP_CRCDataWrite \
+ ROM_CRCDataWrite
+#else
+#define MAP_CRCDataWrite \
+ CRCDataWrite
+#endif
+#ifdef ROM_CRCResultRead
+#define MAP_CRCResultRead \
+ ROM_CRCResultRead
+#else
+#define MAP_CRCResultRead \
+ CRCResultRead
+#endif
+#ifdef ROM_CRCSeedSet
+#define MAP_CRCSeedSet \
+ ROM_CRCSeedSet
+#else
+#define MAP_CRCSeedSet \
+ CRCSeedSet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the SDHOST API.
+//
+//*****************************************************************************
+#ifdef ROM_SDHostCmdReset
+#define MAP_SDHostCmdReset \
+ ROM_SDHostCmdReset
+#else
+#define MAP_SDHostCmdReset \
+ SDHostCmdReset
+#endif
+#ifdef ROM_SDHostInit
+#define MAP_SDHostInit \
+ ROM_SDHostInit
+#else
+#define MAP_SDHostInit \
+ SDHostInit
+#endif
+#ifdef ROM_SDHostCmdSend
+#define MAP_SDHostCmdSend \
+ ROM_SDHostCmdSend
+#else
+#define MAP_SDHostCmdSend \
+ SDHostCmdSend
+#endif
+#ifdef ROM_SDHostIntRegister
+#define MAP_SDHostIntRegister \
+ ROM_SDHostIntRegister
+#else
+#define MAP_SDHostIntRegister \
+ SDHostIntRegister
+#endif
+#ifdef ROM_SDHostIntUnregister
+#define MAP_SDHostIntUnregister \
+ ROM_SDHostIntUnregister
+#else
+#define MAP_SDHostIntUnregister \
+ SDHostIntUnregister
+#endif
+#ifdef ROM_SDHostIntEnable
+#define MAP_SDHostIntEnable \
+ ROM_SDHostIntEnable
+#else
+#define MAP_SDHostIntEnable \
+ SDHostIntEnable
+#endif
+#ifdef ROM_SDHostIntDisable
+#define MAP_SDHostIntDisable \
+ ROM_SDHostIntDisable
+#else
+#define MAP_SDHostIntDisable \
+ SDHostIntDisable
+#endif
+#ifdef ROM_SDHostIntStatus
+#define MAP_SDHostIntStatus \
+ ROM_SDHostIntStatus
+#else
+#define MAP_SDHostIntStatus \
+ SDHostIntStatus
+#endif
+#ifdef ROM_SDHostIntClear
+#define MAP_SDHostIntClear \
+ ROM_SDHostIntClear
+#else
+#define MAP_SDHostIntClear \
+ SDHostIntClear
+#endif
+#ifdef ROM_SDHostRespGet
+#define MAP_SDHostRespGet \
+ ROM_SDHostRespGet
+#else
+#define MAP_SDHostRespGet \
+ SDHostRespGet
+#endif
+#ifdef ROM_SDHostBlockSizeSet
+#define MAP_SDHostBlockSizeSet \
+ ROM_SDHostBlockSizeSet
+#else
+#define MAP_SDHostBlockSizeSet \
+ SDHostBlockSizeSet
+#endif
+#ifdef ROM_SDHostBlockCountSet
+#define MAP_SDHostBlockCountSet \
+ ROM_SDHostBlockCountSet
+#else
+#define MAP_SDHostBlockCountSet \
+ SDHostBlockCountSet
+#endif
+#ifdef ROM_SDHostDataNonBlockingWrite
+#define MAP_SDHostDataNonBlockingWrite \
+ ROM_SDHostDataNonBlockingWrite
+#else
+#define MAP_SDHostDataNonBlockingWrite \
+ SDHostDataNonBlockingWrite
+#endif
+#ifdef ROM_SDHostDataNonBlockingRead
+#define MAP_SDHostDataNonBlockingRead \
+ ROM_SDHostDataNonBlockingRead
+#else
+#define MAP_SDHostDataNonBlockingRead \
+ SDHostDataNonBlockingRead
+#endif
+#ifdef ROM_SDHostDataWrite
+#define MAP_SDHostDataWrite \
+ ROM_SDHostDataWrite
+#else
+#define MAP_SDHostDataWrite \
+ SDHostDataWrite
+#endif
+#ifdef ROM_SDHostDataRead
+#define MAP_SDHostDataRead \
+ ROM_SDHostDataRead
+#else
+#define MAP_SDHostDataRead \
+ SDHostDataRead
+#endif
+#ifdef ROM_SDHostSetExpClk
+#define MAP_SDHostSetExpClk \
+ ROM_SDHostSetExpClk
+#else
+#define MAP_SDHostSetExpClk \
+ SDHostSetExpClk
+#endif
+#ifdef ROM_SDHostCardErrorMaskSet
+#define MAP_SDHostCardErrorMaskSet \
+ ROM_SDHostCardErrorMaskSet
+#else
+#define MAP_SDHostCardErrorMaskSet \
+ SDHostCardErrorMaskSet
+#endif
+#ifdef ROM_SDHostCardErrorMaskGet
+#define MAP_SDHostCardErrorMaskGet \
+ ROM_SDHostCardErrorMaskGet
+#else
+#define MAP_SDHostCardErrorMaskGet \
+ SDHostCardErrorMaskGet
+#endif
+
+//*****************************************************************************
+//
+// Macros for the PRCM API.
+//
+//*****************************************************************************
+#ifdef ROM_PRCMMCUReset
+#define MAP_PRCMMCUReset \
+ ROM_PRCMMCUReset
+#else
+#define MAP_PRCMMCUReset \
+ PRCMMCUReset
+#endif
+#ifdef ROM_PRCMSysResetCauseGet
+#define MAP_PRCMSysResetCauseGet \
+ ROM_PRCMSysResetCauseGet
+#else
+#define MAP_PRCMSysResetCauseGet \
+ PRCMSysResetCauseGet
+#endif
+#ifdef ROM_PRCMPeripheralClkEnable
+#define MAP_PRCMPeripheralClkEnable \
+ ROM_PRCMPeripheralClkEnable
+#else
+#define MAP_PRCMPeripheralClkEnable \
+ PRCMPeripheralClkEnable
+#endif
+#ifdef ROM_PRCMPeripheralClkDisable
+#define MAP_PRCMPeripheralClkDisable \
+ ROM_PRCMPeripheralClkDisable
+#else
+#define MAP_PRCMPeripheralClkDisable \
+ PRCMPeripheralClkDisable
+#endif
+#ifdef ROM_PRCMPeripheralReset
+#define MAP_PRCMPeripheralReset \
+ ROM_PRCMPeripheralReset
+#else
+#define MAP_PRCMPeripheralReset \
+ PRCMPeripheralReset
+#endif
+#ifdef ROM_PRCMPeripheralStatusGet
+#define MAP_PRCMPeripheralStatusGet \
+ ROM_PRCMPeripheralStatusGet
+#else
+#define MAP_PRCMPeripheralStatusGet \
+ PRCMPeripheralStatusGet
+#endif
+#ifdef ROM_PRCMI2SClockFreqSet
+#define MAP_PRCMI2SClockFreqSet \
+ ROM_PRCMI2SClockFreqSet
+#else
+#define MAP_PRCMI2SClockFreqSet \
+ PRCMI2SClockFreqSet
+#endif
+#ifdef ROM_PRCMPeripheralClockGet
+#define MAP_PRCMPeripheralClockGet \
+ ROM_PRCMPeripheralClockGet
+#else
+#define MAP_PRCMPeripheralClockGet \
+ PRCMPeripheralClockGet
+#endif
+#ifdef ROM_PRCMSleepEnter
+#define MAP_PRCMSleepEnter \
+ ROM_PRCMSleepEnter
+#else
+#define MAP_PRCMSleepEnter \
+ PRCMSleepEnter
+#endif
+#ifdef ROM_PRCMSRAMRetentionEnable
+#define MAP_PRCMSRAMRetentionEnable \
+ ROM_PRCMSRAMRetentionEnable
+#else
+#define MAP_PRCMSRAMRetentionEnable \
+ PRCMSRAMRetentionEnable
+#endif
+#ifdef ROM_PRCMSRAMRetentionDisable
+#define MAP_PRCMSRAMRetentionDisable \
+ ROM_PRCMSRAMRetentionDisable
+#else
+#define MAP_PRCMSRAMRetentionDisable \
+ PRCMSRAMRetentionDisable
+#endif
+#ifdef ROM_PRCMLPDSEnter
+#define MAP_PRCMLPDSEnter \
+ ROM_PRCMLPDSEnter
+#else
+#define MAP_PRCMLPDSEnter \
+ PRCMLPDSEnter
+#endif
+#ifdef ROM_PRCMLPDSIntervalSet
+#define MAP_PRCMLPDSIntervalSet \
+ ROM_PRCMLPDSIntervalSet
+#else
+#define MAP_PRCMLPDSIntervalSet \
+ PRCMLPDSIntervalSet
+#endif
+#ifdef ROM_PRCMLPDSWakeupSourceEnable
+#define MAP_PRCMLPDSWakeupSourceEnable \
+ ROM_PRCMLPDSWakeupSourceEnable
+#else
+#define MAP_PRCMLPDSWakeupSourceEnable \
+ PRCMLPDSWakeupSourceEnable
+#endif
+#ifdef ROM_PRCMLPDSWakeupCauseGet
+#define MAP_PRCMLPDSWakeupCauseGet \
+ ROM_PRCMLPDSWakeupCauseGet
+#else
+#define MAP_PRCMLPDSWakeupCauseGet \
+ PRCMLPDSWakeupCauseGet
+#endif
+#ifdef ROM_PRCMLPDSWakeUpGPIOSelect
+#define MAP_PRCMLPDSWakeUpGPIOSelect \
+ ROM_PRCMLPDSWakeUpGPIOSelect
+#else
+#define MAP_PRCMLPDSWakeUpGPIOSelect \
+ PRCMLPDSWakeUpGPIOSelect
+#endif
+#ifdef ROM_PRCMLPDSWakeupSourceDisable
+#define MAP_PRCMLPDSWakeupSourceDisable \
+ ROM_PRCMLPDSWakeupSourceDisable
+#else
+#define MAP_PRCMLPDSWakeupSourceDisable \
+ PRCMLPDSWakeupSourceDisable
+#endif
+#ifdef ROM_PRCMHibernateEnter
+#define MAP_PRCMHibernateEnter \
+ ROM_PRCMHibernateEnter
+#else
+#define MAP_PRCMHibernateEnter \
+ PRCMHibernateEnter
+#endif
+#ifdef ROM_PRCMHibernateWakeupSourceEnable
+#define MAP_PRCMHibernateWakeupSourceEnable \
+ ROM_PRCMHibernateWakeupSourceEnable
+#else
+#define MAP_PRCMHibernateWakeupSourceEnable \
+ PRCMHibernateWakeupSourceEnable
+#endif
+#ifdef ROM_PRCMHibernateWakeupCauseGet
+#define MAP_PRCMHibernateWakeupCauseGet \
+ ROM_PRCMHibernateWakeupCauseGet
+#else
+#define MAP_PRCMHibernateWakeupCauseGet \
+ PRCMHibernateWakeupCauseGet
+#endif
+#ifdef ROM_PRCMHibernateWakeUpGPIOSelect
+#define MAP_PRCMHibernateWakeUpGPIOSelect \
+ ROM_PRCMHibernateWakeUpGPIOSelect
+#else
+#define MAP_PRCMHibernateWakeUpGPIOSelect \
+ PRCMHibernateWakeUpGPIOSelect
+#endif
+#ifdef ROM_PRCMHibernateWakeupSourceDisable
+#define MAP_PRCMHibernateWakeupSourceDisable \
+ ROM_PRCMHibernateWakeupSourceDisable
+#else
+#define MAP_PRCMHibernateWakeupSourceDisable \
+ PRCMHibernateWakeupSourceDisable
+#endif
+#ifdef ROM_PRCMHibernateIntervalSet
+#define MAP_PRCMHibernateIntervalSet \
+ ROM_PRCMHibernateIntervalSet
+#else
+#define MAP_PRCMHibernateIntervalSet \
+ PRCMHibernateIntervalSet
+#endif
+#ifdef ROM_PRCMSlowClkCtrGet
+#define MAP_PRCMSlowClkCtrGet \
+ ROM_PRCMSlowClkCtrGet
+#else
+#define MAP_PRCMSlowClkCtrGet \
+ PRCMSlowClkCtrGet
+#endif
+#ifdef ROM_PRCMSlowClkCtrMatchSet
+#define MAP_PRCMSlowClkCtrMatchSet \
+ ROM_PRCMSlowClkCtrMatchSet
+#else
+#define MAP_PRCMSlowClkCtrMatchSet \
+ PRCMSlowClkCtrMatchSet
+#endif
+#ifdef ROM_PRCMSlowClkCtrMatchGet
+#define MAP_PRCMSlowClkCtrMatchGet \
+ ROM_PRCMSlowClkCtrMatchGet
+#else
+#define MAP_PRCMSlowClkCtrMatchGet \
+ PRCMSlowClkCtrMatchGet
+#endif
+#ifdef ROM_PRCMOCRRegisterWrite
+#define MAP_PRCMOCRRegisterWrite \
+ ROM_PRCMOCRRegisterWrite
+#else
+#define MAP_PRCMOCRRegisterWrite \
+ PRCMOCRRegisterWrite
+#endif
+#ifdef ROM_PRCMOCRRegisterRead
+#define MAP_PRCMOCRRegisterRead \
+ ROM_PRCMOCRRegisterRead
+#else
+#define MAP_PRCMOCRRegisterRead \
+ PRCMOCRRegisterRead
+#endif
+#ifdef ROM_PRCMIntRegister
+#define MAP_PRCMIntRegister \
+ ROM_PRCMIntRegister
+#else
+#define MAP_PRCMIntRegister \
+ PRCMIntRegister
+#endif
+#ifdef ROM_PRCMIntUnregister
+#define MAP_PRCMIntUnregister \
+ ROM_PRCMIntUnregister
+#else
+#define MAP_PRCMIntUnregister \
+ PRCMIntUnregister
+#endif
+#ifdef ROM_PRCMIntEnable
+#define MAP_PRCMIntEnable \
+ ROM_PRCMIntEnable
+#else
+#define MAP_PRCMIntEnable \
+ PRCMIntEnable
+#endif
+#ifdef ROM_PRCMIntDisable
+#define MAP_PRCMIntDisable \
+ ROM_PRCMIntDisable
+#else
+#define MAP_PRCMIntDisable \
+ PRCMIntDisable
+#endif
+#ifdef ROM_PRCMIntStatus
+#define MAP_PRCMIntStatus \
+ ROM_PRCMIntStatus
+#else
+#define MAP_PRCMIntStatus \
+ PRCMIntStatus
+#endif
+#ifdef ROM_PRCMRTCInUseSet
+#define MAP_PRCMRTCInUseSet \
+ ROM_PRCMRTCInUseSet
+#else
+#define MAP_PRCMRTCInUseSet \
+ PRCMRTCInUseSet
+#endif
+#ifdef ROM_PRCMRTCInUseGet
+#define MAP_PRCMRTCInUseGet \
+ ROM_PRCMRTCInUseGet
+#else
+#define MAP_PRCMRTCInUseGet \
+ PRCMRTCInUseGet
+#endif
+#ifdef ROM_PRCMRTCSet
+#define MAP_PRCMRTCSet \
+ ROM_PRCMRTCSet
+#else
+#define MAP_PRCMRTCSet \
+ PRCMRTCSet
+#endif
+#ifdef ROM_PRCMRTCGet
+#define MAP_PRCMRTCGet \
+ ROM_PRCMRTCGet
+#else
+#define MAP_PRCMRTCGet \
+ PRCMRTCGet
+#endif
+#ifdef ROM_PRCMRTCMatchSet
+#define MAP_PRCMRTCMatchSet \
+ ROM_PRCMRTCMatchSet
+#else
+#define MAP_PRCMRTCMatchSet \
+ PRCMRTCMatchSet
+#endif
+#ifdef ROM_PRCMRTCMatchGet
+#define MAP_PRCMRTCMatchGet \
+ ROM_PRCMRTCMatchGet
+#else
+#define MAP_PRCMRTCMatchGet \
+ PRCMRTCMatchGet
+#endif
+#ifdef ROM_PRCMLPDSRestoreInfoSet
+#define MAP_PRCMLPDSRestoreInfoSet \
+ ROM_PRCMLPDSRestoreInfoSet
+#else
+#define MAP_PRCMLPDSRestoreInfoSet \
+ PRCMLPDSRestoreInfoSet
+#endif
+#ifdef ROM_PRCMSlowClkCtrFastGet
+#define MAP_PRCMSlowClkCtrFastGet \
+ ROM_PRCMSlowClkCtrFastGet
+#else
+#define MAP_PRCMSlowClkCtrFastGet \
+ PRCMSlowClkCtrFastGet
+#endif
+#ifdef ROM_PRCMCC3200MCUInit
+#define MAP_PRCMCC3200MCUInit \
+ ROM_PRCMCC3200MCUInit
+#else
+#define MAP_PRCMCC3200MCUInit \
+ PRCMCC3200MCUInit
+#endif
+#ifdef ROM_PRCMHIBRegRead
+#define MAP_PRCMHIBRegRead \
+ ROM_PRCMHIBRegRead
+#else
+#define MAP_PRCMHIBRegRead \
+ PRCMHIBRegRead
+#endif
+#ifdef ROM_PRCMHIBRegWrite
+#define MAP_PRCMHIBRegWrite \
+ ROM_PRCMHIBRegWrite
+#else
+#define MAP_PRCMHIBRegWrite \
+ PRCMHIBRegWrite
+#endif
+#ifdef ROM_PRCMCameraFreqSet
+#define MAP_PRCMCameraFreqSet \
+ ROM_PRCMCameraFreqSet
+#else
+#define MAP_PRCMCameraFreqSet \
+ PRCMCameraFreqSet
+#endif
+#ifdef ROM_PRCMIORetentionEnable
+#define MAP_PRCMIORetentionEnable \
+ ROM_PRCMIORetentionEnable
+#else
+#define MAP_PRCMIORetentionEnable \
+ PRCMIORetentionEnable
+#endif
+#ifdef ROM_PRCMIORetentionDisable
+#define MAP_PRCMIORetentionDisable \
+ ROM_PRCMIORetentionDisable
+#else
+#define MAP_PRCMIORetentionDisable \
+ PRCMIORetentionDisable
+#endif
+#ifdef ROM_PRCMDeviceTypeGet
+#define MAP_PRCMDeviceTypeGet \
+ ROM_PRCMDeviceTypeGet
+#else
+#define MAP_PRCMDeviceTypeGet \
+ PRCMDeviceTypeGet
+#endif
+#ifdef ROM_PRCMLPDSEnterKeepDebugIf
+#define MAP_PRCMLPDSEnterKeepDebugIf \
+ ROM_PRCMLPDSEnterKeepDebugIf
+#else
+#define MAP_PRCMLPDSEnterKeepDebugIf \
+ PRCMLPDSEnterKeepDebugIf
+#endif
+#ifdef ROM_PRCMHibernateCycleTrigger
+#define MAP_PRCMHibernateCycleTrigger \
+ ROM_PRCMHibernateCycleTrigger
+#else
+#define MAP_PRCMHibernateCycleTrigger \
+ PRCMHibernateCycleTrigger
+#endif
+
+//*****************************************************************************
+//
+// Macros for the HWSPINLOCK API.
+//
+//*****************************************************************************
+#ifdef ROM_HwSpinLockAcquire
+#define MAP_HwSpinLockAcquire \
+ ROM_HwSpinLockAcquire
+#else
+#define MAP_HwSpinLockAcquire \
+ HwSpinLockAcquire
+#endif
+#ifdef ROM_HwSpinLockTryAcquire
+#define MAP_HwSpinLockTryAcquire \
+ ROM_HwSpinLockTryAcquire
+#else
+#define MAP_HwSpinLockTryAcquire \
+ HwSpinLockTryAcquire
+#endif
+#ifdef ROM_HwSpinLockRelease
+#define MAP_HwSpinLockRelease \
+ ROM_HwSpinLockRelease
+#else
+#define MAP_HwSpinLockRelease \
+ HwSpinLockRelease
+#endif
+#ifdef ROM_HwSpinLockTest
+#define MAP_HwSpinLockTest \
+ ROM_HwSpinLockTest
+#else
+#define MAP_HwSpinLockTest \
+ HwSpinLockTest
+#endif
+
+//*****************************************************************************
+//
+// Macros for the ADC API.
+//
+//*****************************************************************************
+#ifdef ROM_ADCEnable
+#define MAP_ADCEnable \
+ ROM_ADCEnable
+#else
+#define MAP_ADCEnable \
+ ADCEnable
+#endif
+#ifdef ROM_ADCDisable
+#define MAP_ADCDisable \
+ ROM_ADCDisable
+#else
+#define MAP_ADCDisable \
+ ADCDisable
+#endif
+#ifdef ROM_ADCChannelEnable
+#define MAP_ADCChannelEnable \
+ ROM_ADCChannelEnable
+#else
+#define MAP_ADCChannelEnable \
+ ADCChannelEnable
+#endif
+#ifdef ROM_ADCChannelDisable
+#define MAP_ADCChannelDisable \
+ ROM_ADCChannelDisable
+#else
+#define MAP_ADCChannelDisable \
+ ADCChannelDisable
+#endif
+#ifdef ROM_ADCIntRegister
+#define MAP_ADCIntRegister \
+ ROM_ADCIntRegister
+#else
+#define MAP_ADCIntRegister \
+ ADCIntRegister
+#endif
+#ifdef ROM_ADCIntUnregister
+#define MAP_ADCIntUnregister \
+ ROM_ADCIntUnregister
+#else
+#define MAP_ADCIntUnregister \
+ ADCIntUnregister
+#endif
+#ifdef ROM_ADCIntEnable
+#define MAP_ADCIntEnable \
+ ROM_ADCIntEnable
+#else
+#define MAP_ADCIntEnable \
+ ADCIntEnable
+#endif
+#ifdef ROM_ADCIntDisable
+#define MAP_ADCIntDisable \
+ ROM_ADCIntDisable
+#else
+#define MAP_ADCIntDisable \
+ ADCIntDisable
+#endif
+#ifdef ROM_ADCIntStatus
+#define MAP_ADCIntStatus \
+ ROM_ADCIntStatus
+#else
+#define MAP_ADCIntStatus \
+ ADCIntStatus
+#endif
+#ifdef ROM_ADCIntClear
+#define MAP_ADCIntClear \
+ ROM_ADCIntClear
+#else
+#define MAP_ADCIntClear \
+ ADCIntClear
+#endif
+#ifdef ROM_ADCDMAEnable
+#define MAP_ADCDMAEnable \
+ ROM_ADCDMAEnable
+#else
+#define MAP_ADCDMAEnable \
+ ADCDMAEnable
+#endif
+#ifdef ROM_ADCDMADisable
+#define MAP_ADCDMADisable \
+ ROM_ADCDMADisable
+#else
+#define MAP_ADCDMADisable \
+ ADCDMADisable
+#endif
+#ifdef ROM_ADCTimerConfig
+#define MAP_ADCTimerConfig \
+ ROM_ADCTimerConfig
+#else
+#define MAP_ADCTimerConfig \
+ ADCTimerConfig
+#endif
+#ifdef ROM_ADCTimerEnable
+#define MAP_ADCTimerEnable \
+ ROM_ADCTimerEnable
+#else
+#define MAP_ADCTimerEnable \
+ ADCTimerEnable
+#endif
+#ifdef ROM_ADCTimerDisable
+#define MAP_ADCTimerDisable \
+ ROM_ADCTimerDisable
+#else
+#define MAP_ADCTimerDisable \
+ ADCTimerDisable
+#endif
+#ifdef ROM_ADCTimerReset
+#define MAP_ADCTimerReset \
+ ROM_ADCTimerReset
+#else
+#define MAP_ADCTimerReset \
+ ADCTimerReset
+#endif
+#ifdef ROM_ADCTimerValueGet
+#define MAP_ADCTimerValueGet \
+ ROM_ADCTimerValueGet
+#else
+#define MAP_ADCTimerValueGet \
+ ADCTimerValueGet
+#endif
+#ifdef ROM_ADCFIFOLvlGet
+#define MAP_ADCFIFOLvlGet \
+ ROM_ADCFIFOLvlGet
+#else
+#define MAP_ADCFIFOLvlGet \
+ ADCFIFOLvlGet
+#endif
+#ifdef ROM_ADCFIFORead
+#define MAP_ADCFIFORead \
+ ROM_ADCFIFORead
+#else
+#define MAP_ADCFIFORead \
+ ADCFIFORead
+#endif
+
+//*****************************************************************************
+//
+// Macros for the CPU API.
+//
+//*****************************************************************************
+#ifdef ROM_CPUcpsid
+#define MAP_CPUcpsid \
+ ROM_CPUcpsid
+#else
+#define MAP_CPUcpsid \
+ CPUcpsid
+#endif
+#ifdef ROM_CPUcpsie
+#define MAP_CPUcpsie \
+ ROM_CPUcpsie
+#else
+#define MAP_CPUcpsie \
+ CPUcpsie
+#endif
+#ifdef ROM_CPUprimask
+#define MAP_CPUprimask \
+ ROM_CPUprimask
+#else
+#define MAP_CPUprimask \
+ CPUprimask
+#endif
+#ifdef ROM_CPUwfi
+#define MAP_CPUwfi \
+ ROM_CPUwfi
+#else
+#define MAP_CPUwfi \
+ CPUwfi
+#endif
+#ifdef ROM_CPUbasepriGet
+#define MAP_CPUbasepriGet \
+ ROM_CPUbasepriGet
+#else
+#define MAP_CPUbasepriGet \
+ CPUbasepriGet
+#endif
+#ifdef ROM_CPUbasepriSet
+#define MAP_CPUbasepriSet \
+ ROM_CPUbasepriSet
+#else
+#define MAP_CPUbasepriSet \
+ CPUbasepriSet
+#endif
+
+#endif // __ROM_MAP_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/rom_patch.h b/ext/hal/ti/cc3220sdk/driverlib/rom_patch.h
new file mode 100644
index 0000000..f733ec4
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/rom_patch.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// rom_patch.h - Macros to facilitate patching driverlib API's in the ROM.
+//
+//
+
+//*****************************************************************************
+//
+// List of API's in the ROM that need to be patched.
+// For e.g. to patch ROM_UARTCharPut add the line #undef ROM_UARTCharPut
+//*****************************************************************************
+
+#ifndef __ROM_PATCH_H__
+#define __ROM_PATCH_H__
+
+#if defined(TARGET_IS_CC3200) || defined(USE_CC3200_ROM_DRV_API)
+#undef ROM_ADCIntClear
+#undef ROM_IntEnable
+#undef ROM_IntDisable
+#undef ROM_IntPendSet
+#undef ROM_SDHostCardErrorMaskSet
+#undef ROM_SDHostCardErrorMaskGet
+#undef ROM_TimerConfigure
+#undef ROM_TimerDMAEventSet
+#undef ROM_TimerDMAEventGet
+#undef ROM_SDHostDataNonBlockingWrite
+#undef ROM_SDHostDataWrite
+#undef ROM_SDHostDataRead
+#undef ROM_SDHostDataNonBlockingRead
+#undef ROM_PRCMSysResetCauseGet
+#undef ROM_PRCMPeripheralClkEnable
+#undef ROM_PRCMLPDSWakeUpGPIOSelect
+#undef ROM_PRCMHibernateWakeupSourceEnable
+#undef ROM_PRCMHibernateWakeupSourceDisable
+#undef ROM_PRCMHibernateWakeupCauseGet
+#undef ROM_PRCMHibernateIntervalSet
+#undef ROM_PRCMHibernateWakeUpGPIOSelect
+#undef ROM_PRCMHibernateEnter
+#undef ROM_PRCMSlowClkCtrGet
+#undef ROM_PRCMSlowClkCtrMatchSet
+#undef ROM_PRCMSlowClkCtrMatchGet
+#undef ROM_PRCMOCRRegisterWrite
+#undef ROM_PRCMOCRRegisterRead
+#undef ROM_PRCMIntEnable
+#undef ROM_PRCMIntDisable
+#undef ROM_PRCMRTCInUseSet
+#undef ROM_PRCMRTCInUseGet
+#undef ROM_PRCMRTCSet
+#undef ROM_PRCMRTCGet
+#undef ROM_PRCMRTCMatchSet
+#undef ROM_PRCMRTCMatchGet
+#undef ROM_PRCMPeripheralClkDisable
+#undef ROM_PRCMPeripheralReset
+#undef ROM_PRCMPeripheralStatusGet
+#undef ROM_SPIConfigSetExpClk
+#undef ROM_AESDataProcess
+#undef ROM_DESDataProcess
+#undef ROM_I2SEnable
+#undef ROM_I2SConfigSetExpClk
+#undef ROM_PinConfigSet
+#undef ROM_PRCMLPDSEnter
+#undef ROM_PRCMCC3200MCUInit
+#undef ROM_SDHostIntStatus
+#undef ROM_SDHostBlockCountSet
+#undef ROM_UARTModemControlSet
+#undef ROM_UARTModemControlClear
+#undef ROM_CameraXClkSet
+#undef ROM_PRCMMCUReset
+#undef ROM_PRCMPeripheralClkEnable
+#undef ROM_SPIDmaDisable
+#endif
+
+#if defined(USE_CC3220_ROM_DRV_API)
+#undef ROM_PRCMDeviceTypeGet
+#undef ROM_SDHostDataNonBlockingRead
+#undef ROM_PRCMIORetentionEnable
+#undef ROM_PRCMIORetentionDisable
+#undef ROM_PRCMCC3200MCUInit
+#endif
+
+#endif // __ROM_PATCH_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/uart.h b/ext/hal/ti/cc3220sdk/driverlib/uart.h
new file mode 100644
index 0000000..5d1f150
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/uart.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// uart.h
+//
+// Defines and Macros for the UART.
+//
+//*****************************************************************************
+
+#ifndef __UART_H__
+#define __UART_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear
+// as the ulIntFlags parameter, and returned from UARTIntStatus.
+//
+//*****************************************************************************
+#define UART_INT_DMATX 0x20000 // DMA Tx Done interrupt Mask
+#define UART_INT_DMARX 0x10000 // DMA Rx Done interrupt Mask
+#define UART_INT_EOT 0x800 // End of transfer interrupt Mask
+#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask
+#define UART_INT_BE 0x200 // Break Error Interrupt Mask
+#define UART_INT_PE 0x100 // Parity Error Interrupt Mask
+#define UART_INT_FE 0x080 // Framing Error Interrupt Mask
+#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask
+#define UART_INT_TX 0x020 // Transmit Interrupt Mask
+#define UART_INT_RX 0x010 // Receive Interrupt Mask
+#define UART_INT_CTS 0x002 // CTS Modem Interrupt Mask
+
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter
+// and returned by UARTConfigGetExpClk in the pulConfig parameter.
+// Additionally, the UART_CONFIG_PAR_* subset can be passed to
+// UARTParityModeSet as the ulParity parameter, and are returned by
+// UARTParityModeGet.
+//
+//*****************************************************************************
+#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length
+#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data
+#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data
+#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data
+#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data
+#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits
+#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit
+#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits
+#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity
+#define UART_CONFIG_PAR_NONE 0x00000000 // No parity
+#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity
+#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity
+#define UART_CONFIG_PAR_ONE 0x00000082 // Parity bit is one
+#define UART_CONFIG_PAR_ZERO 0x00000086 // Parity bit is zero
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulTxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full
+#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full
+#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full
+#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full
+#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and
+// returned by UARTFIFOLevelGet in the pulRxLevel.
+//
+//*****************************************************************************
+#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full
+#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full
+#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full
+#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full
+#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTDMAEnable() and UARTDMADisable().
+//
+//*****************************************************************************
+#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error
+#define UART_DMA_TX 0x00000002 // Enable DMA for transmit
+#define UART_DMA_RX 0x00000001 // Enable DMA for receive
+
+//*****************************************************************************
+//
+// Values returned from UARTRxErrorGet().
+//
+//*****************************************************************************
+#define UART_RXERROR_OVERRUN 0x00000008
+#define UART_RXERROR_BREAK 0x00000004
+#define UART_RXERROR_PARITY 0x00000002
+#define UART_RXERROR_FRAMING 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTModemControlSet()and UARTModemControlClear()
+// or returned from UARTModemControlGet().
+//
+//*****************************************************************************
+#define UART_OUTPUT_RTS 0x00000800
+
+//*****************************************************************************
+//
+// Values that can be returned from UARTModemStatusGet().
+//
+//*****************************************************************************
+#define UART_INPUT_CTS 0x00000001
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTFlowControl() or returned from
+// UARTFlowControlGet().
+//
+//*****************************************************************************
+#define UART_FLOWCONTROL_TX 0x00008000
+#define UART_FLOWCONTROL_RX 0x00004000
+#define UART_FLOWCONTROL_NONE 0x00000000
+
+//*****************************************************************************
+//
+// Values that can be passed to UARTTxIntModeSet() or returned from
+// UARTTxIntModeGet().
+//
+//*****************************************************************************
+#define UART_TXINT_MODE_FIFO 0x00000000
+#define UART_TXINT_MODE_EOT 0x00000010
+
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity);
+extern unsigned long UARTParityModeGet(unsigned long ulBase);
+extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel,
+ unsigned long ulRxLevel);
+extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel,
+ unsigned long *pulRxLevel);
+extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long ulBaud, unsigned long ulConfig);
+extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk,
+ unsigned long *pulBaud,
+ unsigned long *pulConfig);
+extern void UARTEnable(unsigned long ulBase);
+extern void UARTDisable(unsigned long ulBase);
+extern void UARTFIFOEnable(unsigned long ulBase);
+extern void UARTFIFODisable(unsigned long ulBase);
+extern tBoolean UARTCharsAvail(unsigned long ulBase);
+extern tBoolean UARTSpaceAvail(unsigned long ulBase);
+extern long UARTCharGetNonBlocking(unsigned long ulBase);
+extern long UARTCharGet(unsigned long ulBase);
+extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase,
+ unsigned char ucData);
+extern void UARTCharPut(unsigned long ulBase, unsigned char ucData);
+extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState);
+extern tBoolean UARTBusy(unsigned long ulBase);
+extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void));
+extern void UARTIntUnregister(unsigned long ulBase);
+extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags);
+extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked);
+extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags);
+extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags);
+extern unsigned long UARTRxErrorGet(unsigned long ulBase);
+extern void UARTRxErrorClear(unsigned long ulBase);
+extern void UARTModemControlSet(unsigned long ulBase,
+ unsigned long ulControl);
+extern void UARTModemControlClear(unsigned long ulBase,
+ unsigned long ulControl);
+extern unsigned long UARTModemControlGet(unsigned long ulBase);
+extern unsigned long UARTModemStatusGet(unsigned long ulBase);
+extern void UARTFlowControlSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTFlowControlGet(unsigned long ulBase);
+extern void UARTTxIntModeSet(unsigned long ulBase, unsigned long ulMode);
+extern unsigned long UARTTxIntModeGet(unsigned long ulBase);
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __UART_H__
diff --git a/ext/hal/ti/cc3220sdk/driverlib/utils.c b/ext/hal/ti/cc3220sdk/driverlib/utils.c
new file mode 100644
index 0000000..f97cea6
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/utils.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// utils.c
+//
+// Utility APIs
+//
+//*****************************************************************************
+
+//*****************************************************************************
+//
+//! \addtogroup Utils_api
+//! @{
+//
+//*****************************************************************************
+#include "utils.h"
+
+
+//*****************************************************************************
+//
+//! Provides a small delay.
+//!
+//! \param ulCount is the number of delay loop iterations to perform.
+//!
+//! This function provides a means of generating a constant length delay. It
+//! is written in assembly to keep the delay consistent across tool chains,
+//! avoiding the need to tune the delay based on the tool chain in use.
+//!
+//! The loop takes 3 cycles/loop.
+//!
+//! \return None.
+//
+//*****************************************************************************
+#if defined(ewarm) || defined(DOXYGEN)
+void
+UtilsDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne.n UtilsDelay\n");
+}
+#endif
+
+#if defined(gcc)
+void __attribute__((naked))
+UtilsDelay(unsigned long ulCount)
+{
+ __asm(" subs r0, #1\n"
+ " bne UtilsDelay\n"
+ " bx lr");
+}
+#endif
+
+//
+// For CCS implement this function in pure assembly. This prevents the TI
+// compiler from doing funny things with the optimizer.
+//
+#if defined(ccs)
+ __asm(" .sect \".text:UtilsDelay\"\n"
+ " .clink\n"
+ " .thumbfunc UtilsDelay\n"
+ " .thumb\n"
+ " .global UtilsDelay\n"
+ "UtilsDelay:\n"
+ " subs r0, #1\n"
+ " bne.n UtilsDelay\n"
+ " bx lr\n");
+#endif
+
+//*****************************************************************************
+//
+// Close the Doxygen group.
+//! @}
+//
+//*****************************************************************************
diff --git a/ext/hal/ti/cc3220sdk/driverlib/utils.h b/ext/hal/ti/cc3220sdk/driverlib/utils.h
new file mode 100644
index 0000000..fe7e39b
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/driverlib/utils.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//*****************************************************************************
+//
+// utils.h
+//
+// Prototypes and macros for utility APIs
+//
+//*****************************************************************************
+
+#ifndef __UTILS_H__
+#define __UTILS_H__
+
+//*****************************************************************************
+//
+// If building with a C++ compiler, make all of the definitions in this header
+// have a C binding.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+//*****************************************************************************
+//
+// API Function prototypes
+//
+//*****************************************************************************
+extern void UtilsDelay(unsigned long ulCount);
+
+
+//*****************************************************************************
+//
+// Mark the end of the C bindings section for C++ compilers.
+//
+//*****************************************************************************
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UTILS_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_apps_rcm.h b/ext/hal/ti/cc3220sdk/inc/hw_apps_rcm.h
new file mode 100644
index 0000000..32c666f
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_apps_rcm.h
@@ -0,0 +1,1504 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_APPS_RCM_H__
+#define __HW_APPS_RCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the APPS_RCM register offsets.
+//
+//*****************************************************************************
+#define APPS_RCM_O_CAMERA_CLK_GEN \
+ 0x00000000
+
+#define APPS_RCM_O_CAMERA_CLK_GATING \
+ 0x00000004
+
+#define APPS_RCM_O_CAMERA_SOFT_RESET \
+ 0x00000008
+
+#define APPS_RCM_O_MCASP_CLK_GATING \
+ 0x00000014
+
+#define APPS_RCM_O_MCASP_SOFT_RESET \
+ 0x00000018
+
+#define APPS_RCM_O_MMCHS_CLK_GEN \
+ 0x00000020
+
+#define APPS_RCM_O_MMCHS_CLK_GATING \
+ 0x00000024
+
+#define APPS_RCM_O_MMCHS_SOFT_RESET \
+ 0x00000028
+
+#define APPS_RCM_O_MCSPI_A1_CLK_GEN \
+ 0x0000002C
+
+#define APPS_RCM_O_MCSPI_A1_CLK_GATING \
+ 0x00000030
+
+#define APPS_RCM_O_MCSPI_A1_SOFT_RESET \
+ 0x00000034
+
+#define APPS_RCM_O_MCSPI_A2_CLK_GEN \
+ 0x00000038
+
+#define APPS_RCM_O_MCSPI_A2_CLK_GATING \
+ 0x00000040
+
+#define APPS_RCM_O_MCSPI_A2_SOFT_RESET \
+ 0x00000044
+
+#define APPS_RCM_O_UDMA_A_CLK_GATING \
+ 0x00000048
+
+#define APPS_RCM_O_UDMA_A_SOFT_RESET \
+ 0x0000004C
+
+#define APPS_RCM_O_GPIO_A_CLK_GATING \
+ 0x00000050
+
+#define APPS_RCM_O_GPIO_A_SOFT_RESET \
+ 0x00000054
+
+#define APPS_RCM_O_GPIO_B_CLK_GATING \
+ 0x00000058
+
+#define APPS_RCM_O_GPIO_B_SOFT_RESET \
+ 0x0000005C
+
+#define APPS_RCM_O_GPIO_C_CLK_GATING \
+ 0x00000060
+
+#define APPS_RCM_O_GPIO_C_SOFT_RESET \
+ 0x00000064
+
+#define APPS_RCM_O_GPIO_D_CLK_GATING \
+ 0x00000068
+
+#define APPS_RCM_O_GPIO_D_SOFT_RESET \
+ 0x0000006C
+
+#define APPS_RCM_O_GPIO_E_CLK_GATING \
+ 0x00000070
+
+#define APPS_RCM_O_GPIO_E_SOFT_RESET \
+ 0x00000074
+
+#define APPS_RCM_O_WDOG_A_CLK_GATING \
+ 0x00000078
+
+#define APPS_RCM_O_WDOG_A_SOFT_RESET \
+ 0x0000007C
+
+#define APPS_RCM_O_UART_A0_CLK_GATING \
+ 0x00000080
+
+#define APPS_RCM_O_UART_A0_SOFT_RESET \
+ 0x00000084
+
+#define APPS_RCM_O_UART_A1_CLK_GATING \
+ 0x00000088
+
+#define APPS_RCM_O_UART_A1_SOFT_RESET \
+ 0x0000008C
+
+#define APPS_RCM_O_GPT_A0_CLK_GATING \
+ 0x00000090
+
+#define APPS_RCM_O_GPT_A0_SOFT_RESET \
+ 0x00000094
+
+#define APPS_RCM_O_GPT_A1_CLK_GATING \
+ 0x00000098
+
+#define APPS_RCM_O_GPT_A1_SOFT_RESET \
+ 0x0000009C
+
+#define APPS_RCM_O_GPT_A2_CLK_GATING \
+ 0x000000A0
+
+#define APPS_RCM_O_GPT_A2_SOFT_RESET \
+ 0x000000A4
+
+#define APPS_RCM_O_GPT_A3_CLK_GATING \
+ 0x000000A8
+
+#define APPS_RCM_O_GPT_A3_SOFT_RESET \
+ 0x000000AC
+
+#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 \
+ 0x000000B0
+
+#define APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 \
+ 0x000000B4
+
+#define APPS_RCM_O_CRYPTO_CLK_GATING \
+ 0x000000B8
+
+#define APPS_RCM_O_CRYPTO_SOFT_RESET \
+ 0x000000BC
+
+#define APPS_RCM_O_MCSPI_S0_CLK_GATING \
+ 0x000000C8
+
+#define APPS_RCM_O_MCSPI_S0_SOFT_RESET \
+ 0x000000CC
+
+#define APPS_RCM_O_MCSPI_S0_CLKDIV_CFG \
+ 0x000000D0
+
+#define APPS_RCM_O_I2C_CLK_GATING \
+ 0x000000D8
+
+#define APPS_RCM_O_I2C_SOFT_RESET \
+ 0x000000DC
+
+#define APPS_RCM_O_APPS_LPDS_REQ \
+ 0x000000E4
+
+#define APPS_RCM_O_APPS_TURBO_REQ \
+ 0x000000EC
+
+#define APPS_RCM_O_APPS_DSLP_WAKE_CONFIG \
+ 0x00000108
+
+#define APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG \
+ 0x0000010C
+
+#define APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE \
+ 0x00000110
+
+#define APPS_RCM_O_APPS_SLP_WAKETIMER_CFG \
+ 0x00000114
+
+#define APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST \
+ 0x00000118
+
+#define APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS \
+ 0x00000120
+
+#define APPS_RCM_O_APPS_RCM_INTERRUPT_ENABLE \
+ 0x00000124
+
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of Camera func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_CAMERA_CLK_GEN_NU1_M \
+ 0x000000F8
+
+#define APPS_RCM_CAMERA_CLK_GEN_NU1_S 3
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of Camera func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_CAMERA_CLK_GEN_CAMERA_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU1_S 17
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable camera clk during
+ // deep-sleep mode
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU2_S 9
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable camera clk during
+ // sleep mode ; 0- Disable camera
+ // clk during sleep mode
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_CAMERA_CLK_GATING_NU3_S 1
+#define APPS_RCM_CAMERA_CLK_GATING_CAMERA_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable camera clk during run
+ // mode ; 0- Disable camera clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CAMERA_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_ENABLED_STATUS \
+ 0x00000002 // 1 - Camera clocks/resets are
+ // enabled ; 0 - Camera
+ // clocks/resets are disabled
+
+#define APPS_RCM_CAMERA_SOFT_RESET_CAMERA_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for Camera-core
+ // ; 0 - De-assert reset for
+ // Camera-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCASP_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCASP clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCASP_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCASP_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCASP clk during sleep
+ // mode ; 0- Disable MCASP clk
+ // during sleep mode
+
+#define APPS_RCM_MCASP_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCASP_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCASP_CLK_GATING_MCASP_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCASP clk during run
+ // mode ; 0- Disable MCASP clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_SOFT_RESET_MCASP_ENABLED_STATUS \
+ 0x00000002 // 1 - MCASP Clocks/resets are
+ // enabled ; 0 - MCASP Clocks/resets
+ // are disabled
+
+#define APPS_RCM_MCASP_SOFT_RESET_MCASP_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for MCASP-core
+ // ; 0 - De-assert reset for
+ // MCASP-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MMCHS func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_MMCHS_CLK_GEN_NU1_M \
+ 0x000000F8
+
+#define APPS_RCM_MMCHS_CLK_GEN_NU1_S 3
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MMCHS func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MMCHS_CLK_GEN_MMCHS_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU1_S 17
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MMCHS clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU2_S 9
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MMCHS clk during sleep
+ // mode ; 0- Disable MMCHS clk
+ // during sleep mode
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MMCHS_CLK_GATING_NU3_S 1
+#define APPS_RCM_MMCHS_CLK_GATING_MMCHS_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MMCHS clk during run
+ // mode ; 0- Disable MMCHS clk
+ // during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MMCHS_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_ENABLED_STATUS \
+ 0x00000002 // 1 - MMCHS Clocks/resets are
+ // enabled ; 0 - MMCHS Clocks/resets
+ // are disabled
+
+#define APPS_RCM_MMCHS_SOFT_RESET_MMCHS_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for MMCHS-core
+ // ; 0 - De-assert reset for
+ // MMCHS-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud clk
+ // for MCSPI_A1 ; 1 - PLL divclk is
+ // used as baud clk for MCSPI_A1.
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU1_S 11
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A1 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_NU2_S 3
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A1 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A1_CLK_GEN_MCSPI_A1_PLLCLKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCSPI_A1 clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCSPI_A1 clk during
+ // sleep mode ; 0- Disable MCSPI_A1
+ // clk during sleep mode
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_A1_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCSPI_A1_CLK_GATING_MCSPI_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCSPI_A1 clk during
+ // run mode ; 0- Disable MCSPI_A1
+ // clk during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_A1 Clocks/Resets are
+ // enabled ; 0 - MCSPI_A1
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_MCSPI_A1_SOFT_RESET_MCSPI_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for
+ // MCSPI_A1-core ; 0 - De-assert
+ // reset for MCSPI_A1-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_CLK_GEN register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud-clk
+ // for MCSPI_A2 ; 1 - PLL divclk is
+ // used as baud-clk for MCSPI_A2
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU1_S 11
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A2 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_NU2_S 3
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_A2 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_A2_CLK_GEN_MCSPI_A2_PLLCKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_M \
+ 0x00FE0000
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU1_S 17
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable MCSPI_A2 clk during
+ // deep-sleep mode
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU2_S 9
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_SLP_CLK_ENABLE \
+ 0x00000100 // 1- Enable MCSPI_A2 clk during
+ // sleep mode ; 0- Disable MCSPI_A2
+ // clk during sleep mode
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_A2_CLK_GATING_NU3_S 1
+#define APPS_RCM_MCSPI_A2_CLK_GATING_MCSPI_A2_RUN_CLK_ENABLE \
+ 0x00000001 // 1- Enable MCSPI_A2 clk during
+ // run mode ; 0- Disable MCSPI_A2
+ // clk during run mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_A2_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_A2 Clocks/Resets are
+ // enabled ; 0 - MCSPI_A2
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_MCSPI_A2_SOFT_RESET_MCSPI_A2_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for
+ // MCSPI_A2-core ; 0 - De-assert
+ // reset for MCSPI_A2-core
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UDMA_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UDMA_A clk during
+ // deep-sleep mode 0 - Disable
+ // UDMA_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UDMA_A clk during
+ // sleep mode 0 - Disable UDMA_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UDMA_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_UDMA_A_CLK_GATING_UDMA_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UDMA_A clk during run
+ // mode 0 - Disable UDMA_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UDMA_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_ENABLED_STATUS \
+ 0x00000002 // 1 - UDMA_A Clocks/Resets are
+ // enabled ; 0 - UDMA_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UDMA_A_SOFT_RESET_UDMA_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for DMA_A ; 0 -
+ // De-assert reset for DMA_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_A clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_A clk during
+ // sleep mode 0 - Disable GPIO_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_A_CLK_GATING_GPIO_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_A clk during run
+ // mode 0 - Disable GPIO_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_A Clocks/Resets are
+ // enabled ; 0 - GPIO_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_A_SOFT_RESET_GPIO_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_A ; 0
+ // - De-assert reset for GPIO_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_B_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_B clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_B clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_B clk during
+ // sleep mode 0 - Disable GPIO_B clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_B_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_B_CLK_GATING_GPIO_B_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_B clk during run
+ // mode 0 - Disable GPIO_B clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_B_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_B Clocks/Resets are
+ // enabled ; 0 - GPIO_B
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_B_SOFT_RESET_GPIO_B_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_B ; 0
+ // - De-assert reset for GPIO_B
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_C_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_C clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_C clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_C clk during
+ // sleep mode 0 - Disable GPIO_C clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_C_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_C_CLK_GATING_GPIO_C_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_C clk during run
+ // mode 0 - Disable GPIO_C clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_C_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_C Clocks/Resets are
+ // enabled ; 0 - GPIO_C
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_C_SOFT_RESET_GPIO_C_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_C ; 0
+ // - De-assert reset for GPIO_C
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_D_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_D clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_D clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_D clk during
+ // sleep mode 0 - Disable GPIO_D clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_D_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_D_CLK_GATING_GPIO_D_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_D clk during run
+ // mode 0 - Disable GPIO_D clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_D_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_D Clocks/Resets are
+ // enabled ; 0 - GPIO_D
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_D_SOFT_RESET_GPIO_D_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_D ; 0
+ // - De-assert reset for GPIO_D
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_E_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable GPIO_E clk during
+ // deep-sleep mode 0 - Disable
+ // GPIO_E clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable GPIO_E clk during
+ // sleep mode 0 - Disable GPIO_E clk
+ // during sleep mode ;
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPIO_E_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPIO_E_CLK_GATING_GPIO_E_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable GPIO_E clk during run
+ // mode 0 - Disable GPIO_E clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPIO_E_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_ENABLED_STATUS \
+ 0x00000002 // 1 - GPIO_E Clocks/Resets are
+ // enabled ; 0 - GPIO_E
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_GPIO_E_SOFT_RESET_GPIO_E_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for GPIO_E ; 0
+ // - De-assert reset for GPIO_E
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_WDOG_A_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_M \
+ 0x03000000 // "00" - Sysclk ; "01" - REF_CLK
+ // (38.4 MHz) ; "10/11" - Slow_clk
+
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_BAUD_CLK_SEL_S 24
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable WDOG_A clk during
+ // deep-sleep mode 0 - Disable
+ // WDOG_A clk during deep-sleep mode
+ // ;
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU1_S 9
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable WDOG_A clk during
+ // sleep mode 0 - Disable WDOG_A clk
+ // during sleep mode ;
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_WDOG_A_CLK_GATING_NU2_S 1
+#define APPS_RCM_WDOG_A_CLK_GATING_WDOG_A_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable WDOG_A clk during run
+ // mode 0 - Disable WDOG_A clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_WDOG_A_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_ENABLED_STATUS \
+ 0x00000002 // 1 - WDOG_A Clocks/Resets are
+ // enabled ; 0 - WDOG_A
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_WDOG_A_SOFT_RESET_WDOG_A_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for WDOG_A ; 0
+ // - De-assert reset for WDOG_A
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UART_A0 clk during
+ // deep-sleep mode 0 - Disable
+ // UART_A0 clk during deep-sleep
+ // mode ;
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU1_S 9
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UART_A0 clk during
+ // sleep mode 0 - Disable UART_A0
+ // clk during sleep mode ;
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UART_A0_CLK_GATING_NU2_S 1
+#define APPS_RCM_UART_A0_CLK_GATING_UART_A0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UART_A0 clk during
+ // run mode 0 - Disable UART_A0 clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_ENABLED_STATUS \
+ 0x00000002 // 1 - UART_A0 Clocks/Resets are
+ // enabled ; 0 - UART_A0
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UART_A0_SOFT_RESET_UART_A0_SOFT_RESET \
+ 0x00000001 // 1 - Assert reset for UART_A0 ; 0
+ // - De-assert reset for UART_A0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable UART_A1 clk during
+ // deep-sleep mode 0 - Disable
+ // UART_A1 clk during deep-sleep
+ // mode ;
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU1_S 9
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable UART_A1 clk during
+ // sleep mode 0 - Disable UART_A1
+ // clk during sleep mode ;
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_UART_A1_CLK_GATING_NU2_S 1
+#define APPS_RCM_UART_A1_CLK_GATING_UART_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable UART_A1 clk during
+ // run mode 0 - Disable UART_A1 clk
+ // during run mode ;
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_UART_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - UART_A1 Clocks/Resets are
+ // enabled ; 0 - UART_A1
+ // Clocks/Resets are disabled
+
+#define APPS_RCM_UART_A1_SOFT_RESET_UART_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // UART_A1 ; 0 - De-assert the soft
+ // reset for UART_A1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A0 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A0 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A0 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A0 clock during sleep
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A0_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A0_CLK_GATING_GPT_A0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A0 clock
+ // during run ; 0 - Disable the
+ // GPT_A0 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A0 clocks/resets are
+ // enabled ; 0 - GPT_A0
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A0_SOFT_RESET_GPT_A0_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A0 ; 0 - De-assert the soft
+ // reset for GPT_A0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A1_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A1 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A1 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A1 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A1 clock during sleep
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A1_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A1_CLK_GATING_GPT_A1_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A1 clock
+ // during run ; 0 - Disable the
+ // GPT_A1 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A1_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A1 clocks/resets are
+ // enabled ; 0 - GPT_A1
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A1_SOFT_RESET_GPT_A1_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A1 ; 0 - De-assert the soft
+ // reset for GPT_A1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A2_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A2 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A2 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A2 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A2 clock during sleep
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A2_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A2_CLK_GATING_GPT_A2_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A2 clock
+ // during run ; 0 - Disable the
+ // GPT_A2 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A2_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A2 clocks/resets are
+ // enabled ; 0 - GPT_A2
+ // clocks/resets are disabled
+
+#define APPS_RCM_GPT_A2_SOFT_RESET_GPT_A2_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A2 ; 0 - De-assert the soft
+ // reset for GPT_A2
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A3_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the GPT_A3 clock
+ // during deep-sleep ; 0 - Disable
+ // the GPT_A3 clock during
+ // deep-sleep
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU1_S 9
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the GPT_A3 clock
+ // during sleep ; 0 - Disable the
+ // GPT_A3 clock during sleep
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_GPT_A3_CLK_GATING_NU2_S 1
+#define APPS_RCM_GPT_A3_CLK_GATING_GPT_A3_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the GPT_A3 clock
+ // during run ; 0 - Disable the
+ // GPT_A3 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_GPT_A3_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_ENABLED_STATUS \
+ 0x00000002 // 1 - GPT_A3 Clocks/resets are
+ // enabled ; 0 - GPT_A3
+ // Clocks/resets are disabled
+
+#define APPS_RCM_GPT_A3_SOFT_RESET_GPT_A3_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // GPT_A3 ; 0 - De-assert the soft
+ // reset for GPT_A3
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG0 register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_M \
+ 0x03FF0000
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_DIVISOR_S 16
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_M \
+ 0x0000FFFF
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG0_MCASP_FRAC_DIV_FRACTION_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCASP_FRAC_CLK_CONFIG1 register.
+//
+//******************************************************************************
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_SOFT_RESET \
+ 0x00010000 // 1 - Assert the reset for MCASP
+ // Frac-clk div; 0 - Donot assert
+ // the reset for MCASP frac clk-div
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_M \
+ 0x000003FF
+
+#define APPS_RCM_MCASP_FRAC_CLK_CONFIG1_MCASP_FRAC_DIV_PERIOD_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CRYPTO_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable the Crypto clock
+ // during deep-sleep
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU1_S 9
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the Crypto clock
+ // during sleep ; 0 - Disable the
+ // Crypto clock during sleep
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_CRYPTO_CLK_GATING_NU2_S 1
+#define APPS_RCM_CRYPTO_CLK_GATING_CRYPTO_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the Crypto clock
+ // during run ; 0 - Disable the
+ // Crypto clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_CRYPTO_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_ENABLED_STATUS \
+ 0x00000002 // 1 - Crypto clocks/resets are
+ // enabled ; 0 - Crypto
+ // clocks/resets are disabled
+
+#define APPS_RCM_CRYPTO_SOFT_RESET_CRYPTO_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // Crypto ; 0 - De-assert the soft
+ // reset for Crypto
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_DSLP_CLK_ENABLE \
+ 0x00010000 // 0 - Disable the MCSPI_S0 clock
+ // during deep-sleep
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU1_S 9
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the MCSPI_S0 clock
+ // during sleep ; 0 - Disable the
+ // MCSPI_S0 clock during sleep
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_MCSPI_S0_CLK_GATING_NU2_S 1
+#define APPS_RCM_MCSPI_S0_CLK_GATING_MCSPI_S0_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the MCSPI_S0 clock
+ // during run ; 0 - Disable the
+ // MCSPI_S0 clock during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_ENABLED_STATUS \
+ 0x00000002 // 1 - MCSPI_S0 Clocks/Resets are
+ // enabled ; 0 - MCSPI_S0
+ // Clocks/resets are disabled
+
+#define APPS_RCM_MCSPI_S0_SOFT_RESET_MCSPI_S0_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // MCSPI_S0 ; 0 - De-assert the soft
+ // reset for MCSPI_S0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_MCSPI_S0_CLKDIV_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_BAUD_CLK_SEL \
+ 0x00010000 // 0 - XTAL clk is used as baud-clk
+ // for MCSPI_S0 ; 1 - PLL divclk is
+ // used as buad-clk for MCSPI_S0
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_M \
+ 0x0000F800
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU1_S 11
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_M \
+ 0x00000700 // Configuration of OFF-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_S0 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_OFF_TIME_S 8
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_M \
+ 0x000000F8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_NU2_S 3
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_M \
+ 0x00000007 // Configuration of ON-TIME for
+ // dividing PLL clk (240 MHz) in
+ // generation of MCSPI_S0 func-clk :
+ // "000" - 1 "001" - 2 "010" - 3
+ // "011" - 4 "100" - 5 "101" - 6
+ // "110" - 7 "111" - 8
+
+#define APPS_RCM_MCSPI_S0_CLKDIV_CFG_MCSPI_S0_PLLCLKDIV_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_I2C_CLK_GATING register.
+//
+//******************************************************************************
+#define APPS_RCM_I2C_CLK_GATING_I2C_DSLP_CLK_ENABLE \
+ 0x00010000 // 1 - Enable the I2C Clock during
+ // deep-sleep 0 - Disable the I2C
+ // clock during deep-sleep
+
+#define APPS_RCM_I2C_CLK_GATING_NU1_M \
+ 0x0000FE00
+
+#define APPS_RCM_I2C_CLK_GATING_NU1_S 9
+#define APPS_RCM_I2C_CLK_GATING_I2C_SLP_CLK_ENABLE \
+ 0x00000100 // 1 - Enable the I2C clock during
+ // sleep ; 0 - Disable the I2C clock
+ // during sleep
+
+#define APPS_RCM_I2C_CLK_GATING_NU2_M \
+ 0x000000FE
+
+#define APPS_RCM_I2C_CLK_GATING_NU2_S 1
+#define APPS_RCM_I2C_CLK_GATING_I2C_RUN_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the I2C clock during
+ // run ; 0 - Disable the I2C clock
+ // during run
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_I2C_SOFT_RESET register.
+//
+//******************************************************************************
+#define APPS_RCM_I2C_SOFT_RESET_I2C_ENABLED_STATUS \
+ 0x00000002 // 1 - I2C Clocks/Resets are
+ // enabled ; 0 - I2C clocks/resets
+ // are disabled
+
+#define APPS_RCM_I2C_SOFT_RESET_I2C_SOFT_RESET \
+ 0x00000001 // 1 - Assert the soft reset for
+ // Shared-I2C ; 0 - De-assert the
+ // soft reset for Shared-I2C
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_LPDS_REQ register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_LPDS_REQ_APPS_LPDS_REQ \
+ 0x00000001 // 1 - Request for LPDS
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_TURBO_REQ register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_TURBO_REQ_APPS_TURBO_REQ \
+ 0x00000001 // 1 - Request for TURBO
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_DSLP_WAKE_CONFIG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_FROM_NWP_ENABLE \
+ 0x00000002 // 1 - Enable the NWP to wake APPS
+ // from deep-sleep ; 0 - Disable NWP
+ // to wake APPS from deep-sleep
+
+#define APPS_RCM_APPS_DSLP_WAKE_CONFIG_DSLP_WAKE_TIMER_ENABLE \
+ 0x00000001 // 1 - Enable deep-sleep wake timer
+ // in APPS RCM for deep-sleep; 0 -
+ // Disable deep-sleep wake timer in
+ // APPS RCM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_DSLP_WAKE_TIMER_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_M \
+ 0xFFFF0000 // Configuration (in slow_clks)
+ // which says when to request for
+ // OPP during deep-sleep exit
+
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_OPP_CFG_S 16
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_M \
+ 0x0000FFFF // Configuration (in slow_clks)
+ // which says when to request for
+ // WAKE during deep-sleep exit
+
+#define APPS_RCM_APPS_DSLP_WAKE_TIMER_CFG_DSLP_WAKE_TIMER_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_RCM_SLP_WAKE_ENABLE register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_FROM_NWP_ENABLE \
+ 0x00000002 // 1- Enable the sleep wakeup due
+ // to NWP request. 0- Disable the
+ // sleep wakeup due to NWP request
+
+#define APPS_RCM_APPS_RCM_SLP_WAKE_ENABLE_SLP_WAKE_TIMER_ENABLE \
+ 0x00000001 // 1- Enable the sleep wakeup due
+ // to sleep-timer; 0-Disable the
+ // sleep wakeup due to sleep-timer
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_SLP_WAKETIMER_CFG register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_M \
+ 0xFFFFFFFF // Configuration (number of
+ // sysclks-80MHz) for the Sleep
+ // wakeup timer
+
+#define APPS_RCM_APPS_SLP_WAKETIMER_CFG_SLP_WAKE_TIMER_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_TO_NWP_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_TO_NWP_WAKE_REQUEST_APPS_TO_NWP_WAKEUP_REQUEST \
+ 0x00000001 // When 1 => APPS generated a wake
+ // request to NWP (When NWP is in
+ // any of its low-power modes :
+ // SLP/DSLP/LPDS)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// APPS_RCM_O_APPS_RCM_INTERRUPT_STATUS register.
+//
+//******************************************************************************
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_timer_wake \
+ 0x00000008 // 1 - Indicates that deep-sleep
+ // timer expiry had caused the
+ // wakeup from deep-sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_timer_wake \
+ 0x00000004 // 1 - Indicates that sleep timer
+ // expiry had caused the wakeup from
+ // sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_deep_sleep_wake_from_nwp \
+ 0x00000002 // 1 - Indicates that NWP had
+ // caused the wakeup from deep-sleep
+
+#define APPS_RCM_APPS_RCM_INTERRUPT_STATUS_apps_sleep_wake_from_nwp \
+ 0x00000001 // 1 - Indicates that NWP had
+ // caused the wakeup from Sleep
+
+
+
+
+#endif // __HW_APPS_RCM_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_common_reg.h b/ext/hal/ti/cc3220sdk/inc/hw_common_reg.h
new file mode 100644
index 0000000..48bebc8
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_common_reg.h
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_COMMON_REG_H__
+#define __HW_COMMON_REG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the COMMON_REG register offsets.
+//
+//*****************************************************************************
+#define COMMON_REG_O_I2C_Properties_Register \
+ 0x00000000
+
+#define COMMON_REG_O_SPI_Properties_Register \
+ 0x00000004
+
+#define COMMON_REG_O_APPS_sh_resource_Interrupt_enable \
+ 0x0000000C
+
+#define COMMON_REG_O_APPS_sh_resource_Interrupt_status \
+ 0x00000010
+
+#define COMMON_REG_O_NWP_sh_resource_Interrupt_enable \
+ 0x00000014
+
+#define COMMON_REG_O_NWP_sh_resource_Interrupt_status \
+ 0x00000018
+
+#define COMMON_REG_O_Flash_ctrl_reg \
+ 0x0000001C
+
+#define COMMON_REG_O_Bus_matrix_M0_segment_access_config \
+ 0x00000024
+
+#define COMMON_REG_O_Bus_matrix_M1_segment_access_config \
+ 0x00000028
+
+#define COMMON_REG_O_Bus_matrix_M2_segment_access_config \
+ 0x0000002C
+
+#define COMMON_REG_O_Bus_matrix_M3_segment_access_config \
+ 0x00000030
+
+#define COMMON_REG_O_Bus_matrix_M4_segment_access_config \
+ 0x00000034
+
+#define COMMON_REG_O_Bus_matrix_M5_segment_access_config \
+ 0x00000038
+
+#define COMMON_REG_O_GPIO_properties_register \
+ 0x0000003C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE1 \
+ 0x00000040
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE2 \
+ 0x00000044
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE3 \
+ 0x00000048
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE4 \
+ 0x0000004C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE5 \
+ 0x00000050
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE6 \
+ 0x00000054
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE7 \
+ 0x00000058
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE8 \
+ 0x0000005C
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE9 \
+ 0x00000060
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE10 \
+ 0x00000064
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE11 \
+ 0x00000068
+
+#define COMMON_REG_O_APPS_NW_SEMAPHORE12 \
+ 0x0000006C
+
+#define COMMON_REG_O_APPS_SEMAPPHORE_PEND \
+ 0x00000070
+
+#define COMMON_REG_O_NW_SEMAPPHORE_PEND \
+ 0x00000074
+
+#define COMMON_REG_O_SEMAPHORE_STATUS \
+ 0x00000078
+
+#define COMMON_REG_O_IDMEM_TIM_Update \
+ 0x0000007C
+
+#define COMMON_REG_O_FPGA_ROM_WR_EN \
+ 0x00000080
+
+#define COMMON_REG_O_NW_INT_MASK \
+ 0x00000084
+
+#define COMMON_REG_O_NW_INT_MASK_SET \
+ 0x00000088
+
+#define COMMON_REG_O_NW_INT_MASK_CLR \
+ 0x0000008C
+
+#define COMMON_REG_O_NW_INT_STS_CLR \
+ 0x00000090
+
+#define COMMON_REG_O_NW_INT_ACK 0x00000094
+#define COMMON_REG_O_NW_INT_TRIG \
+ 0x00000098
+
+#define COMMON_REG_O_NW_INT_STS_MASKED \
+ 0x0000009C
+
+#define COMMON_REG_O_NW_INT_STS_RAW \
+ 0x000000A0
+
+#define COMMON_REG_O_APPS_INT_MASK \
+ 0x000000A4
+
+#define COMMON_REG_O_APPS_INT_MASK_SET \
+ 0x000000A8
+
+#define COMMON_REG_O_APPS_INT_MASK_CLR \
+ 0x000000AC
+
+#define COMMON_REG_O_APPS_INT_STS_CLR \
+ 0x000000B0
+
+#define COMMON_REG_O_APPS_INT_ACK \
+ 0x000000B4
+
+#define COMMON_REG_O_APPS_INT_TRIG \
+ 0x000000B8
+
+#define COMMON_REG_O_APPS_INT_STS_MASKED \
+ 0x000000BC
+
+#define COMMON_REG_O_APPS_INT_STS_RAW \
+ 0x000000C0
+
+#define COMMON_REG_O_IDMEM_TIM_Updated \
+ 0x000000C4
+
+#define COMMON_REG_O_APPS_GPIO_TRIG_EN \
+ 0x000000C8
+
+#define COMMON_REG_O_EMU_DEBUG_REG \
+ 0x000000CC
+
+#define COMMON_REG_O_SEMAPHORE_STATUS2 \
+ 0x000000D0
+
+#define COMMON_REG_O_SEMAPHORE_PREV_OWNER1 \
+ 0x000000D4
+
+#define COMMON_REG_O_SEMAPHORE_PREV_OWNER2 \
+ 0x000000D8
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_I2C_Properties_Register register.
+//
+//******************************************************************************
+#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_I2C_Properties_Register_I2C_Properties_Register_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SPI_Properties_Register register.
+//
+//******************************************************************************
+#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_SPI_Properties_Register_SPI_Properties_Register_S 0
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_sh_resource_Interrupt_enable register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_M \
+ 0x0000000F // Interrupt enable APPS bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_APPS_sh_resource_Interrupt_enable_APPS_sh_resource_Interrupt_enable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_sh_resource_Interrupt_status register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_M \
+ 0x0000000F // Interrupt enable APPS bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_APPS_sh_resource_Interrupt_status_APPS_sh_resource_Interrupt_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NWP_sh_resource_Interrupt_enable register.
+//
+//******************************************************************************
+#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_M \
+ 0x0000000F // Interrupt enable NWP bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_NWP_sh_resource_Interrupt_enable_NWP_sh_resource_Interrupt_enable_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NWP_sh_resource_Interrupt_status register.
+//
+//******************************************************************************
+#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_M \
+ 0x0000000F // Interrupt enable NWP bit 0 ->
+ // when '1' enable I2C interrupt bit
+ // 1 -> when '1' enable SPI
+ // interrupt bit 3 ->
+ // when '1' enable GPIO interrupt
+
+#define COMMON_REG_NWP_sh_resource_Interrupt_status_NWP_sh_resource_Interrupt_status_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Flash_ctrl_reg register.
+//
+//******************************************************************************
+#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_M \
+ 0x00000003 // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_Flash_ctrl_reg_Flash_ctrl_reg_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M0_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_M \
+ 0x0003FFFF // Master 0 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M0_segment_access_config_Bus_matrix_M0_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M1_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_M \
+ 0x0003FFFF // Master 1 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M1_segment_access_config_Bus_matrix_M1_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M2_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_M \
+ 0x0003FFFF // Master 2 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M2_segment_access_config_Bus_matrix_M2_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M3_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_M \
+ 0x0003FFFF // Master 3 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M3_segment_access_config_Bus_matrix_M3_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M4_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_M \
+ 0x0003FFFF // Master 4 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M4_segment_access_config_Bus_matrix_M4_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_Bus_matrix_M5_segment_access_config register.
+//
+//******************************************************************************
+#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_M \
+ 0x0003FFFF // Master 5 control word matrix to
+ // each segment. Tieoff. Bit value 1
+ // indicates segment is accesable.
+
+#define COMMON_REG_Bus_matrix_M5_segment_access_config_Bus_matrix_M5_segment_access_config_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_GPIO_properties_register register.
+//
+//******************************************************************************
+#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_M \
+ 0x000003FF // Shared GPIO configuration
+ // register. Bit [1:0] to configure
+ // GPIO0 Bit [3:2] to configure
+ // GPIO1 Bit [5:4] to configure
+ // GPIO2 Bit [7:6] to configure
+ // GPIO3 Bit [9:8] to configure
+ // GPIO4 each GPIO can be
+ // individully selected. When “00�
+ // GPIO is free resource. When “01�
+ // GPIO is APPS resource. When “10�
+ // GPIO is NWP resource. Writing 11
+ // doesnt have any affect, i.e. If
+ // one write only relevant gpio
+ // semaphore and other bits are 1s,
+ // it'll not disturb the other
+ // semaphore bits. For example : Say
+ // If NW wants to take control of
+ // gpio-1, one should write
+ // 10'b11_1111_1011 and if one wants
+ // to release it write
+ // 10'b11_1111_0011.
+
+#define COMMON_REG_GPIO_properties_register_GPIO_properties_register_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE1 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE1_APPS_NW_SEMAPHORE1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE2 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE2_APPS_NW_SEMAPHORE2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE3 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE3_APPS_NW_SEMAPHORE3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE4 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE4_APPS_NW_SEMAPHORE4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE5 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE5_APPS_NW_SEMAPHORE5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE6 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE6_APPS_NW_SEMAPHORE6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE7 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE7_APPS_NW_SEMAPHORE7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE8 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE8_APPS_NW_SEMAPHORE8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE9 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE9_APPS_NW_SEMAPHORE9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE10 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE10_APPS_NW_SEMAPHORE10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE11 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_M \
+ 0xFFFFFFFF // • Each semaphore register is of
+ // 2 bit. • When this register is
+ // set to 2’b01 – Apps have access
+ // and when set to 2’b10 – NW have
+ // access. • Ideally both the master
+ // can modify any of this 2 bit, but
+ // assumption apps will write only
+ // 2’b01 or 2’b00 to this register
+ // and nw will write only 2’b10 or
+ // 2’b00. • Implementation is when
+ // any of the bit of this register
+ // is set, only next write
+ // allowedvis 2’b00 – Again
+ // assumption is one master will not
+ // write 2’b00 if other is already
+ // holding the semaphore.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE11_APPS_NW_SEMAPHORE11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_NW_SEMAPHORE12 register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_M \
+ 0xFFFFFFFF // APPS NW semaphore register - not
+ // reflected in status.
+
+#define COMMON_REG_APPS_NW_SEMAPHORE12_APPS_NW_SEMAPHORE12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_SEMAPPHORE_PEND register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_M \
+ 0xFFFFFFFF // APPS SEMAPOHORE STATUS
+
+#define COMMON_REG_APPS_SEMAPPHORE_PEND_APPS_SEMAPPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_SEMAPPHORE_PEND register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_M \
+ 0xFFFFFFFF // NW SEMAPHORE STATUS
+
+#define COMMON_REG_NW_SEMAPPHORE_PEND_NW_SEMAPPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_STATUS register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_M \
+ 0xFFFFFFFF // SEMAPHORE STATUS 9:8 :semaphore
+ // status of flash_control 7:6
+ // :semaphore status of
+ // gpio_properties 5:4
+ // :semaphore status of
+ // spi_propertie 1:0 :semaphore
+ // status of i2c_propertie
+
+#define COMMON_REG_SEMAPHORE_STATUS_SEMAPHORE_STATUS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_IDMEM_TIM_Update register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_FPGA_ROM_WR_EN register.
+//
+//******************************************************************************
+#define COMMON_REG_FPGA_ROM_WR_EN_FPGA_ROM_WR_EN \
+ 0x00000001 // when '1' enables Write into
+ // IDMEM CORE ROM, APPS ROM, NWP ROM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_M \
+ 0xFFFFFFFF // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define COMMON_REG_NW_INT_MASK_NW_INT_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK_SET register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_M \
+ 0xFFFFFFFF // write 1 to set corresponding bit
+ // in NW_INT_MASK;0 = no effect
+
+#define COMMON_REG_NW_INT_MASK_SET_NW_INT_MASK_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // bit in NW_INT_MASK;0 = no effect
+
+#define COMMON_REG_NW_INT_MASK_CLR_NW_INT_MASK_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+ // interrupt is not lost if coincide
+ // with write operation
+
+#define COMMON_REG_NW_INT_STS_CLR_NW_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_ACK register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt;0 = no effect
+
+#define COMMON_REG_NW_INT_ACK_NW_INT_ACK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_TRIG register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_M \
+ 0xFFFFFFFF // Writing a 1 to a bit in this
+ // register causes the the Host CPU
+ // if enabled (not masked). This
+ // register is self-clearing.
+ // Writing 0 has no effect
+
+#define COMMON_REG_NW_INT_TRIG_NW_INT_TRIG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by NW_INT mask
+
+#define COMMON_REG_NW_INT_STS_MASKED_NW_INT_STS_MASKED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_NW_INT_STS_RAW register.
+//
+//******************************************************************************
+#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define COMMON_REG_NW_INT_STS_RAW_NW_INT_STS_RAW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_M \
+ 0xFFFFFFFF // 1= disable corresponding
+ // interrupt;0 = interrupt enabled
+
+#define COMMON_REG_APPS_INT_MASK_APPS_INT_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK_SET register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_M \
+ 0xFFFFFFFF // write 1 to set corresponding bit
+ // in APPS_INT_MASK;0 = no effect
+
+#define COMMON_REG_APPS_INT_MASK_SET_APPS_INT_MASK_SET_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_MASK_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // bit in APPS_INT_MASK;0 = no
+ // effect
+
+#define COMMON_REG_APPS_INT_MASK_CLR_APPS_INT_MASK_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_CLR register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt; 0 = no effect;
+ // interrupt is not lost if coincide
+ // with write operation
+
+#define COMMON_REG_APPS_INT_STS_CLR_APPS_INT_STS_CLR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_ACK register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_M \
+ 0xFFFFFFFF // write 1 to clear corresponding
+ // interrupt;0 = no effect
+
+#define COMMON_REG_APPS_INT_ACK_APPS_INT_ACK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_TRIG register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_M \
+ 0xFFFFFFFF // Writing a 1 to a bit in this
+ // register causes the the Host CPU
+ // if enabled (not masked). This
+ // register is self-clearing.
+ // Writing 0 has no effect
+
+#define COMMON_REG_APPS_INT_TRIG_APPS_INT_TRIG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_MASKED register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active and not masked. read is
+ // non-destructive;0 = corresponding
+ // interrupt is inactive or masked
+ // by APPS_INT mask
+
+#define COMMON_REG_APPS_INT_STS_MASKED_APPS_INT_STS_MASKED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_INT_STS_RAW register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_M \
+ 0xFFFFFFFF // 1= corresponding interrupt is
+ // active. read is non-destructive;0
+ // = corresponding interrupt is
+ // inactive
+
+#define COMMON_REG_APPS_INT_STS_RAW_APPS_INT_STS_RAW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_IDMEM_TIM_Updated register.
+//
+//******************************************************************************
+#define COMMON_REG_IDMEM_TIM_Updated_TIM_UPDATED \
+ 0x00000001 // toggle in this signal
+ // indicatesIDMEM_TIM_UPDATE
+ // register mentioned above is
+ // updated.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_APPS_GPIO_TRIG_EN register.
+//
+//******************************************************************************
+#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_M \
+ 0x0000001F // APPS GPIO Trigger EN control.
+ // Bit 0: when '1' enable GPIO 0
+ // trigger. This bit enables trigger
+ // for all GPIO 0 pins (GPIO 0 to
+ // GPIO7). Bit 1: when '1' enable
+ // GPIO 1 trigger. This bit enables
+ // trigger for all GPIO 1 pins (
+ // GPIO8 to GPIO15). Bit 2: when '1'
+ // enable GPIO 2 trigger. This bit
+ // enables trigger for all GPIO 2
+ // pins (GPIO16 to GPIO23). Bit 3:
+ // when '1' enable GPIO 3 trigger.
+ // This bit enables trigger for all
+ // GPIO 3 pins (GPIO24 to GPIO31).
+ // Bit 4: when '1' enable GPIO 4
+ // trigger. This bit enables trigger
+ // for all GPIO 4 pins.(GPIO32 to
+ // GPIO39)
+
+#define COMMON_REG_APPS_GPIO_TRIG_EN_APPS_GPIO_TRIG_EN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_EMU_DEBUG_REG register.
+//
+//******************************************************************************
+#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_M \
+ 0xFFFFFFFF // 0 th bit used for stalling APPS
+ // DMA and 1st bit is used for
+ // stalling NWP DMA for debug
+ // purpose. Other bits are unused.
+
+#define COMMON_REG_EMU_DEBUG_REG_EMU_DEBUG_REG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_STATUS2 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_M \
+ 0x00FFFFFF // SEMAPHORE STATUS 23:22
+ // :semaphore status of
+ // apps_nw_semaphore11 21:20
+ // :semaphore status of
+ // apps_nw_semaphore11 19:18
+ // :semaphore status of
+ // apps_nw_semaphore10 17:16
+ // :semaphore status of
+ // apps_nw_semaphore9 15:14
+ // :semaphore status of
+ // apps_nw_semaphore8 13:12
+ // :semaphore status of
+ // apps_nw_semaphore7 11:10
+ // :semaphore status of
+ // apps_nw_semaphore6 9:8 :semaphore
+ // status of apps_nw_semaphore5 7:6
+ // :semaphore status of
+ // apps_nw_semaphore4 5:4 :semaphore
+ // status of apps_nw_semaphore3 3:2
+ // :semaphore status of
+ // apps_nw_semaphore2 1:0 :semaphore
+ // status of apps_nw_semaphore1
+
+#define COMMON_REG_SEMAPHORE_STATUS2_SEMPAPHORE_STATUS2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_PREV_OWNER1 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_M \
+ 0x0003FFFF // 1:0 : prvious owner of
+ // i2c_properties_reg[1:0] 3:2 :
+ // prvious owner of
+ // spi_properties_reg[1:0] 5:4 :
+ // prvious owner of
+ // gpio_properties_reg[1:0] 9:8 :
+ // prvious owner of
+ // gpio_properties_reg[3:2] 11:10 :
+ // prvious owner of
+ // gpio_properties_reg[5:4] 13:12 :
+ // prvious owner of
+ // gpio_properties_reg[7:6] 15:14 :
+ // prvious owner of
+ // gpio_properties_reg[9:8] 17:16 :
+ // prvious owner of
+ // flash_control_reg[1:0]
+
+#define COMMON_REG_SEMAPHORE_PREV_OWNER1_SEMAPHORE_PREV_OWNER1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// COMMON_REG_O_SEMAPHORE_PREV_OWNER2 register.
+//
+//******************************************************************************
+#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_M \
+ 0x00FFFFFF // 1:0 : previous owner of
+ // apps_nw_semaphore1_reg[1:0] 3:2 :
+ // previous owner of
+ // apps_nw_semaphore2_reg[1:0] 5:4 :
+ // previous owner of
+ // apps_nw_semaphore3_reg[1:0] 7:6 :
+ // previous owner of
+ // apps_nw_semaphore4_reg[1:0] 9:8 :
+ // previous owner of
+ // apps_nw_semaphore5_reg[1:0] 11:10
+ // : previous owner of
+ // apps_nw_semaphore6_reg[1:0] 13:12
+ // : previous owner of
+ // apps_nw_semaphore7_reg[1:0] 15:14
+ // : previous owner of
+ // apps_nw_semaphore8_reg[1:0] 17:16
+ // : previous owner of
+ // apps_nw_semaphore9_reg[1:0] 19:18
+ // : previous owner of
+ // apps_nw_semaphore10_reg[1:0]
+ // 21:20 : previous owner of
+ // apps_nw_semaphore11_reg[1:0]
+ // 23:22 : previous owner of
+ // apps_nw_semaphore12_reg[1:0]
+
+#define COMMON_REG_SEMAPHORE_PREV_OWNER2_SEMAPHORE_PREV_OWNER2_S 0
+
+
+
+#endif // __HW_COMMON_REG_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_gpio.h b/ext/hal/ti/cc3220sdk/inc/hw_gpio.h
new file mode 100644
index 0000000..41ddbb1
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_gpio.h
@@ -0,0 +1,1347 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_GPIO_DATA 0x00000000 // 0x4000 5000 0x4000 6000 0x4000
+ // 7000 0x4002 4000 GPIO Data
+ // (GPIODATA)@@ offset 0x000 The
+ // GPIODATA register is the data
+ // register. In software control
+ // mode@@ values written in the
+ // GPIODATA register are transferred
+ // onto the GPIO port pins if the
+ // respective pins have been
+ // configured as outputs through the
+ // GPIO Direction (GPIODIR) register
+ // (see page 653). In order to write
+ // to GPIODATA@@ the corresponding
+ // bits in the mask@@ resulting from
+ // the address bus bits [9:2]@@ must
+ // be set. Otherwise@@ the bit
+ // values remain unchanged by the
+ // write. Similarly@@ the values
+ // read from this register are
+ // determined for each bit by the
+ // mask bit derived from the address
+ // used to access the data
+ // register@@ bits [9:2]. Bits that
+ // are set in the address mask cause
+ // the corresponding bits in
+ // GPIODATA to be read@@ and bits
+ // that are clear in the address
+ // mask cause the corresponding bits
+ // in GPIODATA to be read as 0@@
+ // regardless of their value. A read
+ // from GPIODATA returns the last
+ // bit value written if the
+ // respective pins are configured as
+ // outputs@@ or it returns the value
+ // on the corresponding input pin
+ // when these are configured as
+ // inputs. All bits are cleared by a
+ // reset.
+#define GPIO_O_GPIO_DIR 0x00000400 // 0x4000 5400 0x4000 6400 0x4000
+ // 7400 0x4002 4400 GPIO Direction
+ // (GPIODIR)@@ offset 0x400 The
+ // GPIODIR register is the data
+ // direction register. Setting a bit
+ // in the GPIODIR register
+ // configures the corresponding pin
+ // to be an output@@ while clearing
+ // a bit configures the
+ // corresponding pin to be an input.
+ // All bits are cleared by a reset@@
+ // meaning all GPIO pins are inputs
+ // by default.
+#define GPIO_O_GPIO_IS 0x00000404 // 0x4000 5404 0x4000 6404 0x4000
+ // 7404 0x4002 4404 GPIO Interrupt
+ // Sense (GPIOIS)@@ offset 0x404 The
+ // GPIOIS register is the interrupt
+ // sense register. Setting a bit in
+ // the GPIOIS register configures
+ // the corresponding pin to detect
+ // levels@@ while clearing a bit
+ // configures the corresponding pin
+ // to detect edges. All bits are
+ // cleared by a reset.
+#define GPIO_O_GPIO_IBE 0x00000408 // 0x4000 5408 0x4000 6408 0x4000
+ // 7408 0x4002 4408 GPIO Interrupt
+ // Both Edges (GPIOIBE)@@ offset
+ // 0x408 The GPIOIBE register allows
+ // both edges to cause interrupts.
+ // When the corresponding bit in the
+ // GPIO Interrupt Sense (GPIOIS)
+ // register is set to detect edges@@
+ // setting a bit in the GPIOIBE
+ // register configures the
+ // corresponding pin to detect both
+ // rising and falling edges@@
+ // regardless of the corresponding
+ // bit in the GPIO Interrupt Event
+ // (GPIOIEV) register . Clearing a
+ // bit configures the pin to be
+ // controlled by the GPIOIEV
+ // register. All bits are cleared by
+ // a reset.
+#define GPIO_O_GPIO_IEV 0x0000040C // 0x4000 540C 0x4000 640C 0x4000
+ // 740C 0x4002 440C GPIO Interrupt
+ // Event (GPIOIEV)@@ offset 0x40C
+ // The GPIOIEV register is the
+ // interrupt event register. Setting
+ // a bit in the GPIOIEV register
+ // configures the corresponding pin
+ // to detect rising edges or high
+ // levels@@ depending on the
+ // corresponding bit value in the
+ // GPIO Interrupt Sense (GPIOIS)
+ // register . Clearing a bit
+ // configures the pin to detect
+ // falling edges or low levels@@
+ // depending on the corresponding
+ // bit value in the GPIOIS register.
+ // All bits are cleared by a reset.
+#define GPIO_O_GPIO_IM 0x00000410 // 0x4000 5410 0x4000 6410 0x4000
+ // 7410 0x4002 4410 GPIO Interrupt
+ // Mask (GPIOIM)@@ offset 0x410 The
+ // GPIOIM register is the interrupt
+ // mask register. Setting a bit in
+ // the GPIOIM register allows
+ // interrupts that are generated by
+ // the corresponding pin to be sent
+ // to the interrupt controller on
+ // the combined interrupt signal.
+ // Clearing a bit prevents an
+ // interrupt on the corresponding
+ // pin from being sent to the
+ // interrupt controller. All bits
+ // are cleared by a reset.
+#define GPIO_O_GPIO_RIS 0x00000414 // 0x4000 5414 0x4000 6414 0x4000
+ // 7414 0x4002 4414 GPIO Raw
+ // Interrupt Status (GPIORIS)@@
+ // offset 0x414 The GPIORIS register
+ // is the raw interrupt status
+ // register. A bit in this register
+ // is set when an interrupt
+ // condition occurs on the
+ // corresponding GPIO pin. If the
+ // corresponding bit in the GPIO
+ // Interrupt Mask (GPIOIM) register
+ // is set@@ the interrupt is sent to
+ // the interrupt controller. Bits
+ // read as zero indicate that
+ // corresponding input pins have not
+ // initiated an interrupt. A bit in
+ // this register can be cleared by
+ // writing a 1 to the corresponding
+ // bit in the GPIO Interrupt Clear
+ // (GPIOICR) register.
+#define GPIO_O_GPIO_MIS 0x00000418 // 0x4000 5418 0x4000 6418 0x4000
+ // 7418 0x4002 4418 GPIO Masked
+ // Interrupt Status (GPIOMIS)@@
+ // offset 0x418 The GPIOMIS register
+ // is the masked interrupt status
+ // register. If a bit is set in this
+ // register@@ the corresponding
+ // interrupt has triggered an
+ // interrupt to the interrupt
+ // controller. If a bit is clear@@
+ // either no interrupt has been
+ // generated@@ or the interrupt is
+ // masked. If no port pin@@ other
+ // than the one that is being used
+ // as an ADC trigger@@ is being used
+ // to generate interrupts@@ the
+ // appropriate Interrupt Set Enable
+ // (ENn) register can disable the
+ // interrupts for the port@@ and the
+ // ADC interrupt can be used to read
+ // back the converted data.
+ // Otherwise@@ the port interrupt
+ // handler must ignore and clear
+ // interrupts on the port pin and
+ // wait for the ADC interrupt@@ or
+ // the ADC interrupt must be
+ // disabled in the EN0 register and
+ // the port interrupt handler must
+ // poll the ADC registers until the
+ // conversion is completed. If no
+ // port pin@@ other than the one
+ // that is being used as an ADC
+ // trigger@@ is being used to
+ // generate interrupts@@ the
+ // appropriate Interrupt Set Enable
+ // (ENn) register can disable the
+ // interrupts for the port@@ and the
+ // ADC interrupt can be used to read
+ // back the converted data.
+ // Otherwise@@ the port interrupt
+ // handler must ignore and clear
+ // interrupts on the port pin and
+ // wait for the ADC interrupt@@ or
+ // the ADC interrupt must be
+ // disabled in the EN0 register and
+ // the port interrupt handler must
+ // poll the ADC registers until the
+ // conversion is completed. Note
+ // that if the Port B GPIOADCCTL
+ // register is cleared@@ PB4 can
+ // still be used as an external
+ // trigger for the ADC. This is a
+ // legacy mode which allows code
+ // written for previous Stellaris
+ // devices to operate on this
+ // microcontroller. GPIOMIS is the
+ // state of the interrupt after
+ // masking.
+#define GPIO_O_GPIO_ICR 0x0000041C // 0x4000 541C 0x4000 641C 0x4000
+ // 741C 0x4002 441C GPIO Interrupt
+ // Clear (GPIOICR)@@ offset 0x41C
+ // The GPIOICR register is the
+ // interrupt clear register. Writing
+ // a 1 to a bit in this register
+ // clears the corresponding
+ // interrupt bit in the GPIORIS and
+ // GPIOMIS registers. Writing a 0
+ // has no effect.
+#define GPIO_O_GPIO_AFSEL 0x00000420 // 0x4000 5420 0x4000 6420 0x4000
+ // 7420 0x4002 4420 GPIO Alternate
+ // Function Select (GPIOAFSEL)@@
+ // offset 0x420 The GPIOAFSEL
+ // register is the mode control
+ // select register. If a bit is
+ // clear@@ the pin is used as a GPIO
+ // and is controlled by the GPIO
+ // registers. Setting a bit in this
+ // register configures the
+ // corresponding GPIO line to be
+ // controlled by an associated
+ // peripheral. Several possible
+ // peripheral functions are
+ // multiplexed on each GPIO. The
+ // GPIO Port Control (GPIOPCTL)
+ // register is used to select one of
+ // the possible functions.
+#define GPIO_O_GPIO_DR2R 0x00000500 // 0x4000 5500 0x4000 6500 0x4000
+ // 7500 0x4002 4500 GPIO 2-mA Drive
+ // Select (GPIODR2R)@@ offset 0x500
+ // The GPIODR2R register is the 2-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV2 bit for a GPIO
+ // signal@@ the corresponding DRV4
+ // bit in the GPIODR4R register and
+ // DRV8 bit in the GPIODR8R register
+ // are automatically cleared by
+ // hardware. By default@@ all GPIO
+ // pins have 2-mA drive.
+#define GPIO_O_GPIO_DR4R 0x00000504 // 0x4000 5504 0x4000 6504 0x4000
+ // 7504 0x4002 4504 GPIO 4-mA Drive
+ // Select (GPIODR4R)@@ offset 0x504
+ // The GPIODR4R register is the 4-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV4 bit for a GPIO
+ // signal@@ the corresponding DRV2
+ // bit in the GPIODR2R register and
+ // DRV8 bit in the GPIODR8R register
+ // are automatically cleared by
+ // hardware.
+#define GPIO_O_GPIO_DR8R 0x00000508 // 0x4000 5508 0x4000 6508 0x4000
+ // 7508 0x4002 4508 GPIO 8-mA Drive
+ // Select (GPIODR8R)@@ offset 0x508
+ // The GPIODR8R register is the 8-mA
+ // drive control register. Each GPIO
+ // signal in the port can be
+ // individually configured without
+ // affecting the other pads. When
+ // setting the DRV8 bit for a GPIO
+ // signal@@ the corresponding DRV2
+ // bit in the GPIODR2R register and
+ // DRV4 bit in the GPIODR4R register
+ // are automatically cleared by
+ // hardware. The 8-mA setting is
+ // also used for high-current
+ // operation. Note: There is no
+ // configuration difference between
+ // 8-mA and high-current operation.
+ // The additional current capacity
+ // results from a shift in the
+ // VOH/VOL levels.
+#define GPIO_O_GPIO_ODR 0x0000050C // 0x4000 550C 0x4000 650C 0x4000
+ // 750C 0x4002 450C GPIO Open Drain
+ // Select (GPIOODR)@@ offset 0x50C
+ // The GPIOODR register is the open
+ // drain control register. Setting a
+ // bit in this register enables the
+ // open-drain configuration of the
+ // corresponding GPIO pad. When
+ // open-drain mode is enabled@@ the
+ // corresponding bit should also be
+ // set in the GPIO Digital Input
+ // Enable (GPIODEN) register .
+ // Corresponding bits in the drive
+ // strength and slew rate control
+ // registers (GPIODR2R@@ GPIODR4R@@
+ // GPIODR8R@@ and GPIOSLR) can be
+ // set to achieve the desired rise
+ // and fall times. The GPIO acts as
+ // an open-drain input if the
+ // corresponding bit in the GPIODIR
+ // register is cleared. If open
+ // drain is selected while the GPIO
+ // is configured as an input@@ the
+ // GPIO will remain an input and the
+ // open-drain selection has no
+ // effect until the GPIO is changed
+ // to an output. When using the I2C
+ // module@@ in addition to
+ // configuring the pin to open
+ // drain@@ the GPIO Alternate
+ // Function Select (GPIOAFSEL)
+ // register bits for the I2C clock
+ // and data pins should be set
+#define GPIO_O_GPIO_PUR 0x00000510 // 0x4000 5510 0x4000 6510 0x4000
+ // 7510 0x4002 4510 GPIO Pull-Up
+ // Select (GPIOPUR)@@ offset 0x510
+ // The GPIOPUR register is the
+ // pull-up control register. When a
+ // bit is set@@ a weak pull-up
+ // resistor on the corresponding
+ // GPIO signal is enabled. Setting a
+ // bit in GPIOPUR automatically
+ // clears the corresponding bit in
+ // the GPIO Pull-Down Select
+ // (GPIOPDR) register . Write access
+ // to this register is protected
+ // with the GPIOCR register. Bits in
+ // GPIOCR that are cleared prevent
+ // writes to the equivalent bit in
+ // this register.
+#define GPIO_O_GPIO_PDR 0x00000514 // 0x4000 5514 0x4000 6514 0x4000
+ // 7514 0x4002 4514 GPIO Pull-Down
+ // Select (GPIOPDR)@@ offset 0x514
+ // The GPIOPDR register is the
+ // pull-down control register. When
+ // a bit is set@@ a weak pull-down
+ // resistor on the corresponding
+ // GPIO signal is enabled. Setting a
+ // bit in GPIOPDR automatically
+ // clears the corresponding bit in
+ // the GPIO Pull-Up Select (GPIOPUR)
+ // register
+#define GPIO_O_GPIO_SLR 0x00000518 // 0x4000 5518 0x4000 6518 0x4000
+ // 7518 0x4002 4518 The GPIOSLR
+ // register is the slew rate control
+ // register. Slew rate control is
+ // only available when using the
+ // 8-mA drive strength option via
+ // the GPIO 8-mA Drive Select
+ // (GPIODR8R) register
+#define GPIO_O_GPIO_DEN 0x0000051C // 0x4000 551C 0x4000 651C 0x4000
+ // 751C 0x4002 451C GPIO Digital
+ // Enable (GPIODEN)@@ offset 0x51C
+ // Note: Pins configured as digital
+ // inputs are Schmitt-triggered. The
+ // GPIODEN register is the digital
+ // enable register. By default@@ all
+ // GPIO signals except those listed
+ // below are configured out of reset
+ // to be undriven (tristate). Their
+ // digital function is disabled;
+ // they do not drive a logic value
+ // on the pin and they do not allow
+ // the pin voltage into the GPIO
+ // receiver. To use the pin as a
+ // digital input or output (either
+ // GPIO or alternate function)@@ the
+ // corresponding GPIODEN bit must be
+ // set.
+#define GPIO_O_GPIO_LOCK 0x00000520 // 0x4000 5520 0x4000 6520 0x4000
+ // 7520 0x4002 4520 GPIO Lock
+ // (GPIOLOCK)@@ offset 0x520 The
+ // GPIOLOCK register enables write
+ // access to the GPIOCR register .
+ // Writing 0x4C4F.434B to the
+ // GPIOLOCK register unlocks the
+ // GPIOCR register. Writing any
+ // other value to the GPIOLOCK
+ // register re-enables the locked
+ // state. Reading the GPIOLOCK
+ // register returns the lock status
+ // rather than the 32-bit value that
+ // was previously written.
+ // Therefore@@ when write accesses
+ // are disabled@@ or locked@@
+ // reading the GPIOLOCK register
+ // returns 0x0000.0001. When write
+ // accesses are enabled@@ or
+ // unlocked@@ reading the GPIOLOCK
+ // register returns 0x0000.0000.
+#define GPIO_O_GPIO_CR 0x00000524 // 0x4000 5524 0x4000 6524 0x4000
+ // 7524 0x4002 4524 GPIO Commit
+ // (GPIOCR)@@ offset 0x524 The
+ // GPIOCR register is the commit
+ // register. The value of the GPIOCR
+ // register determines which bits of
+ // the GPIOAFSEL@@ GPIOPUR@@
+ // GPIOPDR@@ and GPIODEN registers
+ // are committed when a write to
+ // these registers is performed. If
+ // a bit in the GPIOCR register is
+ // cleared@@ the data being written
+ // to the corresponding bit in the
+ // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
+ // or GPIODEN registers cannot be
+ // committed and retains its
+ // previous value. If a bit in the
+ // GPIOCR register is set@@ the data
+ // being written to the
+ // corresponding bit of the
+ // GPIOAFSEL@@ GPIOPUR@@ GPIOPDR@@
+ // or GPIODEN registers is committed
+ // to the register and reflects the
+ // new value. The contents of the
+ // GPIOCR register can only be
+ // modified if the status in the
+ // GPIOLOCK register is unlocked.
+ // Writes to the GPIOCR register are
+ // ignored if the status in the
+ // GPIOLOCK register is locked.
+#define GPIO_O_GPIO_AMSEL 0x00000528 // 0x4000 5528 0x4000 6528 0x4000
+ // 7528 0x4002 4528 The GPIOAMSEL
+ // register controls isolation
+ // circuits to the analog side of a
+ // unified I/O pad. Because the
+ // GPIOs may be driven by a 5-V
+ // source and affect analog
+ // operation@@ analog circuitry
+ // requires isolation from the pins
+ // when they are not used in their
+ // analog function. Each bit of this
+ // register controls the isolation
+ // circuitry for the corresponding
+ // GPIO signal.
+#define GPIO_O_GPIO_PCTL 0x0000052C // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) 0x4000 552C
+ // 0x4000 652C 0x4000 752C 0x4002
+ // 452C GPIO Port Control
+ // (GPIOPCTL)@@ offset 0x52C The
+ // GPIOPCTL register is used in
+ // conjunction with the GPIOAFSEL
+ // register and selects the specific
+ // peripheral signal for each GPIO
+ // pin when using the alternate
+ // function mode. Most bits in the
+ // GPIOAFSEL register are cleared on
+ // reset@@ therefore most GPIO pins
+ // are configured as GPIOs by
+ // default. When a bit is set in the
+ // GPIOAFSEL register@@ the
+ // corresponding GPIO signal is
+ // controlled by an associated
+ // peripheral. The GPIOPCTL register
+ // selects one out of a set of
+ // peripheral functions for each
+ // GPIO@@ providing additional
+ // flexibility in signal definition.
+#define GPIO_O_GPIO_ADCCTL 0x00000530 // This register is not used in
+ // cc3xx. ADC trigger via GPIO is
+ // not supported. 0x4000 5530 0x4000
+ // 6530 0x4000 7530 0x4002 4530 GPIO
+ // ADC Control (GPIOADCCTL)@@ offset
+ // 0x530 This register is used to
+ // configure a GPIO pin as a source
+ // for the ADC trigger. Note that if
+ // the Port B GPIOADCCTL register is
+ // cleared@@ PB4 can still be used
+ // as an external trigger for the
+ // ADC. This is a legacy mode which
+ // allows code written for previous
+ // Stellaris devices to operate on
+ // this microcontroller.
+#define GPIO_O_GPIO_DMACTL 0x00000534 // 0x4000 5534 0x4000 6534 0x4000
+ // 7534 0x4002 4534 GPIO DMA Control
+ // (GPIODMACTL)@@ offset 0x534 This
+ // register is used to configure a
+ // GPIO pin as a source for the ?DMA
+ // trigger.
+#define GPIO_O_GPIO_SI 0x00000538 // 0x4000 5538 0x4000 6538 0x4000
+ // 7538 0x4002 4538 GPIO Select
+ // Interrupt (GPIOSI)@@ offset 0x538
+ // This register is used to enable
+ // individual interrupts for each
+ // pin. Note: This register is only
+ // available on Port P and Port Q.
+#define GPIO_O_GPIO_PERIPHID4 0x00000FD0 // 0x4000 5FD0 0x4000 6FD0 0x4000
+ // 7FD0 0x4002 4FD0 GPIO Peripheral
+ // Identification 4
+ // (GPIOPeriphID4)@@ offset 0xFD0
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID5 0x00000FD4 // 0x4000 5FD4 0x4000 6FD4 0x4000
+ // 7FD4 0x4002 4FD4 GPIO Peripheral
+ // Identification 5
+ // (GPIOPeriphID5)@@ offset 0xFD4
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID6 0x00000FD8 // 0x4000 5FD8 0x4000 6FD8 0x4000
+ // 7FD8 0x4002 4FD8 GPIO Peripheral
+ // Identification 6
+ // (GPIOPeriphID6)@@ offset 0xFD8
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID7 0x00000FDC // 0x4000 5FDC 0x4000 6FDC 0x4000
+ // 7FDC 0x4002 4FDC GPIO Peripheral
+ // Identification 7
+ // (GPIOPeriphID7)@@ offset 0xFDC
+ // The GPIOPeriphID4@@
+ // GPIOPeriphID5@@ GPIOPeriphID6@@
+ // and GPIOPeriphID7 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID0 0x00000FE0 // 0x4000 5FE0 0x4000 6FE0 0x4000
+ // 7FE0 0x4002 4FE0 GPIO Peripheral
+ // Identification 0
+ // (GPIOPeriphID0)@@ offset 0xFE0
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID1 0x00000FE4 // 0x4000 5FE4 0x4000 6FE4 0x4000
+ // 7FE4 0x4002 4FE4 GPIO Peripheral
+ // Identification 1
+ // (GPIOPeriphID1)@@ offset 0xFE4
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID2 0x00000FE8 // 0x4000 5FE8 0x4000 6FE8 0x4000
+ // 7FE8 0x4002 4FE8 GPIO Peripheral
+ // Identification 2
+ // (GPIOPeriphID2)@@ offset 0xFE8
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PERIPHID3 0x00000FEC // 0x4000 5FEC 0x4000 6FEC 0x4000
+ // 7FEC 0x4002 4FEC GPIO Peripheral
+ // Identification 3
+ // (GPIOPeriphID3)@@ offset 0xFEC
+ // The GPIOPeriphID0@@
+ // GPIOPeriphID1@@ GPIOPeriphID2@@
+ // and GPIOPeriphID3 registers can
+ // conceptually be treated as one
+ // 32-bit register; each register
+ // contains eight bits of the 32-bit
+ // register@@ used by software to
+ // identify the peripheral.
+#define GPIO_O_GPIO_PCELLID0 0x00000FF0 // 0x4000 5FF0 0x4000 6FF0 0x4000
+ // 7FF0 0x4002 4FF0 GPIO PrimeCell
+ // Identification 0 (GPIOPCellID0)@@
+ // offset 0xFF0 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID1 0x00000FF4 // 0x4000 5FF4 0x4000 6FF4 0x4000
+ // 7FF4 0x4002 4FF4 GPIO PrimeCell
+ // Identification 1 (GPIOPCellID1)@@
+ // offset 0xFF4 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID2 0x00000FF8 // 0x4000 5FF8 0x4000 6FF8 0x4000
+ // 7FF8 0x4002 4FF8 GPIO PrimeCell
+ // Identification 2 (GPIOPCellID2)@@
+ // offset 0xFF8 The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.
+#define GPIO_O_GPIO_PCELLID3 0x00000FFC // 0x4000 5FFC 0x4000 6FFC 0x4000
+ // 7FFC 0x4002 4FFC GPIO PrimeCell
+ // Identification 3 (GPIOPCellID3)@@
+ // offset 0xFFC The GPIOPCellID0@@
+ // GPIOPCellID1@@ GPIOPCellID2@@ and
+ // GPIOPCellID3 registers are four
+ // 8-bit wide registers@@ that can
+ // conceptually be treated as one
+ // 32-bit register. The register is
+ // used as a standard
+ // cross-peripheral identification
+ // system.0xb1
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DATA register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DATA_DATA_M 0x000000FF // GPIO Data This register is
+ // virtually mapped to 256 locations
+ // in the address space. To
+ // facilitate the reading and
+ // writing of data to these
+ // registers by independent
+ // drivers@@ the data read from and
+ // written to the registers are
+ // masked by the eight address lines
+ // [9:2]. Reads from this register
+ // return its current state. Writes
+ // to this register only affect bits
+ // that are not masked by ADDR[9:2]
+ // and are configured as outputs.
+#define GPIO_GPIO_DATA_DATA_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DIR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DIR_DIR_M 0x000000FF // GPIO Data Direction Value
+ // Description 0 Corresponding pin
+ // is an input. 1 Corresponding pins
+ // is an output.
+#define GPIO_GPIO_DIR_DIR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IS_IS_M 0x000000FF // GPIO Interrupt Sense Value
+ // Description 0 The edge on the
+ // corresponding pin is detected
+ // (edge-sensitive). 1 The level on
+ // the corresponding pin is detected
+ // (level-sensitive).
+#define GPIO_GPIO_IS_IS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IBE register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IBE_IBE_M 0x000000FF // GPIO Interrupt Both Edges Value
+ // Description 0 Interrupt
+ // generation is controlled by the
+ // GPIO Interrupt Event (GPIOIEV)
+ // register. 1 Both edges on the
+ // corresponding pin trigger an
+ // interrupt.
+#define GPIO_GPIO_IBE_IBE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IEV register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IEV_IEV_M 0x000000FF // GPIO Interrupt Event Value
+ // Description 1 A falling edge or a
+ // Low level on the corresponding
+ // pin triggers an interrupt. 0 A
+ // rising edge or a High level on
+ // the corresponding pin triggers an
+ // interrupt.
+#define GPIO_GPIO_IEV_IEV_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_IM register.
+//
+//******************************************************************************
+#define GPIO_GPIO_IM_IME_M 0x000000FF // GPIO Interrupt Mask Enable Value
+ // Description 0 The interrupt from
+ // the corresponding pin is masked.
+ // 1 The interrupt from the
+ // corresponding pin is sent to the
+ // interrupt controller.
+#define GPIO_GPIO_IM_IME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_RIS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_RIS_RIS_M 0x000000FF // GPIO Interrupt Raw Status Value
+ // Description 1 An interrupt
+ // condition has occurred on the
+ // corresponding pin. 0 interrupt
+ // condition has not occurred on the
+ // corresponding pin. A bit is
+ // cleared by writing a 1 to the
+ // corresponding bit in the GPIOICR
+ // register.
+#define GPIO_GPIO_RIS_RIS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_MIS register.
+//
+//******************************************************************************
+#define GPIO_GPIO_MIS_MIS_M 0x000000FF // GPIO Masked Interrupt Status
+ // Value Description 1 An interrupt
+ // condition on the corresponding
+ // pin has triggered an interrupt to
+ // the interrupt controller. 0 An
+ // interrupt condition on the
+ // corresponding pin is masked or
+ // has not occurred. A bit is
+ // cleared by writing a 1 to the
+ // corresponding bit in the GPIOICR
+ // register.
+#define GPIO_GPIO_MIS_MIS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_ICR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ICR_IC_M 0x000000FF // GPIO Interrupt Clear Value
+ // Description 1 The corresponding
+ // interrupt is cleared. 0 The
+ // corresponding interrupt is
+ // unaffected.
+#define GPIO_GPIO_ICR_IC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_AFSEL register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR2R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR2R_DRV2_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 2-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 2-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR4R
+ // or GPIODR8R register. 0 Setting a
+ // bit in either the GPIODR4
+ // register or the GPIODR8 register
+ // clears the corresponding 2-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR2R_DRV2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR4R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR4R_DRV4_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 4-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 4-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR2R
+ // or GPIODR8R register. 0 Setting a
+ // bit in either the GPIODR2
+ // register or the GPIODR8 register
+ // clears the corresponding 4-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR4R_DRV4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DR8R register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DR8R_DRV8_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // 8-mA Drive Enable Value
+ // Description 1 The corresponding
+ // GPIO pin has 8-mA drive. The
+ // drive for the corresponding GPIO
+ // pin is controlled by the GPIODR2R
+ // or GPIODR4R register. 0 Setting a
+ // bit in either the GPIODR2
+ // register or the GPIODR4 register
+ // clears the corresponding 8-mA
+ // enable bit. The change is
+ // effective on the second clock
+ // cycle after the write if
+ // accessing GPIO via the APB memory
+ // aperture. If using AHB access@@
+ // the change is effective on the
+ // next clock cycle.
+#define GPIO_GPIO_DR8R_DRV8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_ODR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ODR_ODE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Output Pad
+ // Open Drain Enable Value
+ // Description 1 The corresponding
+ // pin is configured as open drain.
+ // 0 The corresponding pin is not
+ // configured as open drain.
+#define GPIO_GPIO_ODR_ODE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PUR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PUR_PUE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Pad Weak
+ // Pull-Up Enable Value Description
+ // 1 The corresponding pin has a
+ // weak pull-up resistor. 0 The
+ // corresponding pin is not
+ // affected. Setting a bit in the
+ // GPIOPDR register clears the
+ // corresponding bit in the GPIOPUR
+ // register. The change is effective
+ // on the second clock cycle after
+ // the write if accessing GPIO via
+ // the APB memory aperture. If using
+ // AHB access@@ the change is
+ // effective on the next clock
+ // cycle.
+#define GPIO_GPIO_PUR_PUE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PDR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PDR_PDE_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Pad Weak
+ // Pull-Down Enable Value
+ // Description 1 The corresponding
+ // pin has a weak pull-down
+ // resistor. 0 The corresponding pin
+ // is not affected. Setting a bit in
+ // the GPIOPUR register clears the
+ // corresponding bit in the GPIOPDR
+ // register. The change is effective
+ // on the second clock cycle after
+ // the write if accessing GPIO via
+ // the APB memory aperture. If using
+ // AHB access@@ the change is
+ // effective on the next clock
+ // cycle.
+#define GPIO_GPIO_PDR_PDE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_SLR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_SLR_SRL_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Slew Rate
+ // Limit Enable (8-mA drive only)
+ // Value Description 1 Slew rate
+ // control is enabled for the
+ // corresponding pin. 0 Slew rate
+ // control is disabled for the
+ // corresponding pin.
+#define GPIO_GPIO_SLR_SRL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_DEN register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DEN_DEN_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Digital Enable
+ // Value Description 0 The digital
+ // functions for the corresponding
+ // pin are disabled. 1 The digital
+ // functions for the corresponding
+ // pin are enabled.
+#define GPIO_GPIO_DEN_DEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_LOCK register.
+//
+//******************************************************************************
+#define GPIO_GPIO_LOCK_LOCK_M 0xFFFFFFFF // This register is not used in
+ // cc3xx. GPIO Lock A write of the
+ // value 0x4C4F.434B unlocks the
+ // GPIO Commit (GPIOCR) register for
+ // write access.A write of any other
+ // value or a write to the GPIOCR
+ // register reapplies the lock@@
+ // preventing any register updates.
+ // A read of this register returns
+ // the following values: Value
+ // Description 0x1 The GPIOCR
+ // register is locked and may not be
+ // modified. 0x0 The GPIOCR register
+ // is unlocked and may be modified.
+#define GPIO_GPIO_LOCK_LOCK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_CR register.
+//
+//******************************************************************************
+#define GPIO_GPIO_CR_CR_M 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) GPIO Commit
+ // Value Description The
+ // corresponding GPIOAFSEL@@
+ // GPIOPUR@@ GPIOPDR@@ or GPIODEN
+ // bits can be written. 1 The
+ // corresponding GPIOAFSEL@@
+ // GPIOPUR@@ GPIOPDR@@ or GPIODEN
+ // bits cannot be written. 0 Note:
+ // The default register type for the
+ // GPIOCR register is RO for all
+ // GPIO pins with the exception of
+ // the NMI pin and the four JTAG/SWD
+ // pins (PD7@@ PF0@@ and PC[3:0]).
+ // These six pins are the only GPIOs
+ // that are protected by the GPIOCR
+ // register. Because of this@@ the
+ // register type for GPIO Port D7@@
+ // GPIO Port F0@@ and GPIO Port
+ // C[3:0] is R/W. The default reset
+ // value for the GPIOCR register is
+ // 0x0000.00FF for all GPIO pins@@
+ // with the exception of the NMI pin
+ // and the four JTAG/SWD pins (PD7@@
+ // PF0@@ and PC[3:0]). To ensure
+ // that the JTAG port is not
+ // accidentally programmed as GPIO
+ // pins@@ the PC[3:0] pins default
+ // to non-committable. Similarly@@
+ // to ensure that the NMI pin is not
+ // accidentally programmed as a GPIO
+ // pin@@ the PD7 and PF0 pins
+ // default to non-committable.
+ // Because of this@@ the default
+ // reset value of GPIOCR for GPIO
+ // Port C is 0x0000.00F0@@ for GPIO
+ // Port D is 0x0000.007F@@ and for
+ // GPIO Port F is 0x0000.00FE.
+#define GPIO_GPIO_CR_CR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_AMSEL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_AMSEL_GPIO_AMSEL_M \
+ 0x000000FF // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) GPIO Analog
+ // Mode Select Value Description 1
+ // The analog function of the pin is
+ // enabled@@ the isolation is
+ // disabled@@ and the pin is capable
+ // of analog functions. 0 The analog
+ // function of the pin is disabled@@
+ // the isolation is enabled@@ and
+ // the pin is capable of digital
+ // functions as specified by the
+ // other GPIO configuration
+ // registers. Note: This register
+ // and bits are only valid for GPIO
+ // signals that share analog
+ // function through a unified I/O
+ // pad. The reset state of this
+ // register is 0 for all signals.
+
+#define GPIO_GPIO_AMSEL_GPIO_AMSEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_PCTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCTL_PMC7_M 0xF0000000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 7 This field controls the
+ // configuration for GPIO pin 7.
+#define GPIO_GPIO_PCTL_PMC7_S 28
+#define GPIO_GPIO_PCTL_PMC6_M 0x0F000000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 6 This field controls the
+ // configuration for GPIO pin 6.
+#define GPIO_GPIO_PCTL_PMC6_S 24
+#define GPIO_GPIO_PCTL_PMC5_M 0x00F00000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 5 This field controls the
+ // configuration for GPIO pin 5.
+#define GPIO_GPIO_PCTL_PMC5_S 20
+#define GPIO_GPIO_PCTL_PMC4_M 0x000F0000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 4 This field controls the
+ // configuration for GPIO pin 4.
+#define GPIO_GPIO_PCTL_PMC4_S 16
+#define GPIO_GPIO_PCTL_PMC3_M 0x0000F000 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 43 This field controls
+ // the configuration for GPIO pin 3.
+#define GPIO_GPIO_PCTL_PMC3_S 12
+#define GPIO_GPIO_PCTL_PMC1_M 0x00000F00 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 1 This field controls the
+ // configuration for GPIO pin 1.
+#define GPIO_GPIO_PCTL_PMC1_S 8
+#define GPIO_GPIO_PCTL_PMC2_M 0x000000F0 // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 2 This field controls the
+ // configuration for GPIO pin 2.
+#define GPIO_GPIO_PCTL_PMC2_S 4
+#define GPIO_GPIO_PCTL_PMC0_M 0x0000000F // This register is not used in
+ // cc3xx. equivalant register exsist
+ // outside GPIO IP (refer
+ // PAD*_config register in the
+ // shared comn space) Port Mux
+ // Control 0 This field controls the
+ // configuration for GPIO pin 0.
+#define GPIO_GPIO_PCTL_PMC0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_ADCCTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_ADCCTL_ADCEN_M \
+ 0x000000FF // This register is not used in
+ // cc3xx. ADC trigger via GPIO is
+ // not supported. ADC Trigger Enable
+ // Value Description 1 The
+ // corresponding pin is used to
+ // trigger the ADC. 0 The
+ // corresponding pin is not used to
+ // trigger the ADC.
+
+#define GPIO_GPIO_ADCCTL_ADCEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_DMACTL register.
+//
+//******************************************************************************
+#define GPIO_GPIO_DMACTL_DMAEN_M \
+ 0x000000FF // This register is not used in the
+ // cc3xx. Alternate register to
+ // support this feature is coded in
+ // the APPS_NWP_CMN space. refer
+ // register as offset 0x400F70D8
+ // ?DMA Trigger Enable Value
+ // Description 1 The corresponding
+ // pin is used to trigger the ?DMA.
+ // 0 The corresponding pin is not
+ // used to trigger the ?DMA.
+
+#define GPIO_GPIO_DMACTL_DMAEN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_GPIO_SI register.
+//
+//******************************************************************************
+#define GPIO_GPIO_SI_SUM 0x00000001 // Summary Interrupt Value
+ // Description 1 Each pin has its
+ // own interrupt vector. 0 All port
+ // pin interrupts are OR'ed together
+ // to produce a summary interrupt.
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID4 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID4_PID4_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [7:0]
+
+#define GPIO_GPIO_PERIPHID4_PID4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID5 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID5_PID5_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [15:8]
+
+#define GPIO_GPIO_PERIPHID5_PID5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID6 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID6_PID6_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [23:16]
+
+#define GPIO_GPIO_PERIPHID6_PID6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID7 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID7_PID7_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [31:24]
+
+#define GPIO_GPIO_PERIPHID7_PID7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID0 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID0_PID0_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [7:0] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID0_PID0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID1 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID1_PID1_M \
+ 0x000000FF // GPIO Peripheral ID Register
+ // [15:8] Can be used by software to
+ // identify the presence of this
+ // peripheral.
+
+#define GPIO_GPIO_PERIPHID1_PID1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID2 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID2_PID2_M \
+ 0x000000FF // This register is not used in
+ // CC3XX.v GPIO Peripheral ID
+ // Register [23:16] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID2_PID2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PERIPHID3 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PERIPHID3_PID3_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO Peripheral ID
+ // Register [31:24] Can be used by
+ // software to identify the presence
+ // of this peripheral.
+
+#define GPIO_GPIO_PERIPHID3_PID3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID0 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID0_CID0_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [7:0] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID0_CID0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID1 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID1_CID1_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [15:8] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID1_CID1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID2 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID2_CID2_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [23:16] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID2_CID2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPIO_O_GPIO_PCELLID3 register.
+//
+//******************************************************************************
+#define GPIO_GPIO_PCELLID3_CID3_M \
+ 0x000000FF // This register is not used in
+ // CC3XX. GPIO PrimeCell ID Register
+ // [31:24] Provides software a
+ // standard cross-peripheral
+ // identification system.
+
+#define GPIO_GPIO_PCELLID3_CID3_S 0
+
+
+
+#endif // __HW_GPIO_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_gprcm.h b/ext/hal/ti/cc3220sdk/inc/hw_gprcm.h
new file mode 100644
index 0000000..1683e38
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_gprcm.h
@@ -0,0 +1,3320 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_GPRCM_H__
+#define __HW_GPRCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPRCM register offsets.
+//
+//*****************************************************************************
+#define GPRCM_O_APPS_SOFT_RESET 0x00000000
+#define GPRCM_O_APPS_LPDS_WAKEUP_CFG \
+ 0x00000004
+
+#define GPRCM_O_APPS_LPDS_WAKEUP_SRC \
+ 0x00000008
+
+#define GPRCM_O_APPS_RESET_CAUSE \
+ 0x0000000C
+
+#define GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG \
+ 0x00000010
+
+#define GPRCM_O_APPS_SRAM_DSLP_CFG \
+ 0x00000018
+
+#define GPRCM_O_APPS_SRAM_LPDS_CFG \
+ 0x0000001C
+
+#define GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG \
+ 0x00000020
+
+#define GPRCM_O_TOP_DIE_ENABLE 0x00000100
+#define GPRCM_O_TOP_DIE_ENABLE_PARAMETERS \
+ 0x00000104
+
+#define GPRCM_O_MCU_GLOBAL_SOFT_RESET \
+ 0x00000108
+
+#define GPRCM_O_ADC_CLK_CONFIG 0x0000010C
+#define GPRCM_O_APPS_GPIO_WAKE_CONF \
+ 0x00000110
+
+#define GPRCM_O_EN_NWP_BOOT_WO_DEVINIT \
+ 0x00000114
+
+#define GPRCM_O_MEM_HCLK_DIV_CFG \
+ 0x00000118
+
+#define GPRCM_O_MEM_SYSCLK_DIV_CFG \
+ 0x0000011C
+
+#define GPRCM_O_APLLMCS_LOCK_TIME_CONF \
+ 0x00000120
+
+#define GPRCM_O_NWP_SOFT_RESET 0x00000400
+#define GPRCM_O_NWP_LPDS_WAKEUP_CFG \
+ 0x00000404
+
+#define GPRCM_O_NWP_LPDS_WAKEUP_SRC \
+ 0x00000408
+
+#define GPRCM_O_NWP_RESET_CAUSE 0x0000040C
+#define GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG \
+ 0x00000410
+
+#define GPRCM_O_NWP_SRAM_DSLP_CFG \
+ 0x00000418
+
+#define GPRCM_O_NWP_SRAM_LPDS_CFG \
+ 0x0000041C
+
+#define GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG \
+ 0x00000420
+
+#define GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL \
+ 0x00000424
+
+#define GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ \
+ 0x00000428
+
+#define GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST \
+ 0x0000042C
+
+#define GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST \
+ 0x00000430
+
+#define GPRCM_O_NWP_GPIO_WAKE_CONF \
+ 0x00000434
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG12 \
+ 0x00000438
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG5 \
+ 0x00000448
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG6 \
+ 0x0000044C
+
+#define GPRCM_O_REF_FSM_CFG0 0x00000800
+#define GPRCM_O_REF_FSM_CFG1 0x00000804
+#define GPRCM_O_APLLMCS_WLAN_CONFIG0_40 \
+ 0x00000808
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG1_40 \
+ 0x0000080C
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG0_26 \
+ 0x00000810
+
+#define GPRCM_O_APLLMCS_WLAN_CONFIG1_26 \
+ 0x00000814
+
+#define GPRCM_O_APLLMCS_WLAN_OVERRIDES \
+ 0x00000818
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 \
+ 0x0000081C
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 \
+ 0x00000820
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 \
+ 0x00000824
+
+#define GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 \
+ 0x00000828
+
+#define GPRCM_O_SPARE_RW0 0x0000082C
+#define GPRCM_O_SPARE_RW1 0x00000830
+#define GPRCM_O_APLLMCS_MCU_OVERRIDES \
+ 0x00000834
+
+#define GPRCM_O_SYSCLK_SWITCH_STATUS \
+ 0x00000838
+
+#define GPRCM_O_REF_LDO_CONTROLS \
+ 0x0000083C
+
+#define GPRCM_O_REF_RTRIM_CONTROL \
+ 0x00000840
+
+#define GPRCM_O_REF_SLICER_CONTROLS0 \
+ 0x00000844
+
+#define GPRCM_O_REF_SLICER_CONTROLS1 \
+ 0x00000848
+
+#define GPRCM_O_REF_ANA_BGAP_CONTROLS0 \
+ 0x0000084C
+
+#define GPRCM_O_REF_ANA_BGAP_CONTROLS1 \
+ 0x00000850
+
+#define GPRCM_O_REF_ANA_SPARE_CONTROLS0 \
+ 0x00000854
+
+#define GPRCM_O_REF_ANA_SPARE_CONTROLS1 \
+ 0x00000858
+
+#define GPRCM_O_MEMSS_PSCON_OVERRIDES0 \
+ 0x0000085C
+
+#define GPRCM_O_MEMSS_PSCON_OVERRIDES1 \
+ 0x00000860
+
+#define GPRCM_O_PLL_REF_LOCK_OVERRIDES \
+ 0x00000864
+
+#define GPRCM_O_MCU_PSCON_DEBUG 0x00000868
+#define GPRCM_O_MEMSS_PWR_PS 0x0000086C
+#define GPRCM_O_REF_FSM_DEBUG 0x00000870
+#define GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE \
+ 0x00000874
+
+#define GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG \
+ 0x00000878
+
+#define GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES \
+ 0x0000087C
+
+#define GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES \
+ 0x00000880
+
+#define GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES \
+ 0x00000884
+
+#define GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES \
+ 0x00000888
+
+#define GPRCM_O_MEM_REF_FSM_CFG2 \
+ 0x0000088C
+
+#define GPRCM_O_TESTCTRL_POWER_CTRL \
+ 0x00000C10
+
+#define GPRCM_O_SSDIO_POWER_CTRL \
+ 0x00000C14
+
+#define GPRCM_O_MCSPI_N1_POWER_CTRL \
+ 0x00000C18
+
+#define GPRCM_O_WELP_POWER_CTRL 0x00000C1C
+#define GPRCM_O_WL_SDIO_POWER_CTRL \
+ 0x00000C20
+
+#define GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG \
+ 0x00000C24
+
+#define GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG \
+ 0x00000C28
+
+#define GPRCM_O_APPS_SECURE_INIT_DONE \
+ 0x00000C30
+
+#define GPRCM_O_APPS_DEV_MODE_INIT_DONE \
+ 0x00000C34
+
+#define GPRCM_O_EN_APPS_REBOOT 0x00000C38
+#define GPRCM_O_MEM_APPS_PERIPH_PRESENT \
+ 0x00000C3C
+
+#define GPRCM_O_MEM_NWP_PERIPH_PRESENT \
+ 0x00000C40
+
+#define GPRCM_O_MEM_SHARED_PERIPH_PRESENT \
+ 0x00000C44
+
+#define GPRCM_O_NWP_PWR_STATE 0x00000C48
+#define GPRCM_O_APPS_PWR_STATE 0x00000C4C
+#define GPRCM_O_MCU_PWR_STATE 0x00000C50
+#define GPRCM_O_WTOP_PM_PS 0x00000C54
+#define GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C58
+
+#define GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C5C
+
+#define GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C60
+
+#define GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C64
+
+#define GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C68
+
+#define GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C6C
+
+#define GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG \
+ 0x00000C70
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG0 \
+ 0x00000C78
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG1 \
+ 0x00000C7C
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG2 \
+ 0x00000C80
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG3 \
+ 0x00000C84
+
+#define GPRCM_O_WTOP_MEM_RET_CFG \
+ 0x00000C88
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG0 \
+ 0x00000C8C
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG1 \
+ 0x00000C90
+
+#define GPRCM_O_COEX_CLK_SWALLOW_CFG2 \
+ 0x00000C94
+
+#define GPRCM_O_COEX_CLK_SWALLOW_ENABLE \
+ 0x00000C98
+
+#define GPRCM_O_DCDC_CLK_GEN_CONFIG \
+ 0x00000C9C
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG4 \
+ 0x00000CA0
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG5 \
+ 0x00000CA4
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG6 \
+ 0x00000CA8
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG7 \
+ 0x00000CAC
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG8 \
+ 0x00000CB0
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG9 \
+ 0x00000CB4
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG10 \
+ 0x00000CB8
+
+#define GPRCM_O_GPRCM_EFUSE_READ_REG11 \
+ 0x00000CBC
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG0 \
+ 0x00000CC0
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG1 \
+ 0x00000CC4
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG2 \
+ 0x00000CC8
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG3 \
+ 0x00000CCC
+
+#define GPRCM_O_GPRCM_DIEID_READ_REG4 \
+ 0x00000CD0
+
+#define GPRCM_O_APPS_SS_OVERRIDES \
+ 0x00000CD4
+
+#define GPRCM_O_NWP_SS_OVERRIDES \
+ 0x00000CD8
+
+#define GPRCM_O_SHARED_SS_OVERRIDES \
+ 0x00000CDC
+
+#define GPRCM_O_IDMEM_CORE_RST_OVERRIDES \
+ 0x00000CE0
+
+#define GPRCM_O_TOP_DIE_FSM_OVERRIDES \
+ 0x00000CE4
+
+#define GPRCM_O_MCU_PSCON_OVERRIDES \
+ 0x00000CE8
+
+#define GPRCM_O_WTOP_PSCON_OVERRIDES \
+ 0x00000CEC
+
+#define GPRCM_O_WELP_PSCON_OVERRIDES \
+ 0x00000CF0
+
+#define GPRCM_O_WL_SDIO_PSCON_OVERRIDES \
+ 0x00000CF4
+
+#define GPRCM_O_MCSPI_PSCON_OVERRIDES \
+ 0x00000CF8
+
+#define GPRCM_O_SSDIO_PSCON_OVERRIDES \
+ 0x00000CFC
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET1 \
+ 0x00000002 // Soft-reset1 for APPS : Cortex
+ // sysrstn is asserted and in
+ // addition to that the associated
+ // APPS Peripherals are also reset.
+ // This is an auto-clear bit.
+
+#define GPRCM_APPS_SOFT_RESET_APPS_SOFT_RESET0 \
+ 0x00000001 // Soft-reset0 for APPS : Only
+ // sys-resetn for Cortex will be
+ // asserted. This is an auto-clear
+ // bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKEUP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_M \
+ 0x000000FF // Mask for LPDS Wakeup interrupt :
+ // [7] - Host IRQ from NWP [6] -
+ // NWP_LPDS_Wake_irq (TRUE_LPDS) [5]
+ // - NWP Wake-request to APPS [4] -
+ // GPIO [3:1] - Reserved [0] - LPDS
+ // Wakeup-timer
+
+#define GPRCM_APPS_LPDS_WAKEUP_CFG_APPS_LPDS_WAKEUP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKEUP_SRC register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_M \
+ 0x000000FF // Indicates the cause for wakeup
+ // from LPDS : [7] - Host IRQ from
+ // NWP [6] - NWP_LPDS_Wake_irq
+ // (TRUE_LPDS) [5] - NWP
+ // Wake-request to APPS [4] - GPIO
+ // [3:1] - Reserved [0] - LPDS
+ // Wakeup-timer
+
+#define GPRCM_APPS_LPDS_WAKEUP_SRC_APPS_LPDS_WAKEUP_SRC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_RESET_CAUSE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_M \
+ 0x000000FF // Indicates the reset cause for
+ // APPS : "0000" - Wake from HIB/OFF
+ // mode; "0001" - Wake from LPDS ;
+ // "0010" - Reserved ; "0011" -
+ // Soft-reset0 (Only APPS
+ // Cortex-sysrstn is asserted);
+ // "0100" - Soft-reset1 (APPS
+ // Cortex-sysrstn and APPS
+ // peripherals are reset); "0101" -
+ // WDOG0 (APPS Cortex-sysrstn and
+ // APPS peripherals are reset);
+ // "0110" - MCU Soft-reset (APPS +
+ // NWP Cortex-sysrstn + Peripherals
+ // are reset); "0111" - Secure Init
+ // done (Indication that reset has
+ // happened after DevInit); "1000" -
+ // Dev Mode Patch Init done (During
+ // development mode, patch
+ // downloading and Cortex
+ // re-vectoring is completed)
+
+#define GPRCM_APPS_RESET_CAUSE_APPS_RESET_CAUSE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKETIME_OPP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_M \
+ 0xFFFFFFFF // OPP Request Configuration
+ // (Number of slow-clk cycles) for
+ // LPDS Wake-timer : This
+ // configuration implies the RTC
+ // time-stamp, which must be few
+ // slow-clks prior to
+ // APPS_LPDS_WAKETIME_WAKE_CFG, such
+ // that by the time actual wakeup is
+ // given, OPP is already switched to
+ // ACTIVE (RUN).
+
+#define GPRCM_APPS_LPDS_WAKETIME_OPP_CFG_APPS_LPDS_WAKETIME_OPP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SRAM_DSLP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_M \
+ 0x000FFFFF // Configuration of APPS Memories
+ // during Deep-sleep : 0 - SRAMs are
+ // OFF ; 1 - SRAMs are Retained.
+ // APPS SRAM Cluster information :
+ // [0] - 1st column in MEMSS
+ // (Applicable only when owned by
+ // APPS); [1] - 2nd column in MEMSS
+ // (Applicable only when owned by
+ // APPS); [2] - 3rd column in MEMSS
+ // (Applicable only when owned by
+ // APPS) ; [3] - 4th column in MEMSS
+ // (Applicable only when owned by
+ // APPS) ; [16] - MCU-PD - Apps
+ // cluster 0 (TBD); [19:18] -
+ // Reserved.
+
+#define GPRCM_APPS_SRAM_DSLP_CFG_APPS_SRAM_DSLP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SRAM_LPDS_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_M \
+ 0x000FFFFF // Configuration of APPS Memories
+ // during LPDS : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. APPS SRAM
+ // Cluster information : [0] - 1st
+ // column in MEMSS (Applicable only
+ // when owned by APPS); [1] - 2nd
+ // column in MEMSS (Applicable only
+ // when owned by APPS); [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by APPS) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by APPS) ; [16] -
+ // MCU-PD - Apps cluster 0 (TBD);
+ // [19:18] - Reserved.
+
+#define GPRCM_APPS_SRAM_LPDS_CFG_APPS_SRAM_LPDS_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_LPDS_WAKETIME_WAKE_CFG register.
+//
+//******************************************************************************
+#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_M \
+ 0xFFFFFFFF // Configuration (in no of
+ // slow_clks) which says when the
+ // actual wakeup request for
+ // removing the PD-reset be given.
+
+#define GPRCM_APPS_LPDS_WAKETIME_WAKE_CFG_APPS_LPDS_WAKETIME_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_ENABLE register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_ENABLE_FLASH_BUSY \
+ 0x00001000
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_M \
+ 0x00000F00
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_PWR_PS_S 8
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE_STATUS \
+ 0x00000002 // 1 - Top-die is enabled ;
+
+#define GPRCM_TOP_DIE_ENABLE_TOP_DIE_ENABLE \
+ 0x00000001 // 1 - Enable the top-die ; 0 -
+ // Disable the top-die
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_ENABLE_PARAMETERS register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_M \
+ 0xF0000000 // Configuration (in slow_clks) for
+ // number of clks between
+ // Flash-3p3-rstn to D2D POR Resetn.
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_FLASH_3P3_RSTN2D2D_POR_RSTN_S 28
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_M \
+ 0x00FF0000 // Configuration (in slow_clks) for
+ // number of clks between Top-die
+ // Switch-Enable and Top-die Flash
+ // 3p3 Reset removal
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_SW_EN2TOP_DIE_FLASH_3P3_RSTN_S 16
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_M \
+ 0x000000FF // Configuration (in slow_clks) for
+ // number of clks between D2D POR
+ // Reset removal and bottom die FMC
+ // reset removal
+
+#define GPRCM_TOP_DIE_ENABLE_PARAMETERS_TOP_DIE_POR_RSTN2BOTT_DIE_FMC_RSTN_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_GLOBAL_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_MCU_GLOBAL_SOFT_RESET_MCU_GLOBAL_SOFT_RESET \
+ 0x00000001 // 1 - Assert the global reset for
+ // MCU (APPS + NWP) ; Asserts both
+ // Cortex sysrstn and its
+ // peripherals 0 - Deassert the
+ // global reset for MCU (APPS + NWP)
+ // ; Asserts both Cortex sysrstn and
+ // its peripherals Note : Reset for
+ // shared peripherals is not
+ // affected here.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_ADC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_M \
+ 0x000007C0 // Configuration (in number of 38.4
+ // MHz clks) for the OFF-Time in
+ // generation of ADC_CLK
+
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_OFF_TIME_S 6
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_M \
+ 0x0000003E // Configuration (in number of 38.4
+ // MHz clks) for the ON-Time in
+ // generation of ADC_CLK
+
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLKGEN_ON_TIME_S 1
+#define GPRCM_ADC_CLK_CONFIG_ADC_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the ADC_CLK ; 0 -
+ // Disable the ADC_CLK
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_M \
+ 0x00000003 // "00" - Wake on Level0 on
+ // selected GPIO pin (GPIO is
+ // selected inside the HIB3p3
+ // module); "01" - Wakeup on
+ // fall-edge of GPIO pin.
+
+#define GPRCM_APPS_GPIO_WAKE_CONF_APPS_GPIO_WAKE_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_EN_NWP_BOOT_WO_DEVINIT register.
+//
+//******************************************************************************
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_M \
+ 0xFFFFFFFE
+
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_reserved_S 1
+#define GPRCM_EN_NWP_BOOT_WO_DEVINIT_mem_en_nwp_boot_wo_devinit \
+ 0x00000001 // 1 - Override the secure-mode
+ // done for booting up NWP (Wakeup
+ // NWP on its event independent of
+ // CM4 state) ; 0 - Donot override
+ // the secure-mode done for NWP boot
+ // (NWP must be enabled by CM4 only)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_HCLK_DIV_CFG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_M \
+ 0x00000007 // Division configuration for
+ // HCLKDIVOUT : "000" - Divide by 1
+ // ; "001" - Divide by 2 ; "010" -
+ // Divide by 3 ; "011" - Divide by 4
+ // ; "100" - Divide by 5 ; "101" -
+ // Divide by 6 ; "110" - Divide by 7
+ // ; "111" - Divide by 8
+
+#define GPRCM_MEM_HCLK_DIV_CFG_mem_hclk_div_cfg_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SYSCLK_DIV_CFG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_M \
+ 0x00000038
+
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_off_time_S 3
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_M \
+ 0x00000007
+
+#define GPRCM_MEM_SYSCLK_DIV_CFG_mem_sysclk_div_on_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_LOCK_TIME_CONF register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_M \
+ 0x0000FF00
+
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_wlan_lock_time_S 8
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_M \
+ 0x000000FF
+
+#define GPRCM_APLLMCS_LOCK_TIME_CONF_mem_apllmcs_mcu_lock_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SOFT_RESET register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET1 \
+ 0x00000002 // Soft-reset1 for NWP - Cortex
+ // sysrstn and NWP associated
+ // peripherals are - This is an
+ // auto-clr bit.
+
+#define GPRCM_NWP_SOFT_RESET_NWP_SOFT_RESET0 \
+ 0x00000001 // Soft-reset0 for NWP - Only
+ // Cortex-sysrstn is asserted - This
+ // is an auto-clear bit.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKEUP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_M \
+ 0x000000FF // Mask for LPDS Wakeup interrupt :
+ // 7 - WLAN Host Interrupt ; 6 -
+ // WLAN to NWP Wake request ; 5 -
+ // APPS to NWP Wake request; 4 -
+ // GPIO Wakeup ; 3 - Autonomous UART
+ // Wakeup ; 2 - SSDIO Wakeup ; 1 -
+ // Autonomous SPI Wakeup ; 0 - LPDS
+ // Wakeup-timer
+
+#define GPRCM_NWP_LPDS_WAKEUP_CFG_NWP_LPDS_WAKEUP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKEUP_SRC register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_M \
+ 0x000000FF // Indicates the cause for NWP
+ // LPDS-Wakeup : 7 - WLAN Host
+ // Interrupt ; 6 - WLAN to NWP Wake
+ // request ; 5 - APPS to NWP Wake
+ // request; 4 - GPIO Wakeup ; 3 -
+ // Autonomous UART Wakeup ; 2 -
+ // SSDIO Wakeup ; 1 - Autonomous SPI
+ // Wakeup ; 0 - LPDS Wakeup-timer
+
+#define GPRCM_NWP_LPDS_WAKEUP_SRC_NWP_LPDS_WAKEUP_SRC_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_RESET_CAUSE register.
+//
+//******************************************************************************
+#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_M \
+ 0x000000FF // Indicates the reset cause for
+ // NWP : "0000" - Wake from HIB/OFF
+ // mode; "0001" - Wake from LPDS ;
+ // "0010" - Reserved ; "0011" -
+ // Soft-reset0 (Only NWP
+ // Cortex-sysrstn is asserted);
+ // "0100" - Soft-reset1 (NWP
+ // Cortex-sysrstn and NWP
+ // peripherals are reset); "0101" -
+ // WDOG0 (NWP Cortex-sysrstn and NWP
+ // peripherals are reset); "0110" -
+ // MCU Soft-reset (APPS + NWP
+ // Cortex-sysrstn + Peripherals are
+ // reset); "0111" - SSDIO Function2
+ // reset (Only Cortex-sysrstn is
+ // asserted) ; "1000" - Reset due to
+ // WDOG of APPS (NWP Cortex-sysrstn
+ // and NWP peripherals are reset);
+
+#define GPRCM_NWP_RESET_CAUSE_NWP_RESET_CAUSE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKETIME_OPP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_M \
+ 0xFFFFFFFF // OPP Request Configuration
+ // (Number of slow-clk cycles) for
+ // LPDS Wake-timer
+
+#define GPRCM_NWP_LPDS_WAKETIME_OPP_CFG_NWP_LPDS_WAKETIME_OPP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SRAM_DSLP_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_M \
+ 0x000FFFFF // Configuration of NWP Memories
+ // during DSLP : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. NWP SRAM
+ // Cluster information : [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [4] - 5th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [5] - 6th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [6] - 7th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [7] - 8th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [8] - 9th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [9] - 10th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [10] - 11th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [11] - 12th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [12] - 13th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [13] - 14th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [14] - 15th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [19:18] -
+ // Reserved.
+
+#define GPRCM_NWP_SRAM_DSLP_CFG_NWP_SRAM_DSLP_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SRAM_LPDS_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_M \
+ 0x000FFFFF // Configuration of NWP Memories
+ // during LPDS : 0 - SRAMs are OFF ;
+ // 1 - SRAMs are Retained. NWP SRAM
+ // Cluster information : [2] - 3rd
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [3] - 4th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [4] - 5th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [5] - 6th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [6] - 7th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [7] - 8th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [8] - 9th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [9] - 10th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [10] - 11th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [11] - 12th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [12] - 13th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [13] - 14th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [14] - 15th
+ // column in MEMSS (Applicable only
+ // when owned by NWP) ; [19:18] -
+ // Reserved.
+
+#define GPRCM_NWP_SRAM_LPDS_CFG_NWP_SRAM_LPDS_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_LPDS_WAKETIME_WAKE_CFG register.
+//
+//******************************************************************************
+#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_M \
+ 0xFFFFFFFF // Wake time configuration (no of
+ // slow clks) for NWP wake from
+ // LPDS.
+
+#define GPRCM_NWP_LPDS_WAKETIME_WAKE_CFG_NWP_LPDS_WAKETIME_WAKE_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_AUTONMS_SPI_MASTER_SEL register.
+//
+//******************************************************************************
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_M \
+ 0xFFFE0000
+
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_F_S 17
+#define GPRCM_NWP_AUTONMS_SPI_MASTER_SEL_MEM_AUTONMS_SPI_MASTER_SEL \
+ 0x00010000 // 0 - APPS is selected as host for
+ // Autonms SPI ; 1 - External host
+ // is selected as host for Autonms
+ // SPI
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_AUTONMS_SPI_IDLE_REQ register.
+//
+//******************************************************************************
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_WAKEUP \
+ 0x00010000
+
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_ACK \
+ 0x00000002 // When 1 => IDLE-mode is
+ // acknowledged by the SPI-IP. (This
+ // is for MCSPI_N1)
+
+#define GPRCM_NWP_AUTONMS_SPI_IDLE_REQ_NWP_AUTONMS_SPI_IDLE_REQ \
+ 0x00000001 // When 1 => Request for IDLE-mode
+ // for autonomous SPI. (This is for
+ // MCSPI_N1)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_TO_NWP_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_TO_NWP_WAKE_REQUEST_WLAN_TO_NWP_WAKE_REQUEST \
+ 0x00000001 // 1 - Request for waking up NWP
+ // from any of its low-power modes
+ // (SLP/DSLP/LPDS)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_TO_WLAN_WAKE_REQUEST register.
+//
+//******************************************************************************
+#define GPRCM_NWP_TO_WLAN_WAKE_REQUEST_NWP_TO_WLAN_WAKE_REQUEST \
+ 0x00000001 // 1 - Request for wakinp up WLAN
+ // from its ELP Mode (This gets
+ // triggered to ELP-logic of WLAN)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_M \
+ 0x00000003 // "00" - Wakeup on level0 of the
+ // selected GPIO (GPIO gets selected
+ // inside HIB3P3-module); "01" -
+ // Wakeup on fall-edge of selected
+ // GPIO.
+
+#define GPRCM_NWP_GPIO_WAKE_CONF_NWP_GPIO_WAKE_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG12 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_M \
+ 0x0000FFFF // This corrsponds to ROW_32
+ // [31:16] of the FUSEFARM. SPARE
+
+#define GPRCM_GPRCM_EFUSE_READ_REG12_FUSEFARM_ROW_32_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG5 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_M \
+ 0xFFFFFFFF // Corresponds to ROW10 of FUSEFARM
+ // : [5:0] - ADC OFFSET ; [13:6] -
+ // TEMP_SENSE ; [14:14] - DFT_GSG ;
+ // [15:15] - FMC_DISABLE ; [31:16] -
+ // WLAN_MAC ID
+
+#define GPRCM_GPRCM_DIEID_READ_REG5_FUSEFARM_ROW_10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG6 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_M \
+ 0xFFFFFFFF // Corresponds to ROW11 of FUSEFARM
+ // : [31:0] : WLAN MAC ID
+
+#define GPRCM_GPRCM_DIEID_READ_REG6_FUSEFARM_ROW_11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_CFG0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_M \
+ 0x00FF0000 // ANA-BGAP Settling time (In
+ // number of slow_clks)
+
+#define GPRCM_REF_FSM_CFG0_BGAP_SETTLING_TIME_S 16
+#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_M \
+ 0x0000FF00 // Slicer LDO settling time (In
+ // number of slow clks)
+
+#define GPRCM_REF_FSM_CFG0_FREF_LDO_SETTLING_TIME_S 8
+#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_M \
+ 0x000000FF // Dig-buffer settling time (In
+ // number of slow clks)
+
+#define GPRCM_REF_FSM_CFG0_DIG_BUF_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_CFG1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_M \
+ 0xFF000000 // XTAL settling time (In number of
+ // slow clks)
+
+#define GPRCM_REF_FSM_CFG1_XTAL_SETTLING_TIME_S 24
+#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_M \
+ 0x00FF0000 // LV Slicer settling time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_LV_SETTLING_TIME_S 16
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_M \
+ 0x0000FF00 // HV Slicer Pull-down settling
+ // time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_PD_SETTLING_TIME_S 8
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_M \
+ 0x000000FF // HV Slicer settling time
+
+#define GPRCM_REF_FSM_CFG1_SLICER_HV_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG0_40 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_M \
+ 0x00007F00 // Configuration for WLAN APLLMCS -
+ // N[6:0], if the XTAL frequency is
+ // 40 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_N_40_S 8
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_M \
+ 0x000000FF // Configuration for WLAN APLLMCS -
+ // M[7:0], if the XTAL frequency is
+ // 40 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_40_APLLMCS_WLAN_M_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG1_40 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_HISPEED_40 \
+ 0x00000010 // Configuration for WLAN APLLMCS -
+ // if the XTAL frequency if 40 MHz
+ // (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SEL96_40 \
+ 0x00000008 // Configuration for WLAN APLLMCS -
+ // Sel96, if the XTAL frequency is
+ // 40 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_M \
+ 0x00000007 // Configuration for WLAN APLLMCS -
+ // Selinpfreq, if the XTAL frequency
+ // is 40 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_40_APLLMCS_SELINPFREQ_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG0_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_M \
+ 0x00007F00 // Configuration for WLAN APLLMCS -
+ // N[6:0], if the XTAL frequency is
+ // 26 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_N_26_S 8
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_M \
+ 0x000000FF // Configuration for WLAN APLLMCS -
+ // M[7:0], if the XTAL frequency is
+ // 26 MHz (Selected by efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG0_26_APLLMCS_WLAN_M_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_CONFIG1_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_HISPEED_26 \
+ 0x00000010 // Configuration for WLAN APLLMCS -
+ // if the XTAL frequency if 26 MHz
+ // (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SEL96_26 \
+ 0x00000008 // Configuration for WLAN APLLMCS -
+ // Sel96, if the XTAL frequency is
+ // 26 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_M \
+ 0x00000007 // Configuration for WLAN APLLMCS -
+ // Selinpfreq, if the XTAL frequency
+ // is 26 MHz (Selected by Efuse)
+
+#define GPRCM_APLLMCS_WLAN_CONFIG1_26_APLLMCS_SELINPFREQ_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_WLAN_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_CTRL \
+ 0x00080000
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_M \
+ 0x00070000
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_POSTDIV_OVERRIDE_S 16
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_M \
+ 0x00000700
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_SPARE_S 8
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE_CTRL \
+ 0x00000020 // Override control for
+ // WLAN_APLLMCS_M[8]. When set to1,
+ // M[8] will be selected by bit [3].
+ // (Else controlled from WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_M_8_OVERRIDE \
+ 0x00000010 // Override for WLAN_APLLMCS_M[8].
+ // Applicable only when bit [4] is
+ // set to 1. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_CTRL \
+ 0x00000004 // Override control for
+ // WLAN_APLLMCS_N[8:7]. When set
+ // to1, N[8:7] will be selected by
+ // bits [2:1]. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_M \
+ 0x00000003 // Override value for
+ // WLAN_APLLMCS_N[8:7] bits.
+ // Applicable only when bit [1] is
+ // set to 1. (Else controlled from
+ // WTOP)
+
+#define GPRCM_APLLMCS_WLAN_OVERRIDES_APLLMCS_WLAN_N_7_8_OVERRIDE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_38P4 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_M \
+ 0x38000000
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_POSTDIV_S 27
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_M \
+ 0x07000000
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_SPARE_S 24
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_M \
+ 0x007F0000 // Configuration for MCU-APLLMCS :
+ // N during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_38P4_S 16
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_M \
+ 0x0000FF00 // Configuration for MCU-APLLMCS :
+ // M during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_38P4_S 8
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_M_8_38P4 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // M[8] during RUN mode. Selected if
+ // the XTAL frequency is 38.4 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_M \
+ 0x00000003 // Configuration for MCU-APLLMCS :
+ // N[8:7] during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_38P4_APLLMCS_MCU_RUN_N_7_8_38P4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_38P4 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_HISPEED_38P4 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // HISPEED during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SEL96_38P4 \
+ 0x00000008 // Configuration for MCU-APLLMCS :
+ // SEL96 during RUN mode. Selected
+ // if the XTAL frequency is 38.4 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_M \
+ 0x00000007 // Configuration for MCU-APLLMCS :
+ // SELINPFREQ during RUN mode.
+ // Selected if the XTAL frequency is
+ // 38.4 MHz (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_38P4_APLLMCS_MCU_RUN_SELINPFREQ_38P4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG0_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_M \
+ 0x007F0000 // Configuration for MCU-APLLMCS :
+ // N during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_26_S 16
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_M \
+ 0x0000FF00 // Configuration for MCU-APLLMCS :
+ // M during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_26_S 8
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_M_8_26 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // M[8] during RUN mode. Selected if
+ // the XTAL frequency is 26 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_M \
+ 0x00000003 // Configuration for MCU-APLLMCS :
+ // N[8:7] during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (From Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG0_26_APLLMCS_MCU_RUN_N_7_8_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_RUN_CONFIG1_26 register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_HISPEED_26 \
+ 0x00000010 // Configuration for MCU-APLLMCS :
+ // HISPEED during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SEL96_26 \
+ 0x00000008 // Configuration for MCU-APLLMCS :
+ // SEL96 during RUN mode. Selected
+ // if the XTAL frequency is 26 MHz
+ // (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_M \
+ 0x00000007 // Configuration for MCU-APLLMCS :
+ // SELINPFREQ during RUN mode.
+ // Selected if the XTAL frequency is
+ // 26 MHz (from Efuse)
+
+#define GPRCM_APLLMCS_MCU_RUN_CONFIG1_26_APLLMCS_MCU_RUN_SELINPFREQ_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPRCM_O_SPARE_RW0 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the GPRCM_O_SPARE_RW1 register.
+//
+//******************************************************************************
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APLLMCS_MCU_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_LOCK \
+ 0x00000400 // 1 - APLLMCS_MCU is locked ; 0 -
+ // APLLMCS_MCU is not locked
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE \
+ 0x00000200 // Override for APLLMCS_MCU Enable.
+ // Applicable if bit [8] is set
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_APLLMCS_MCU_ENABLE_OVERRIDE_CTRL \
+ 0x00000100 // 1 - Enable for APLLMCS_MCU comes
+ // from bit [9]. 0 - Enable for
+ // APLLMCS_MCU comes from FSM.
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_M \
+ 0x00000006 // Override for sysclk src
+ // (applicable only if bit [0] is
+ // set to 1. "00"- SLOW_CLK "01"-
+ // XTAL_CLK "10"- PLL_CLK
+
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_S 1
+#define GPRCM_APLLMCS_MCU_OVERRIDES_SYSCLK_SRC_OVERRIDE_CTRL \
+ 0x00000001 // 1 - Sysclk src is selected from
+ // bits [2:1] of this register. 0 -
+ // Sysclk src is selected from FSM
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SYSCLK_SWITCH_STATUS register.
+//
+//******************************************************************************
+#define GPRCM_SYSCLK_SWITCH_STATUS_SYSCLK_SWITCH_STATUS \
+ 0x00000001 // 1 - Sysclk switching is
+ // complete. 0 - Sysclk switching is
+ // in progress.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_LDO_CONTROLS register.
+//
+//******************************************************************************
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE_OVERRIDE_CTRL \
+ 0x00010000 // 1 - Enable for REF_LDO comes
+ // from bit [0] of this register ; 0
+ // - Enable for REF_LDO comes from
+ // the FSM. Note : Final REF_LDO_EN
+ // reaches on the port
+ // TOP_PM_REG2[0] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_M \
+ 0x0000C000 // Spare bits for REF_CTRL_FSM.
+ // Reaches directly on port
+ // TOP_PM_REG2[15:14] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_SPARE_CONTROL_S 14
+#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_M \
+ 0x00003800 // REF TLOAD Enable. Reaches
+ // directly on port
+ // TOP_PM_REG2[13:11] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_TLOAD_ENABLE_S 11
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_M \
+ 0x00000700 // REF_LDO Test-mux control.
+ // Reaches directly on port
+ // TOP_PM_REG2[10:8] of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_TMUX_CONTROL_S 8
+#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_M \
+ 0x000000C0 // REF BW Control. Reaches directly
+ // on port TOP_PM_REG2[7:6] of
+ // gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_BW_CONTROL_S 6
+#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_M \
+ 0x0000003C // REF VTRIM Control. Reaches
+ // directly on port TOP_PM_REG2[5:2]
+ // of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_VTRIM_CONTROL_S 2
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_BYPASS_ENABLE \
+ 0x00000002 // REF LDO Bypass Enable. Reaches
+ // directly on port TOP_PM_REG2[1]
+ // of gprcm.
+
+#define GPRCM_REF_LDO_CONTROLS_REF_LDO_ENABLE \
+ 0x00000001 // Override for REF_LDO Enable.
+ // Applicable only if bit [16] of
+ // this register is set. Note :
+ // Final REF_LDO_EN reaches on the
+ // port TOP_PM_REG2[0] of gprcm.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_RTRIM_CONTROL register.
+//
+//******************************************************************************
+#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_M \
+ 0x18000000 // This is [5:4] bits of
+ // TOP_PM_REG0
+
+#define GPRCM_REF_RTRIM_CONTROL_TOP_PM_REG0_5_4_S 27
+#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_M \
+ 0x07FF0000 // This is [15:5] bits of
+ // TOP_CLKM_REG0
+
+#define GPRCM_REF_RTRIM_CONTROL_TOP_CLKM_REG0_15_5_S 16
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_OVERRIDE_CTRL \
+ 0x00000100 // 1 - CLKM_RTRIM comes for
+ // bits[4:0] of this register. 0 -
+ // CLKM_RTRIM comes from Efuse
+ // (after efuse_done = 1).
+
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_M \
+ 0x0000001F // CLKM_TRIM Override. Applicable
+ // when efuse_done = 0 or bit[8] is
+ // set to 1.
+
+#define GPRCM_REF_RTRIM_CONTROL_REF_CLKM_RTRIM_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_SLICER_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV_OVERRIDE_CTRL \
+ 0x00200000 // 1 - EN_DIG_BUF_TOP comes from
+ // bit [14] of this register. 0 -
+ // EN_DIG_BUF_TOP comes from the
+ // FSM. Note : Final EN_DIG_BUF_WLAN
+ // reaches on TOP_CLKM_REG1_IN[14]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV_OVERRIDE_CTRL \
+ 0x00100000 // 1 - EN_DIG_BUF_TOP comes from
+ // bit [15] of this register. 0 -
+ // EN_DIG_BUF_TOP comes from the
+ // FSM. Note : Final EN_DIG_BUF_TOP
+ // reaches on TOP_CLKM_REG1_IN[15]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL_OVERRIDE_CTRL \
+ 0x00080000 // 1 - EN_XTAL comes from bit [3]
+ // of this register. 0 - EN_XTAL
+ // comes from FSM. Note : Final
+ // XTAL_EN reaches on
+ // TOP_CLKM_REG1_IN[3] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_OVERRIDE_CTRL \
+ 0x00040000 // 1 - Enable HV Slicer comes from
+ // bit [2] of this register. 0 -
+ // Enable HV Slicer comes from FSM.
+ // Note : Final HV_SLICER_EN reaches
+ // on port TOP_CLKM_REG1_IN[1] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_LV_OVERRIDE_CTRL \
+ 0x00020000 // 1 - Enable LV Slicer comes from
+ // bit[1] of this register. 0 -
+ // Enable LV Slicer comes from FSM.
+ // Note : final LV_SLICER_EN reaches
+ // on port TOP_CLKM_REG1_IN[2] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLI_HV_PDN_OVERRIDE_CTRL \
+ 0x00010000 // 1 - Enable HV Pull-down comes
+ // from bit[0] of this register. 0 -
+ // Enable HV Pull-down comes from
+ // FSM. Note : Final HV_PULL_DOWN
+ // reaches on port
+ // TOP_CLKM_REG1_IN[0] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_TOP_LOWV \
+ 0x00008000 // Override for EN_DIG_BUF_TOP.
+ // Applicable if bit[20] is set to
+ // 1. Note : Final EN_DIG_BUF_TOP
+ // reaches on TOP_CLKM_REG1_IN[15]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLK_EN_WLAN_LOWV \
+ 0x00004000 // Override for EN_DIG_BUF_WLAN.
+ // Applicable if bit[19] is set to
+ // 1. Note : Final EN_DIG_BUF_WLAN
+ // reaches on TOP_CLKM_REG1_IN[14]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CLKOUT_FLIP_EN \
+ 0x00002000 // CLKOUT Flip Enable. Reaches on
+ // bit[13] of TOP_CLKM_REG1_IN[13]
+ // port of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV2_WLAN_CLK \
+ 0x00001000 // Enable divide2 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[12]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV3_WLAN_CLK \
+ 0x00000800 // Enable divide3 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[11]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_DIV4_WLAN_CLK \
+ 0x00000400 // Enable divide4 in WLAN Clk-path.
+ // Reaches on TOP_CLKM_REG1_IN[10]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_M \
+ 0x000003C0 // CM Test-mux select. Reaches on
+ // TOP_CLMM_REG1_IN[9:6] port of
+ // gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_CM_TMUX_SEL_LOWV_S 6
+#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_M \
+ 0x00000030 // Slicer spare0 control. Reaches
+ // on TOP_CLKM_REG1_IN[5:4] port of
+ // gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_SLICER_SPARE0_S 4
+#define GPRCM_REF_SLICER_CONTROLS0_EN_XTAL \
+ 0x00000008 // Enable XTAL override. Reaches on
+ // TOP_CLKM_REG1_IN[3] port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV \
+ 0x00000004 // Enable HV Slicer override.
+ // Reaches on TOP_CLKM_REG1_IN[1]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_LV \
+ 0x00000002 // Enable LV Slicer override.
+ // Reaches on TOP_CLKM_REG1_IN[2]
+ // port of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS0_EN_SLICER_HV_PDN \
+ 0x00000001 // Enable HV Pull-down override.
+ // Reaches on TOP_CLKM_REG1_IN[0]
+ // port of gprcm
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_SLICER_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_M \
+ 0x0000FC00 // Slicer spare1. Reaches on port
+ // TOP_CLKM_REG2_IN[15:10] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_SPARE1_S 10
+#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_M \
+ 0x000003F0 // XOSC Trim. Reaches on port
+ // TOP_CLKM_REG2_IN[9:4] of gprcm
+
+#define GPRCM_REF_SLICER_CONTROLS1_XOSC_TRIM_S 4
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_ITRIM_CHANGE_TOGGLE \
+ 0x00000008 // Slicer ITRIM Toggle. Reaches on
+ // port TOP_CLKM_REG2_IN[3] of
+ // gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_M \
+ 0x00000007 // LV Slicer trim. Reaches on port
+ // TOP_CLKM_REG2_IN[2:0] of gprcm.
+
+#define GPRCM_REF_SLICER_CONTROLS1_SLICER_LV_TRIM_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_BGAP_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_M \
+ 0xFF800000
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_reserved_S 23
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_mag_trim_override_ctrl \
+ 0x00400000 // 1 - REF_MAG_TRIM comes from
+ // bit[4:0] of register
+ // REF_ANA_BGAP_CONTROLS1 [Addr :
+ // 0x0850]; 0 - REF_MAG_TRIM comes
+ // from efuse (After efc_done = 1).
+ // Note : Final REF_MAG_TRIM reaches
+ // on port TOP_PM_REG1[4:0] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_override_ctrl \
+ 0x00200000 // 1 - REF_V2I_TRIM comes from
+ // bit[9:6] of this register ; 0 -
+ // REF_V2I_TRIM comes from efuse
+ // (After efc_done = 1). Note :
+ // Final REF_V2I_TRIM reaches on
+ // port TOP_PM_REG0[9:6] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_override_ctrl \
+ 0x00100000 // 1 - REF_TEMP_TRIM comes from
+ // bit[15:10] of this register ; 0 -
+ // REF_TEMP_TRIM comes from efuse
+ // (After efc_done = 1). Note :
+ // Final REF_TEMP_TRIM reaches on
+ // port TOP_PM_REG0[15:10] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en_override_ctrl \
+ 0x00080000 // 1 - REF_STARTUP_EN comes from
+ // bit [3] of this register ; 0 -
+ // REF_STARTUP_EN comes from FSM.
+ // Note : Final REF_STARTUP_EN
+ // reaches on port TOP_PM_REG0[3] of
+ // gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en_override_ctrl \
+ 0x00040000 // 1 - REF_V2I_EN comes from bit
+ // [2] of this register ; 0 -
+ // REF_V2I_EN comes from FSM. Note :
+ // Final REF_V2I_EN reaches on port
+ // TOP_PM_REG0[2] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en_override_ctrl \
+ 0x00020000 // 1 - REF_FC_EN comes from bit [1]
+ // of this register ; 0 - REF_FC_EN
+ // comes from FSM. Note : Final
+ // REF_FC_EN reaches on port
+ // TOP_PM_REG0[1] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en_override_ctrl \
+ 0x00010000 // 1 - REF_BGAP_EN comes from bit
+ // [0] of this register ; 0 -
+ // REF_BGAP_EN comes from FSM. Note
+ // : Final REF_BGAP_EN reaches on
+ // port TOP_PM_REG0[0] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_M \
+ 0x0000FC00 // REF_TEMP_TRIM override.
+ // Applicable when bit [20] of this
+ // register set to 1. (or efc_done =
+ // 0) Note : Final REF_TEMP_TRIM
+ // reaches on port
+ // TOP_PM_REG0[15:10] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_temp_trim_S 10
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_M \
+ 0x000003C0 // REF_V2I_TRIM Override.
+ // Applicable when bit [21] of this
+ // register set to 1 . (of efc_done
+ // = 0) Note : Final REF_V2I_TRIM
+ // reaches on port TOP_PM_REG0[9:6]
+ // of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_trim_S 6
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_M \
+ 0x00000030
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_NU1_S 4
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_startup_en \
+ 0x00000008 // REF_STARTUP_EN override.
+ // Applicable when bit [19] of this
+ // register is set to 1. Note :
+ // Final REF_STARTUP_EN reaches on
+ // port TOP_PM_REG0[3] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_v2i_en \
+ 0x00000004 // REF_V2I_EN override. Applicable
+ // when bit [21] of this register is
+ // set to 1. Note : Final REF_V2I_EN
+ // reaches on port TOP_PM_REG0[2] of
+ // gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_fc_en \
+ 0x00000002 // REF_FC_EN override. Applicable
+ // when bit [17] of this register is
+ // set to 1. Note : Final REF_FC_EN
+ // reaches on port TOP_PM_REG0[1] of
+ // gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS0_mem_ref_bgap_en \
+ 0x00000001 // REF_BGAP_EN override. Applicable
+ // when bit [16] of this register
+ // set to 1. Note : Final
+ // REF_BGAP_EN reaches on port
+ // TOP_PM_REG0[0] of gprcm.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_BGAP_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_M \
+ 0xFFFF0000
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_reserved_S 16
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_M \
+ 0x0000C000 // REF_BGAP_SPARE. Reaches on port
+ // TOP_PM_REG1[15:14] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bg_spare_S 14
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_M \
+ 0x00003E00 // REF_BGAP_TMUX_CTRL. Reaches on
+ // port TOP_PM_REG1[13:9] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_bgap_tmux_ctrl_S 9
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_M \
+ 0x000001E0 // REF_FILT_TRIM. Reaches on port
+ // TOP_PM_REG1[8:5] of gprcm.
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_filt_trim_S 5
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_M \
+ 0x0000001F // REF_MAG_TRIM Override.
+ // Applicable when bit[22] of
+ // REF_ANA_BGAP_CONTROLS0 [0x084C]
+ // set to 1 (of efc_done = 0). Note
+ // : Final REF_MAG_TRIM reaches on
+ // port TOP_PM_REG1[4:0] of gprcm
+
+#define GPRCM_REF_ANA_BGAP_CONTROLS1_mem_ref_mag_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_SPARE_CONTROLS0 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_M \
+ 0xFFFF0000
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_reserved_S 16
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_M \
+ 0x0000FFFF // Spare control. Reaches on
+ // TOP_PM_REG3 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS0_mem_top_pm_reg3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_ANA_SPARE_CONTROLS1 register.
+//
+//******************************************************************************
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_M \
+ 0xFFFF0000 // Spare control. Reaches on
+ // TOP_CLKM_REG3 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg3_S 16
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_M \
+ 0x0000FFFF // Spare control. Reaches on
+ // TOP_CLKM_REG4 [15:0] of gprcm.
+
+#define GPRCM_REF_ANA_SPARE_CONTROLS1_mem_top_clkm_reg4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PSCON_OVERRIDES0 register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_M \
+ 0xFFFF0000
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_off_override_S 16
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_M \
+ 0x0000FFFF
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES0_mem_memss_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PSCON_OVERRIDES1 register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_reserved_S 6
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override_ctrl \
+ 0x00000020
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_update_override \
+ 0x00000010
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override_ctrl \
+ 0x00000008
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_sleep_override \
+ 0x00000004
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memss_pscon_mem_off_override_ctrl \
+ 0x00000002
+
+#define GPRCM_MEMSS_PSCON_OVERRIDES1_mem_memms_pscon_mem_retain_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_PLL_REF_LOCK_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_reserved_S 3
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_mcu_apllmcs_lock_override \
+ 0x00000004
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_wlan_apllmcs_lock_override \
+ 0x00000002
+
+#define GPRCM_PLL_REF_LOCK_OVERRIDES_mem_ref_clk_valid_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PSCON_DEBUG register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PSCON_DEBUG_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_MCU_PSCON_DEBUG_reserved_S 6
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_M \
+ 0x00000038 // MCU_PSCON_RTC_ON = "0000";
+ // MCU_PSCON_RTC_OFF = "0001";
+ // MCU_PSCON_RTC_RET = "0010";
+ // MCU_PSCON_RTC_OFF_TO_ON = "0011";
+ // MCU_PSCON_RTC_RET_TO_ON = "0100";
+ // MCU_PSCON_RTC_ON_TO_RET = "0101";
+ // MCU_PSCON_RTC_ON_TO_OFF = "0110";
+ // MCU_PSCON_RTC_RET_TO_ON_WAIT_OPP
+ // = "0111";
+ // MCU_PSCON_RTC_OFF_TO_ON_WAIT_OPP
+ // = "1000";
+
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_rtc_ps_S 3
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_M \
+ 0x00000007
+
+#define GPRCM_MCU_PSCON_DEBUG_mcu_pscon_sys_ps_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEMSS_PWR_PS register.
+//
+//******************************************************************************
+#define GPRCM_MEMSS_PWR_PS_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_MEMSS_PWR_PS_reserved_S 3
+#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_M \
+ 0x00000007 // MEMSS_PM_SLEEP = "000";
+ // MEMSS_PM_WAIT_OPP = "010";
+ // MEMSS_PM_ACTIVE = "011";
+ // MEMSS_PM_SLEEP_TO_ACTIVE = "100";
+ // MEMSS_PM_ACTIVE_TO_SLEEP = "101";
+
+#define GPRCM_MEMSS_PWR_PS_pwr_ps_memss_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_REF_FSM_DEBUG register.
+//
+//******************************************************************************
+#define GPRCM_REF_FSM_DEBUG_reserved_M \
+ 0xFFFFFFC0
+
+#define GPRCM_REF_FSM_DEBUG_reserved_S 6
+#define GPRCM_REF_FSM_DEBUG_fref_mode_M \
+ 0x00000030 // 01 - HV Mode ; 10 - LV Mode ; 11
+ // - XTAL Mode
+
+#define GPRCM_REF_FSM_DEBUG_fref_mode_S 4
+#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_M \
+ 0x0000000F // constant FREF_CLK_OFF = "00000";
+ // constant FREF_EN_BGAP = "00001";
+ // constant FREF_EN_LDO = "00010";
+ // constant FREF_EN_SLI_HV =
+ // "00011"; constant
+ // FREF_EN_SLI_HV_PD = "00100";
+ // constant FREF_EN_DIG_BUF =
+ // "00101"; constant FREF_EN_OSC =
+ // "00110"; constant FREF_EN_SLI_LV
+ // = "00111"; constant
+ // FREF_EN_CLK_REQ = "01000";
+ // constant FREF_CLK_VALID =
+ // "01001"; constant FREF_MODE_DET0
+ // = "01010"; constant
+ // FREF_MODE_DET1 = "01011";
+ // constant FREF_MODE_DET2 =
+ // "10010"; constant FREF_MODE_DET3
+ // = "10011"; constant FREF_VALID =
+ // "01100"; constant FREF_VALID0 =
+ // "01101"; constant FREF_VALID1 =
+ // "01110"; constant FREF_VALID2 =
+ // "01111"; constant
+ // FREF_WAIT_EXT_TCXO0 = "10000";
+ // constant FREF_WAIT_EXT_TCXO1 =
+ // "10001";
+
+#define GPRCM_REF_FSM_DEBUG_ref_fsm_ps_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SYS_OPP_REQ_OVERRIDE register.
+//
+//******************************************************************************
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_M \
+ 0xFFFFFFE0
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_reserved_S 5
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_ctrl \
+ 0x00000010 // 1 - Override the sytem-opp
+ // request to ANATOP using bit0 of
+ // this register
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_M \
+ 0x0000000F // "0001" - RUN ; "0010" - DSLP ;
+ // "0100" - LPDS ; Others - NA
+
+#define GPRCM_MEM_SYS_OPP_REQ_OVERRIDE_mem_sys_opp_req_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_TESTCTRL_PD_OPP_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_M \
+ 0xFFFFFFFE
+
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_reserved_S 1
+#define GPRCM_MEM_TESTCTRL_PD_OPP_CONFIG_mem_sleep_opp_enter_with_testpd_on \
+ 0x00000001 // 1 - Enable sleep-opp (DSLP/LPDS)
+ // entry even if Test-Pd is kept ON
+ // ; 0 - Donot enable sleep-opp
+ // (DSLP/LPDS) entry with Test-Pd
+ // ON.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_WL_FAST_CLK_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_M \
+ 0xFFFFFFF8
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_reserved_S 3
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override_ctrl \
+ 0x00000004 // NA
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_fast_clk_req_override \
+ 0x00000002 // NA
+
+#define GPRCM_MEM_WL_FAST_CLK_REQ_OVERRIDES_mem_wl_sleep_with_clk_req_override \
+ 0x00000001 // NA
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_MCU_PD_MODE_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_mode_req_override_ctrl \
+ 0x00000004 // 1 - Override the MCU-PD power
+ // modes using bits [1] & [0] ;
+
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_pwrdn_req_override \
+ 0x00000002 // 1 - Request for power-down of
+ // MCU-PD ;
+
+#define GPRCM_MEM_MCU_PD_MODE_REQ_OVERRIDES_mem_mcu_pd_ret_req_override \
+ 0x00000001 // 1 - Request for retention mode
+ // of MCU-PD.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override_ctrl \
+ 0x00000002 // 1- Override the MCSPI
+ // (Autonomous SPI) memory state
+ // using bit [0]
+
+#define GPRCM_MEM_MCSPI_SRAM_OFF_REQ_OVERRIDES_mem_mcspi_sram_off_req_override \
+ 0x00000001 // 1 - Request for power-down of
+ // Autonomous SPI 8k memory ; 0 -
+ // Donot request power-down of
+ // Autonomous SPI 8k Memory
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_WLAN_APLLMCS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_wlan_apllmcs_lock \
+ 0x00000100
+
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override \
+ 0x00000002
+
+#define GPRCM_MEM_WLAN_APLLMCS_OVERRIDES_mem_wlan_apllmcs_enable_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_REF_FSM_CFG2 register.
+//
+//******************************************************************************
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_M \
+ 0x00380000 // Number of RTC clocks for keeping
+ // the FC_EN asserted high
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_FC_DEASSERT_DELAY_S 19
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_M \
+ 0x00070000 // Number of RTC clocks for keeping
+ // the STARTUP_EN asserted high
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_STARTUP_DEASSERT_DELAY_S 16
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_M \
+ 0x0000FFFF // Number of RTC clocks for waiting
+ // for clock to settle.
+
+#define GPRCM_MEM_REF_FSM_CFG2_MEM_EXT_TCXO_SETTLING_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TESTCTRL_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_STATUS_S 1
+#define GPRCM_TESTCTRL_POWER_CTRL_TESTCTRL_PD_ENABLE \
+ 0x00000001 // 0 - Disable the TestCtrl-pd ; 1
+ // - Enable the TestCtrl-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_M \
+ 0x00000006 // 1 - SSDIO-PD is ON ; 0 -
+ // SSDIO-PD is OFF
+
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_STATUS_S 1
+#define GPRCM_SSDIO_POWER_CTRL_SSDIO_PD_ENABLE \
+ 0x00000001 // 0 - Disable the SSDIO-pd ; 1 -
+ // Enable the SSDIO-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_N1_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_M \
+ 0x00000006 // 1 - MCSPI_N1-PD is ON ; 0 -
+ // MCSPI_N1-PD if OFF
+
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_STATUS_S 1
+#define GPRCM_MCSPI_N1_POWER_CTRL_MCSPI_N1_PD_ENABLE \
+ 0x00000001 // 0 - Disable the MCSPI_N1-pd ; 1
+ // - Enable the MCSPI_N1-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_M \
+ 0x00001C00
+
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_STATUS_S 10
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE \
+ 0x00000200
+
+#define GPRCM_WELP_POWER_CTRL_WTOP_PD_REQ_OVERRIDE_CTRL \
+ 0x00000100
+
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_STATUS_S 1
+#define GPRCM_WELP_POWER_CTRL_WELP_PD_ENABLE \
+ 0x00000001 // 0 - Disable the WELP-pd ; 1 -
+ // Enable the WELP-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_POWER_CTRL register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_M \
+ 0x00000006
+
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_STATUS_S 1
+#define GPRCM_WL_SDIO_POWER_CTRL_WL_SDIO_PD_ENABLE \
+ 0x00000001 // 0 - Disable the WL_SDIO-pd ; 1 -
+ // Enable the WL_SDIO-pd.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_SRAM_ACTIVE_PWR_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_M \
+ 0x00FFFFFF // SRAM (WTOP+DRP) state during
+ // Active-mode : 1 - SRAMs are ON ;
+ // 0 - SRAMs are OFF. Cluster
+ // information : [0] - 1st column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) [1] - 2nd column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [2] - 3rd column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [3] - 4th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [4] -
+ // 5th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [5] - 6th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [6] - 7th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [7] - 8th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [8] - 9th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [9] -
+ // 10th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [10] - 11th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [11] - 12th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [12] - 13th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [13] - 14th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [14] -
+ // 15th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [15] - 16th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [23:16] - Internal to
+ // WTOP Cluster
+
+#define GPRCM_WLAN_SRAM_ACTIVE_PWR_CFG_WLAN_SRAM_ACTIVE_PWR_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WLAN_SRAM_SLEEP_PWR_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_M \
+ 0x00FFFFFF // SRAM (WTOP+DRP) state during
+ // Sleep-mode : 1 - SRAMs are RET ;
+ // 0 - SRAMs are OFF. Cluster
+ // information : [0] - 1st column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) [1] - 2nd column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [2] - 3rd column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [3] - 4th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [4] -
+ // 5th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [5] - 6th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [6] - 7th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [7] - 8th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [8] - 9th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [9] -
+ // 10th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [10] - 11th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [11] - 12th column of
+ // MEMSS (Applicable only when owned
+ // by WTOP/PHY) ; [12] - 13th column
+ // of MEMSS (Applicable only when
+ // owned by WTOP/PHY) ; [13] - 14th
+ // column of MEMSS (Applicable only
+ // when owned by WTOP/PHY) ; [14] -
+ // 15th column of MEMSS (Applicable
+ // only when owned by WTOP/PHY) ;
+ // [15] - 16th column of MEMSS
+ // (Applicable only when owned by
+ // WTOP/PHY) ; [23:16] - Internal to
+ // WTOP Cluster
+
+#define GPRCM_WLAN_SRAM_SLEEP_PWR_CFG_WLAN_SRAM_SLEEP_PWR_CFG_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SECURE_INIT_DONE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SECURE_INIT_DONE_SECURE_INIT_DONE_STATUS \
+ 0x00000002 // 1-Secure mode init is done ;
+ // 0-Secure mode init is not done
+
+#define GPRCM_APPS_SECURE_INIT_DONE_APPS_SECURE_INIT_DONE \
+ 0x00000001 // Must be programmed 1 in order to
+ // say that secure-mode device init
+ // is done
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_DEV_MODE_INIT_DONE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_DEV_MODE_INIT_DONE_APPS_DEV_MODE_INIT_DONE \
+ 0x00000001 // 1 - Patch download and other
+ // initializations are done (before
+ // removing APPS resetn) for
+ // development mode (#3) . 0 -
+ // Development mode (#3) init is not
+ // done yet
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_EN_APPS_REBOOT register.
+//
+//******************************************************************************
+#define GPRCM_EN_APPS_REBOOT_EN_APPS_REBOOT \
+ 0x00000001 // 1 - When 1, disable the reboot
+ // of APPS after DevInit is
+ // completed. In this case, APPS
+ // will permanantly help in reset. 0
+ // - When 0, enable the reboot of
+ // APPS after DevInit is completed.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_APPS_PERIPH_PRESENT register.
+//
+//******************************************************************************
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_WLAN_GEM_PP \
+ 0x00010000 // 1 - Enable ; 0 - Disable
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_AES_PP \
+ 0x00008000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_DES_PP \
+ 0x00004000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_SHA_PP \
+ 0x00002000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_CAMERA_PP \
+ 0x00001000
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MMCHS_PP \
+ 0x00000800
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCASP_PP \
+ 0x00000400
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A1_PP \
+ 0x00000200
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_MCSPI_A2_PP \
+ 0x00000100
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UDMA_PP \
+ 0x00000080
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_WDOG_PP \
+ 0x00000040
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A0_PP \
+ 0x00000020
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_UART_A1_PP \
+ 0x00000010
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A0_PP \
+ 0x00000008
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A1_PP \
+ 0x00000004
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A2_PP \
+ 0x00000002
+
+#define GPRCM_MEM_APPS_PERIPH_PRESENT_APPS_GPT_A3_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_NWP_PERIPH_PRESENT register.
+//
+//******************************************************************************
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_ASYNC_BRIDGE_PP \
+ 0x00000200
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N2_PP \
+ 0x00000100
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N0_PP \
+ 0x00000080
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_GPT_N1_PP \
+ 0x00000040
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_WDOG_PP \
+ 0x00000020
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UDMA_PP \
+ 0x00000010
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N0_PP \
+ 0x00000008
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_UART_N1_PP \
+ 0x00000004
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_SSDIO_PP \
+ 0x00000002
+
+#define GPRCM_MEM_NWP_PERIPH_PRESENT_NWP_MCSPI_N1_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MEM_SHARED_PERIPH_PRESENT register.
+//
+//******************************************************************************
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_MCSPI_PP \
+ 0x00000040
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_I2C_PP \
+ 0x00000020
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_A_PP \
+ 0x00000010
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_B_PP \
+ 0x00000008
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_C_PP \
+ 0x00000004
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_D_PP \
+ 0x00000002
+
+#define GPRCM_MEM_SHARED_PERIPH_PRESENT_SHARED_GPIO_E_PP \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_M \
+ 0x00000F00 // "0000"- PORZ :- NWP is yet to be
+ // enabled by APPS during powerup
+ // (from HIB/OFF) ; "0011"- ACTIVE
+ // :- NWP is enabled, clocks and
+ // resets to NWP-SubSystem are
+ // enabled ; "0010"- LPDS :- NWP is
+ // in LPDS-mode ; Clocks and reset
+ // to NWP-SubSystem are gated ;
+ // "0101"- WAIT_FOR_OPP :- NWP is in
+ // transition from LPDS to ACTIVE,
+ // where it is waiting for OPP to be
+ // stable ; "1000"-
+ // WAKE_TIMER_OPP_REQ :- NWP is in
+ // transition from LPDS, where the
+ // wakeup cause is LPDS_Wake timer
+ // OTHERS : NA
+
+#define GPRCM_NWP_PWR_STATE_NWP_PWR_STATE_PS_S 8
+#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_M \
+ 0x00000007 // "000" - NWP_RUN : NWP is in RUN
+ // state (default) - Applicable only
+ // when NWP_PWR_STATE_PS = ACTIVE ;
+ // "001" - NWP_SLP : NWP is in SLEEP
+ // state (default) - Applicable only
+ // when NWP_PWR_STATE_PS = ACTIVE ;
+ // "010" - NWP_DSLP : NWP is in
+ // Deep-Sleep state (default) -
+ // Applicable only when
+ // NWP_PWR_STATE_PS = ACTIVE ; "011"
+ // - WAIT_FOR_ACTIVE : NWP is in
+ // transition from Deep-sleep to
+ // Run, where it is waiting for OPP
+ // to be stable ; "100" -
+ // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
+ // NWP is in transition from
+ // Deep-sleep to Run, where the
+ // wakeup cause is deep-sleep
+ // wake-timer
+
+#define GPRCM_NWP_PWR_STATE_NWP_RCM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_M \
+ 0x00000F00 // "0000"- PORZ :- APPS is waiting
+ // for PLL_clock during powerup
+ // (from HIB/OFF) ; "0011"- ACTIVE
+ // :- APPS is enabled, clocks and
+ // resets to APPS-SubSystem are
+ // enabled ; APPS might be either in
+ // Secure or Un-secure mode during
+ // this state. "1001" -
+ // SECURE_MODE_LPDS :- While in
+ // ACTIVE (Secure-mode), APPS had to
+ // program the DevInit_done bit at
+ // the end, after which it enters
+ // into this state, where the reset
+ // to APPS will be asserted. From
+ // this state APPS might either
+ // re-boot itself or enter into LPDS
+ // depending upon whether the device
+ // is 3200 or 3100. "0010"- LPDS :-
+ // APPS is in LPDS-mode ; Clocks and
+ // reset to APPS-SubSystem are gated
+ // ; "0101"- WAIT_FOR_OPP :- APPS is
+ // in transition from LPDS to
+ // ACTIVE, where it is waiting for
+ // OPP to be stable ; "1000" -
+ // WAKE_TIMER_OPP_REQ : APPS is in
+ // transition from LPDS, where the
+ // wakeup cause is LPDS_Wake timer ;
+ // "1010" - WAIT_FOR_PATCH_INIT :
+ // APPS enters into this state
+ // during development-mode #3 (SOP =
+ // 3), where it is waiting for patch
+ // download to complete and 0x4 hack
+ // is programmed. OTHERS : NA
+
+#define GPRCM_APPS_PWR_STATE_APPS_PWR_STATE_PS_S 8
+#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_M \
+ 0x00000007 // "000" - APPS_RUN : APPS is in
+ // RUN state (default) - Applicable
+ // only when APPS_PWR_STATE_PS =
+ // ACTIVE ; "001" - APPS_SLP : APPS
+ // is in SLEEP state (default) -
+ // Applicable only when
+ // APPS_PWR_STATE_PS = ACTIVE ;
+ // "010" - APPS_DSLP : APPS is in
+ // Deep-Sleep state (default) -
+ // Applicable only when
+ // APPS_PWR_STATE_PS = ACTIVE ;
+ // "011" - WAIT_FOR_ACTIVE : APPS is
+ // in transition from Deep-sleep to
+ // Run, where it is waiting for OPP
+ // to be stable ; "100" -
+ // WAIT_FOR_DSLP_TIMER_WAKE_REQ :
+ // APPS is in transition from
+ // Deep-sleep to Run, where the
+ // wakeup cause is deep-sleep
+ // wake-timer
+
+#define GPRCM_APPS_PWR_STATE_APPS_RCM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PWR_STATE register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_M \
+ 0x0000001F // TBD
+
+#define GPRCM_MCU_PWR_STATE_MCU_OPP_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PM_PS register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_M \
+ 0x00000007 // "011" - WTOP_PM_ACTIVE (Default)
+ // :- WTOP_Pd is in ACTIVE mode;
+ // "100" - WTOP_PM_ACTIVE_TO_SLEEP
+ // :- WTOP_Pd is in transition from
+ // ACTIVE to SLEEP ; "000" -
+ // WTOP_PM_SLEEP : WTOP-Pd is in
+ // Sleep-state ; "100" -
+ // WTOP_PM_SLEEP_TO_ACTIVE : WTOP_Pd
+ // is in transition from SLEEP to
+ // ACTIVE ; "000" -
+ // WTOP_PM_WAIT_FOR_OPP : Wait for
+ // OPP to be stable ;
+
+#define GPRCM_WTOP_PM_PS_WTOP_PM_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WTOP PD
+ // Resetz. When set to 1,
+ // WTOP_Resetz will be controlled by
+ // bit [0]
+
+#define GPRCM_WTOP_PD_RESETZ_OVERRIDE_REG_WTOP_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WTOP PD Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WELP PD
+ // Resetz. When set to 1,
+ // WELP_Resetz will be controlled by
+ // bit [0]
+
+#define GPRCM_WELP_PD_RESETZ_OVERRIDE_REG_WELP_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WELP PD Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for WL_SDIO
+ // Resetz. When set to 1,
+ // WL_SDIO_Resetz will be controlled
+ // by bit [0]
+
+#define GPRCM_WL_SDIO_PD_RESETZ_OVERRIDE_REG_WL_SDIO_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for WL_SDIO Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for SSDIO
+ // Resetz. When set to 1,
+ // SSDIO_Resetz will be controlled
+ // by bit [0]
+
+#define GPRCM_SSDIO_PD_RESETZ_OVERRIDE_REG_SSDIO_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for SSDIO Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_N1_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for MCSPI_N1
+ // Resetz. When set to 1,
+ // MCSPI_N1_Resetz will be
+ // controlled by bit [0]
+
+#define GPRCM_MCSPI_N1_PD_RESETZ_OVERRIDE_REG_MCSPI_N1_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for MCSPI_N1 Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TESTCTRL_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for TESTCTRL-PD
+ // Resetz. When set to 1,
+ // TESTCTRL_Resetz will be
+ // controlled by bit [0]
+
+#define GPRCM_TESTCTRL_PD_RESETZ_OVERRIDE_REG_TESTCTRL_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for TESTCTRL Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PD_RESETZ_OVERRIDE_REG register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE_CTRL \
+ 0x00000100 // Override control for MCU-PD
+ // Resetz. When set to 1, MCU_Resetz
+ // will be controlled by bit [0]
+
+#define GPRCM_MCU_PD_RESETZ_OVERRIDE_REG_MCU_PD_RESETZ_OVERRIDE \
+ 0x00000001 // Override for MCU Resetz.
+ // Applicable only when bit[8] is
+ // set to 1
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG0 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_M \
+ 0xFFFFFFFF // This is ROW_14 [31:0] of
+ // FUSEFARM. [0:0] : XTAL_IS_26MHZ
+ // [5:1] : TOP_CLKM_RTRIM[4:0]
+ // [10:6] : ANA_BGAP_MAG_TRIM[4:0]
+ // [16:11] : ANA_BGAP_TEMP_TRIM[5:0]
+ // [20:17] : ANA_BGAP_V2I_TRIM[3:0]
+ // [25:22] : PROCESS INDICATOR
+ // [26:26] : Reserved [31:27] :
+ // FUSEROM Version
+
+#define GPRCM_GPRCM_EFUSE_READ_REG0_FUSEFARM_ROW_14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG1 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_M \
+ 0x0000FFFF // This is ROW_15[15:0] of FUSEFARM
+ // 1. NWP Peripheral Present bits
+ // [15:8] NWP_GPT_N0_PP [15:15]
+ // NWP_GPT_N1_PP [14:14] NWP_WDOG_PP
+ // [13:13] NWP_UDMA_PP [12:12]
+ // NWP_UART_N0_PP [11:11]
+ // NWP_UART_N1_PP [10:10]
+ // NWP_SSDIO_PP [9:9]
+ // NWP_MCSPI_N1_PP [8:8] 2. Shared
+ // Peripheral Present bits [7:0]
+ // SHARED SPI PP [6:6]
+ // SHARED I2C PP [5:5] SHARED
+ // GPIO-A PP [4:4] SHARED GPIO-B PP
+ // [3:3] SHARED GPIO-C PP [2:2]
+ // SHARED GPIO-D PP [1:1] SHARED
+ // GPIO-E PP [0:0]
+
+#define GPRCM_GPRCM_EFUSE_READ_REG1_FUSEFARM_ROW_15_LSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG2 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_M \
+ 0xFFFFFFFF // This is ROW_16[15:0] &
+ // ROW_15[31:16] of FUSEFARM.
+ // [31:21] - Reserved [20:16] -
+ // CHIP_ID [15:15] - SSBD SOP
+ // Control [14:14] - SSBD TAP
+ // Control [13:2] - APPS Peripheral
+ // Present bits : APPS_CAMERA_PP
+ // [13:13] APPS_MMCHS_PP [12:12]
+ // APPS_MCASP_PP [11:11]
+ // APPS_MCSPI_A1_PP [10:10]
+ // APPS_MCSPI_A2_PP [9:9]
+ // APPS_UDMA_PP [8:8] APPS_WDOG_PP
+ // [7:7] APPS_UART_A0_PP [6:6]
+ // APPS_UART_A1_PP [5:5]
+ // APPS_GPT_A0_PP [4:4]
+ // APPS_GPT_A1_PP [3:3]
+ // APPS_GPT_A2_PP [2:2]
+ // APPS_GPT_A3_PP [1:1] [0:0] - NWP
+ // Peripheral present bits
+ // NWP_ACSPI_PP [0:0]
+
+#define GPRCM_GPRCM_EFUSE_READ_REG2_FUSEFARM_ROW_16_LSW_ROW_15_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG3 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_M \
+ 0xFFFFFFFF // This is ROW_17[15:0] &
+ // ROW_16[31:16] of FUSEFARM :
+ // [31:16] - TEST_TAP_KEY(15:0)
+ // [15:0] - Reserved
+
+#define GPRCM_GPRCM_EFUSE_READ_REG3_FUSEFARM_ROW_17_LSW_ROW_16_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_MEM_RET_CFG register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_MEM_RET_CFG_WTOP_MEM_RET_CFG \
+ 0x00000001 // 1 - Soft-compile memories in
+ // WTOP can be turned-off during
+ // WTOP-sleep mode ; 0 -
+ // Soft-compile memories in WTOP
+ // must be kept on during WTOP-sleep
+ // mode.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG0 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_M \
+ 0x007FFFFF // TBD
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG0_Q_FACTOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG1 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_M \
+ 0x000FFFFF // TBD
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG1_P_FACTOR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_CFG2 register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_M \
+ 0x00000018
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_CONSECUTIVE_SWALLOW_S 3
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_GAIN \
+ 0x00000004
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_PRBS_ENABLE \
+ 0x00000002
+
+#define GPRCM_COEX_CLK_SWALLOW_CFG2_SWALLOW_ENABLE \
+ 0x00000001 // TBD
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_COEX_CLK_SWALLOW_ENABLE register.
+//
+//******************************************************************************
+#define GPRCM_COEX_CLK_SWALLOW_ENABLE_COEX_CLK_SWALLOW_ENABLE \
+ 0x00000001 // 1 - Enable switching of sysclk
+ // to Coex-clk path ; 0 - Disable
+ // switching of sysclk to Coex-clk
+ // path.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_DCDC_CLK_GEN_CONFIG register.
+//
+//******************************************************************************
+#define GPRCM_DCDC_CLK_GEN_CONFIG_DCDC_CLK_ENABLE \
+ 0x00000001 // 1 - Enable the clock for DCDC
+ // (PWM-mode) ; 0 - Disable the
+ // clock for DCDC (PWM-mode)
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG4 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_M \
+ 0x0000FFFF // This corresponds to
+ // ROW_17[31:16] of the FUSEFARM :
+ // [15:0] : TEST_TAP_KEY(31:16)
+
+#define GPRCM_GPRCM_EFUSE_READ_REG4_FUSEFARM_ROW_17_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG5 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_M \
+ 0xFFFFFFFF // Corresponds to ROW_18 of
+ // FUSEFARM. [29:0] -
+ // MEMSS_COLUMN_SEL_LSW ; [30:30] -
+ // WLAN GEM DISABLE ; [31:31] -
+ // SERIAL WIRE JTAG SELECT
+
+#define GPRCM_GPRCM_EFUSE_READ_REG5_FUSEFARM_ROW_18_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG6 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_M \
+ 0x0000FFFF // Corresponds to ROW_19[15:0] of
+ // FUSEFARM. [15:0] :
+ // MEMSS_COLUMN_SEL_MSW
+
+#define GPRCM_GPRCM_EFUSE_READ_REG6_FUSEFARM_ROW_19_LSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG7 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_20[15:0] &
+ // ROW_19[31:16] of FUSEFARM.
+ // FLASH_REGION0
+
+#define GPRCM_GPRCM_EFUSE_READ_REG7_FUSEFARM_ROW_20_LSW_ROW_19_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG8 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_21[15:0] &
+ // ROW_20[31:16] of FUSEFARM.
+ // FLASH_REGION1
+
+#define GPRCM_GPRCM_EFUSE_READ_REG8_FUSEFARM_ROW_21_LSW_ROW_20_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG9 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_22[15:0] &
+ // ROW_21[31:16] of FUSEFARM.
+ // FLASH_REGION2
+
+#define GPRCM_GPRCM_EFUSE_READ_REG9_FUSEFARM_ROW_22_LSW_ROW_21_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG10 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_23[15:0] &
+ // ROW_22[31:16] of FUSEFARM.
+ // FLASH_REGION3
+
+#define GPRCM_GPRCM_EFUSE_READ_REG10_FUSEFARM_ROW_23_LSW_ROW_22_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_EFUSE_READ_REG11 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_M \
+ 0xFFFFFFFF // Corresponds to ROW_24[15:0] &
+ // ROW_23[31:16] of FUSEFARM.
+ // FLASH_DESCRIPTOR
+
+#define GPRCM_GPRCM_EFUSE_READ_REG11_FUSEFARM_ROW_24_LSW_ROW_23_MSW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG0 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_M \
+ 0xFFFFFFFF // Corresponds to bits [191:160] of
+ // the FUSEFARM. This is ROW_5 of
+ // FUSEFARM [191:160] : [31:0] :
+ // DIE_ID0 [31:0] : DEVX [11:0] DEVY
+ // [23:12] DEVWAF [29:24] DEV_SPARE
+ // [31:30]
+
+#define GPRCM_GPRCM_DIEID_READ_REG0_FUSEFARM_191_160_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG1 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_M \
+ 0xFFFFFFFF // Corresponds to bits [223:192] of
+ // the FUSEFARM. This is ROW_6 of
+ // FUSEFARM :- DEVLOT [23:0] DEVFAB
+ // [28:24] DEVFABBE [31:29]
+
+#define GPRCM_GPRCM_DIEID_READ_REG1_FUSEFARM_223_192_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG2 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_M \
+ 0xFFFFFFFF // Corresponds to bits [255:224] of
+ // the FUSEFARM. This is ROW_7 of
+ // FUSEFARM:- DEVDESREV[4:0]
+ // Memrepair[5:5] MakeDefined[16:6]
+ // CHECKSUM[30:17] Reserved :
+ // [31:31]
+
+#define GPRCM_GPRCM_DIEID_READ_REG2_FUSEFARM_255_224_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG3 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_M \
+ 0xFFFFFFFF // Corresponds to bits [287:256] of
+ // the FUSEFARM. This is ROW_8 of
+ // FUSEFARM :- DIEID0 - DEVREG
+ // [31:0]
+
+#define GPRCM_GPRCM_DIEID_READ_REG3_FUSEFARM_287_256_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_GPRCM_DIEID_READ_REG4 register.
+//
+//******************************************************************************
+#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_M \
+ 0xFFFFFFFF // Corresponds to bits [319:288] of
+ // the FUSEFARM. This is ROW_9 of
+ // FUSEFARM :- [7:0] - VBATMON ;
+ // [13:8] - BUFF_OFFSET ; [15:15] -
+ // DFT_GXG ; [14:14] - DFT_GLX ;
+ // [19:16] - PHY ROM Version ;
+ // [23:20] - MAC ROM Version ;
+ // [27:24] - NWP ROM Version ;
+ // [31:28] - APPS ROM Version
+
+#define GPRCM_GPRCM_DIEID_READ_REG4_FUSEFARM_319_288_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_APPS_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_APPS_SS_OVERRIDES_reserved_M \
+ 0xFFFFFC00
+
+#define GPRCM_APPS_SS_OVERRIDES_reserved_S 10
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override \
+ 0x00000200
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_refclk_gating_override_ctrl \
+ 0x00000100
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override \
+ 0x00000080
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_pllclk_gating_override_ctrl \
+ 0x00000040
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override \
+ 0x00000020
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override \
+ 0x00000010
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override \
+ 0x00000008
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_por_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysrstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_APPS_SS_OVERRIDES_mem_apps_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_NWP_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_NWP_SS_OVERRIDES_reserved_M \
+ 0xFFFFFC00
+
+#define GPRCM_NWP_SS_OVERRIDES_reserved_S 10
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override \
+ 0x00000200
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_refclk_gating_override_ctrl \
+ 0x00000100
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override \
+ 0x00000080
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_pllclk_gating_override_ctrl \
+ 0x00000040
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override \
+ 0x00000020
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override \
+ 0x00000010
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override \
+ 0x00000008
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_por_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysrstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_NWP_SS_OVERRIDES_mem_nwp_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SHARED_SS_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_SHARED_SS_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_SHARED_SS_OVERRIDES_reserved_S 8
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override_ctrl \
+ 0x00000080
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_pllclk_gating_override \
+ 0x00000040
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override_ctrl \
+ 0x00000020
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_refclk_gating_override \
+ 0x00000010
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override \
+ 0x00000008
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override \
+ 0x00000004
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_rstn_override_ctrl \
+ 0x00000002
+
+#define GPRCM_SHARED_SS_OVERRIDES_mem_shared_sysclk_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_IDMEM_CORE_RST_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_reserved_S 8
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override \
+ 0x00000080
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override \
+ 0x00000040
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW1 \
+ 0x00000020
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override \
+ 0x00000010
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_sysrstn_override_ctrl \
+ 0x00000008
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_fmc_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_SPARE_RW0 \
+ 0x00000002
+
+#define GPRCM_IDMEM_CORE_RST_OVERRIDES_mem_idmem_core_piosc_gating_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_TOP_DIE_FSM_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_M \
+ 0xFFFFF000
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_reserved_S 12
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override_ctrl \
+ 0x00000800
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_pgoodin_override \
+ 0x00000400
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override \
+ 0x00000200
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override \
+ 0x00000100
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override \
+ 0x00000080
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override \
+ 0x00000040
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override \
+ 0x00000020
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_hclk_gating_override_ctrl \
+ 0x00000010
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_piosc_gating_override_ctrl \
+ 0x00000008
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_rstn_override_ctrl \
+ 0x00000004
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_d2d_pwr_switch_ponin_override_ctrl \
+ 0x00000002
+
+#define GPRCM_TOP_DIE_FSM_OVERRIDES_mem_flash_ready_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCU_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MCU_PSCON_OVERRIDES_reserved_M \
+ 0xFFF00000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_reserved_S 20
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_sleep_override_ctrl \
+ 0x00080000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override_ctrl \
+ 0x00040000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_ctrl \
+ 0x00020000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_ctrl \
+ 0x00010000
+
+#define GPRCM_MCU_PSCON_OVERRIDES_NU1_M \
+ 0x0000FC00
+
+#define GPRCM_MCU_PSCON_OVERRIDES_NU1_S 10
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_sleep_override \
+ 0x00000200
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_update_override \
+ 0x00000100
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_M \
+ 0x000000F0
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_off_override_S 4
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_M \
+ 0x0000000F
+
+#define GPRCM_MCU_PSCON_OVERRIDES_mem_mcu_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WTOP_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_M \
+ 0xFFC00000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_reserved_S 22
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override_ctrl \
+ 0x00200000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override_ctrl \
+ 0x00100000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_ctrl \
+ 0x00080000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_ctrl \
+ 0x00040000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_sleep_override \
+ 0x00020000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_update_override \
+ 0x00010000
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_M \
+ 0x0000FF00
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_off_override_S 8
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_M \
+ 0x000000FF
+
+#define GPRCM_WTOP_PSCON_OVERRIDES_mem_wtop_pscon_mem_retain_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WELP_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WELP_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_WELP_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_WELP_PSCON_OVERRIDES_mem_welp_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_WL_SDIO_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_WL_SDIO_PSCON_OVERRIDES_mem_wl_sdio_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_MCSPI_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFF00
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_reserved_S 8
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override_ctrl \
+ 0x00000080
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override_ctrl \
+ 0x00000040
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_retain_override \
+ 0x00000020
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_off_override \
+ 0x00000010
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override_ctrl \
+ 0x00000008
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_mem_update_override \
+ 0x00000004
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_MCSPI_PSCON_OVERRIDES_mem_mcspi_pscon_sleep_override \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// GPRCM_O_SSDIO_PSCON_OVERRIDES register.
+//
+//******************************************************************************
+#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_M \
+ 0xFFFFFFFC
+
+#define GPRCM_SSDIO_PSCON_OVERRIDES_reserved_S 2
+#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override_ctrl \
+ 0x00000002
+
+#define GPRCM_SSDIO_PSCON_OVERRIDES_mem_ssdio_pscon_sleep_override \
+ 0x00000001
+
+
+
+
+#endif // __HW_GPRCM_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_hib1p2.h b/ext/hal/ti/cc3220sdk/inc/hw_hib1p2.h
new file mode 100644
index 0000000..4b5e8db
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_hib1p2.h
@@ -0,0 +1,1748 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_HIB1P2_H__
+#define __HW_HIB1P2_H__
+
+//*****************************************************************************
+//
+// The following are defines for the HIB1P2 register offsets.
+//
+//*****************************************************************************
+#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 \
+ 0x00000000
+
+#define HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 \
+ 0x00000004
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS0 \
+ 0x00000008
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS1 \
+ 0x0000000C
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS2 \
+ 0x00000010
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS3 \
+ 0x00000014
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS4 \
+ 0x00000018
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS5 \
+ 0x0000001C
+
+#define HIB1P2_O_DIG_DCDC_PARAMETERS6 \
+ 0x00000020
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS0 \
+ 0x00000024
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS1 \
+ 0x00000028
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS16 \
+ 0x00000064
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS17 \
+ 0x00000068
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS18 \
+ 0x0000006C
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS19 \
+ 0x00000070
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS0 \
+ 0x00000074
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS1 \
+ 0x00000078
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS2 \
+ 0x0000007C
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS3 \
+ 0x00000080
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS4 \
+ 0x00000084
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS5 \
+ 0x00000088
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS6 \
+ 0x0000008C
+
+#define HIB1P2_O_PMBIST_PARAMETERS0 \
+ 0x00000094
+
+#define HIB1P2_O_PMBIST_PARAMETERS1 \
+ 0x00000098
+
+#define HIB1P2_O_PMBIST_PARAMETERS2 \
+ 0x0000009C
+
+#define HIB1P2_O_PMBIST_PARAMETERS3 \
+ 0x000000A0
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS8 \
+ 0x000000A4
+
+#define HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE \
+ 0x000000A8
+
+#define HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE \
+ 0x000000AC
+
+#define HIB1P2_O_DIG_DCDC_VTRIM_CFG \
+ 0x000000B0
+
+#define HIB1P2_O_DIG_DCDC_FSM_PARAMETERS \
+ 0x000000B4
+
+#define HIB1P2_O_ANA_DCDC_FSM_PARAMETERS \
+ 0x000000B8
+
+#define HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS \
+ 0x000000BC
+
+#define HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG \
+ 0x000000C0
+
+#define HIB1P2_O_CM_OSC_16M_CONFIG \
+ 0x000000C4
+
+#define HIB1P2_O_SOP_SENSE_VALUE \
+ 0x000000C8
+
+#define HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 \
+ 0x000000CC
+
+#define HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 \
+ 0x000000D0
+
+#define HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES \
+ 0x000000D4
+
+#define HIB1P2_O_HIB1P2_EFUSE_READ_REG0 \
+ 0x000000D8
+
+#define HIB1P2_O_HIB1P2_EFUSE_READ_REG1 \
+ 0x000000DC
+
+#define HIB1P2_O_HIB1P2_POR_TEST_CTRL \
+ 0x000000E0
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 \
+ 0x000000E4
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 \
+ 0x000000E8
+
+#define HIB1P2_O_HIB_TIMER_SYNC_CFG2 \
+ 0x000000EC
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL \
+ 0x000000F0
+
+#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW \
+ 0x000000F4
+
+#define HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW \
+ 0x000000F8
+
+#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW \
+ 0x000000FC
+
+#define HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW \
+ 0x00000100
+
+#define HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR \
+ 0x00000104
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW \
+ 0x00000108
+
+#define HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW \
+ 0x0000010C
+
+#define HIB1P2_O_CM_SPARE 0x00000110
+#define HIB1P2_O_PORPOL_SPARE 0x00000114
+#define HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG \
+ 0x00000118
+
+#define HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG \
+ 0x0000011C
+
+#define HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG \
+ 0x00000120
+
+#define HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG \
+ 0x00000124
+
+#define HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE \
+ 0x00000128
+
+#define HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE \
+ 0x0000012C
+
+#define HIB1P2_O_MEM_HIB_FSM_DEBUG \
+ 0x00000130
+
+#define HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL \
+ 0x00000134
+
+#define HIB1P2_O_MEM_SLDO_WEAK_PROCESS \
+ 0x00000138
+
+#define HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS \
+ 0x0000013C
+
+#define HIB1P2_O_MEM_CM_TEST_MODE \
+ 0x00000140
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_M \
+ 0xC0000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_itrim_lowv_S 30
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_M \
+ 0x30000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_iq_trim_lowv_S 28
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_sc_prot_lowv \
+ 0x08000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_override \
+ 0x04000000 // FSM Override value for SLDO_EN :
+ // Applicable only when bit [4] of
+ // this register is set to 1.
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_low_pwr_lowv \
+ 0x02000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_int_cap_sel_lowv \
+ 0x01000000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_M \
+ 0x00FC0000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_vtrim_lowv_S 18
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_M \
+ 0x0003FF00
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_spare_lowv_S 8
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_override \
+ 0x00000080 // FSM Override value for
+ // SKA_LDO_EN : Applicable only when
+ // bit [3] of this register is set
+ // to 1.
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_cap_ref_lowv \
+ 0x00000040
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_resdiv_ref_lowv \
+ 0x00000020
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_sldo_en_lowv_fsm_override_ctrl \
+ 0x00000010 // When 1, bit[26] of this register
+ // will be used as SLDO_EN
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_mem_skaldo_en_lowv_fsm_override_ctrl \
+ 0x00000008 // When 1, bit[26] of this register
+ // will be used as SKA_LDO_EN
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_M \
+ 0x00000007
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS0_NA1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_M \
+ 0xFFC00000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_ctrl_lowv_S 22
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_M \
+ 0x003F0000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_vtrim_lowv_S 16
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_sldo_en_tload_lowv \
+ 0x00008000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_tload_lowv \
+ 0x00004000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_cap_sw_en_lowv \
+ 0x00002000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_hib_lowv \
+ 0x00001000
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_mem_skaldo_en_vref_buf_lowv \
+ 0x00000800
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_M \
+ 0x000007FF
+
+#define HIB1P2_SRAM_SKA_LDO_PARAMETERS1_NA2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_lowv_override \
+ 0x80000000 // Override value for DCDC_DIG_EN :
+ // Applicable only when bit [31] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p8v_lowv_override \
+ 0x20000000 // Override value for
+ // DCDC_DIG_EN_SUBREG_1P8V :
+ // Applicable only when bit [30] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_subreg_1p2v_lowv_override \
+ 0x10000000 // Override value for
+ // DCDC_DIG_EN_SUBREG_1P2V :
+ // Applicable only when bit [29] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_slp_mode_lowv_override \
+ 0x08000000 // Override value for
+ // DCDC_DIG_SLP_EN : Applicable only
+ // when bit [28] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1. Else from FSM
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_ldo_mode_lowv \
+ 0x04000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_nfet_rds_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_pfet_rds_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_ext_smps_override_mode_lowv \
+ 0x00800000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_clk_in_lowv_enable \
+ 0x00400000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_M \
+ 0x003F0000 // Override value for
+ // DCDC_DIG_VTRIM : Applicable only
+ // when bit [27] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1.
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_vtrim_lowv_override_S 16
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_M \
+ 0x0000C000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_pfm_ripple_trim_lowv_S 14
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_M \
+ 0x00003000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_iq_ctrl_lowv_S 12
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_en_cl_non_ov_lowv \
+ 0x00000800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_M \
+ 0x00000780
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_non_ov_ctrl_lowv_S 7
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_M \
+ 0x00000078
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_mem_dcdc_dig_slp_drv_dly_sel_lowv_S 3
+#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_M \
+ 0x00000007
+
+#define HIB1P2_DIG_DCDC_PARAMETERS0_NA3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_lowv_fsm_override_ctrl \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p8v_fsm_override_ctrl \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_subreg_1p2v_fsm_override_ctrl \
+ 0x20000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_en_slp_mode_lowv_fsm_override_ctrl \
+ 0x10000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_vtrim_fsm_override_ctrl \
+ 0x08000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_cot_mode_en_lowv_fsm_override_ctrl \
+ 0x04000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_mem_dcdc_dig_ilim_trim_lowv_efc_override_ctrl \
+ 0x02000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_M \
+ 0x01FFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS1_NA4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pfet_sel_lowv_S 28
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_M \
+ 0x0F000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_nfet_sel_lowv_S 24
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_M \
+ 0x00C00000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_stagger_ctrl_lowv_S 22
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_M \
+ 0x00300000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_stagger_ctrl_lowv_S 20
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_pdrv_str_sel_lowv_S 16
+#define HIB1P2_DIG_DCDC_PARAMETERS2_NA5 \
+ 0x00008000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_M \
+ 0x00007800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ndrv_str_sel_lowv_S 11
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_en_shootthru_ctrl_lowv \
+ 0x00000400
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_M \
+ 0x000003FC
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_ton_trim_lowv_S 2
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_swcap_res_hf_clk_lowv \
+ 0x00000002
+
+#define HIB1P2_DIG_DCDC_PARAMETERS2_mem_dcdc_dig_cot_mode_en_lowv_override \
+ 0x00000001 // Override value for
+ // DCDC_DIG_COT_EN : Applicable only
+ // when bit[26] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS3_NA6 \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_M \
+ 0x7F800000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_cot_ctrl_lowv_S 23
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_lowv \
+ 0x00400000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ilim_hib_lowv \
+ 0x00200000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_M \
+ 0x001FE000 // Override value for
+ // DCDC_DIG_ILIM_TRIM : Applicable
+ // only when bit [25] of
+ // DIG_DCDC_PARAMETERS1 [0x000C] is
+ // set to 1
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_trim_lowv_override_S 13
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_M \
+ 0x00001800
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ilim_mask_dly_sel_lowv_S 11
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_lowv \
+ 0x00000400
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ncomp_hib_lowv \
+ 0x00000200
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_M \
+ 0x000001F0
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_trim_lowv_S 4
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_ncomp_mask_dly_sel_lowv_S 2
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_uv_prot_lowv \
+ 0x00000002
+
+#define HIB1P2_DIG_DCDC_PARAMETERS3_mem_dcdc_dig_en_ov_prot_lowv \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS4 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_uv_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_dcdc_dig_ov_prot_out_lowv \
+ 0x40000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_mem_dcdc_dig_en_tmux_lowv \
+ 0x20000000
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_M \
+ 0x1FFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS4_NA7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS5 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS5_mem_dcdc_dig_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_PARAMETERS6 register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_DIG_DCDC_PARAMETERS6_mem_dcdc_dig_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_lowv_override \
+ 0x80000000 // Override for ANA DCDC EN
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p8v_lowv \
+ 0x20000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_subreg_1p2v_lowv \
+ 0x10000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pwm_mode_lowv_override \
+ 0x08000000 // Override for ANA DCDC PWM
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_slp_mode_lowv_override \
+ 0x04000000 // Override for ANA DCDC SLP
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_ldo_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_pfet_rds_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_nfet_rds_mode_lowv \
+ 0x00800000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_ext_smps_override_mode_lowv \
+ 0x00400000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_clk_in_lowv_enable \
+ 0x00200000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_M \
+ 0x001E0000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_vtrim_lowv_S 17
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_M \
+ 0x00018000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfm_ripple_trim_lowv_S 15
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_M \
+ 0x00006000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_iq_ctrl_lowv_S 13
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_en_cl_non_ov_lowv \
+ 0x00001000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_M \
+ 0x00000F00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_non_ov_ctrl_lowv_S 8
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_M \
+ 0x000000F0
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_slp_drv_dly_sel_lowv_S 4
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_M \
+ 0x0000000F
+
+#define HIB1P2_ANA_DCDC_PARAMETERS0_mem_dcdc_ana_pfet_sel_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_nfet_sel_lowv_S 28
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_M \
+ 0x0C000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_stagger_ctrl_lowv_S 26
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_M \
+ 0x03000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_stagger_ctrl_lowv_S 24
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_M \
+ 0x00F00000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_pdrv_str_sel_lowv_S 20
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ndrv_str_sel_lowv_S 16
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_rtrim_lowv \
+ 0x00008000 // (Earlier SHOOTTHRU CTRL)
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_apwm_en_lowv \
+ 0x00004000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_M \
+ 0x00003E00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_ramp_hgt_lowv_S 9
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_anti_glitch_lowv \
+ 0x00000100
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_hi_clamp_lowv \
+ 0x00000080
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_M \
+ 0x00000060
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_hi_clamp_trim_lowv_S 5
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_en_lo_clamp_lowv \
+ 0x00000010
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_mem_dcdc_ana_lo_clamp_trim_lowv_S 2
+#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_M \
+ 0x00000003
+
+#define HIB1P2_ANA_DCDC_PARAMETERS1_NA8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS16 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_lowv \
+ 0x00200000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ilim_hib_lowv \
+ 0x00100000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_M \
+ 0x000FF000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_trim_lowv_override_S 12
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_M \
+ 0x00000C00
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ilim_mask_dly_sel_lowv_S 10
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_lowv \
+ 0x00000200
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ncomp_hib_lowv \
+ 0x00000100
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_M \
+ 0x000000F8
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_trim_lowv_S 3
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_M \
+ 0x00000006
+
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_ncomp_mask_dly_sel_lowv_S 1
+#define HIB1P2_ANA_DCDC_PARAMETERS16_mem_dcdc_ana_en_ov_prot_lowv \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS17 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS17_dcdc_ana_ov_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_mem_dcdc_ana_en_tmux_lowv \
+ 0x40000000
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_M \
+ 0x3FFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS17_NA17_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS18 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS18_mem_dcdc_ana_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS19 register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_ANA_DCDC_PARAMETERS19_mem_dcdc_ana_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_delayed_en_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_clk_in_lowv_enable \
+ 0x20000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_M \
+ 0x18000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_iq_ctrl_lowv_S 27
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_mode_lowv \
+ 0x04000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_boost_mode_lowv \
+ 0x02000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_buck_boost_mode_lowv \
+ 0x01000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_bb_alt_cycles_lowv \
+ 0x00800000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_cl_non_ov_lowv \
+ 0x00400000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_M \
+ 0x003C0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_non_ov_ctrl_lowv_S 18
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_drv_lowv \
+ 0x00020000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pwm_mode_lowv \
+ 0x00010000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_pfm_comp_lowv \
+ 0x00008000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_slp_mode_lowv \
+ 0x00004000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n1fet_rds_mode_lowv \
+ 0x00002000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_n2fet_rds_mode_lowv \
+ 0x00001000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p1fet_rds_mode_lowv \
+ 0x00000800
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_en_p2fet_rds_mode_lowv \
+ 0x00000400
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_ext_smps_mode_override_lowv \
+ 0x00000200
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_M \
+ 0x000001E0
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_p1fet_sel_lowv_S 5
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_M \
+ 0x0000001E
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_mem_dcdc_flash_n1fet_sel_lowv_S 1
+#define HIB1P2_FLASH_DCDC_PARAMETERS0_NA18 \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_M \
+ 0xF0000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_sel_lowv_S 28
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_M \
+ 0x0F000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_sel_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_M \
+ 0x00F00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1drv_str_sel_lowv_S 20
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_M \
+ 0x000F0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1drv_str_sel_lowv_S 16
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_M \
+ 0x0000F000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2drv_str_sel_lowv_S 12
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_M \
+ 0x00000F00
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2drv_str_sel_lowv_S 8
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_M \
+ 0x000000C0
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p1fet_non_ov_lowv_S 6
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_M \
+ 0x00000030
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n1fet_non_ov_lowv_S 4
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_M \
+ 0x0000000C
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_p2fet_non_ov_lowv_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_M \
+ 0x00000003
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS1_mem_dcdc_flash_n2fet_non_ov_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_M \
+ 0xC0000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p1fet_stagger_lowv_S 30
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_M \
+ 0x30000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n1fet_stagger_lowv_S 28
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_M \
+ 0x0C000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_p2fet_stagger_lowv_S 26
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_M \
+ 0x03000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_n2fet_stagger_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_shoot_thru_ctrl_lowv \
+ 0x00800000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_lowv \
+ 0x00400000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ncomp_hib_lowv \
+ 0x00200000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_M \
+ 0x001F0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_trim_lowv_S 16
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_M \
+ 0x0000F000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ncomp_mask_dly_trim_lowv_S 12
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_lowv \
+ 0x00000800
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_en_ilim_hib_lowv \
+ 0x00000400
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_M \
+ 0x000003FC
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_trim_lowv_override_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_M \
+ 0x00000003
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS2_mem_dcdc_flash_ilim_mask_dly_sel_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_anti_glitch_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_hi_clamp_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_lo_clamp_lowv \
+ 0x20000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_M \
+ 0x1F000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_ramp_hgt_lowv_S 24
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_M \
+ 0x00E00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclamph_trim_lowv_S 21
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_M \
+ 0x001C0000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vclampl_trim_lowv_S 18
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_M \
+ 0x0003C000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_vtrim_lowv_S 14
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_M \
+ 0x00003C00
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_pfm_ripple_trim_lowv_S 10
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_M \
+ 0x00000300
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_slp_drv_dly_sel_lowv_S 8
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_ov_prot_lowv \
+ 0x00000080
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_uv_prot_lowv \
+ 0x00000040
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_mem_dcdc_flash_en_tmux_lowv \
+ 0x00000020
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_M \
+ 0x0000001F
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS3_NA19_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS4 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS4_mem_dcdc_flash_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS5 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS5_mem_dcdc_flash_spare_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS6 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_ov_prot_out_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_dcdc_flash_uv_prot_out_lowv \
+ 0x40000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_M \
+ 0x3FFFFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS6_NA20_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_en_lowv \
+ 0x80000000
+
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_M \
+ 0x7FFFF800
+
+#define HIB1P2_PMBIST_PARAMETERS0_mem_pm_bist_ctrl_lowv_S 11
+#define HIB1P2_PMBIST_PARAMETERS0_NA21_M \
+ 0x000007FF
+
+#define HIB1P2_PMBIST_PARAMETERS0_NA21_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_M \
+ 0xFFFF0000
+
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pm_bist_spare_lowv_S 16
+#define HIB1P2_PMBIST_PARAMETERS1_mem_pmtest_en_lowv \
+ 0x00008000
+
+#define HIB1P2_PMBIST_PARAMETERS1_NA22_M \
+ 0x00007FFF
+
+#define HIB1P2_PMBIST_PARAMETERS1_NA22_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS2 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_PMBIST_PARAMETERS2_mem_pmtest_tmux_ctrl_lowv_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PMBIST_PARAMETERS3 register.
+//
+//******************************************************************************
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_M \
+ 0xFFFF0000
+
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_spare_lowv_S 16
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_M \
+ 0x0000E000
+
+#define HIB1P2_PMBIST_PARAMETERS3_mem_pmtest_load_trim_lowv_S 13
+#define HIB1P2_PMBIST_PARAMETERS3_mem_rnwell_calib_en_lowv \
+ 0x00001000
+
+#define HIB1P2_PMBIST_PARAMETERS3_NA23_M \
+ 0x00000FFF
+
+#define HIB1P2_PMBIST_PARAMETERS3_NA23_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS8 register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_en_flash_sup_comp_lowv \
+ 0x80000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_M \
+ 0x7C000000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_high_sup_trim_lowv_S 26
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_M \
+ 0x03E00000
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_mem_flash_low_sup_trim_lowv_S 21
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_M \
+ 0x001FFFFF
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS8_NA24_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_PARAMETERS_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_M \
+ 0xFFFFFFC0
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_reserved_S 6
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p2v_lowv_override_ctrl \
+ 0x00000020
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_subreg_1p8v_lowv_override_ctrl \
+ 0x00000010
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_ilim_trim_lowv_efc_override_ctrl \
+ 0x00000008
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_slp_mode_lowv_fsm_override_ctrl \
+ 0x00000004
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_pwm_mode_lowv_fsm_override_ctrl \
+ 0x00000002
+
+#define HIB1P2_ANA_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_ana_en_lowv_fsm_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_FLASH_DCDC_PARAMETERS_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_M \
+ 0xFFFFFFFC
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_reserved_S 2
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_en_lowv_override_ctrl \
+ 0x00000002
+
+#define HIB1P2_FLASH_DCDC_PARAMETERS_OVERRIDE_mem_dcdc_flash_ilim_trim_lowv_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_VTRIM_CFG register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_M \
+ 0xFF000000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_reserved_S 24
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_M \
+ 0x00FC0000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_run_vtrim_S 18
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_M \
+ 0x0003F000
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_dslp_vtrim_S 12
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_M \
+ 0x00000FC0
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_mem_dcdc_dig_lpds_vtrim_S 6
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_M \
+ 0x0000003F
+
+#define HIB1P2_DIG_DCDC_VTRIM_CFG_Spare_RW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_DIG_DCDC_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_M \
+ 0xFFFF8000
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_reserved_S 15
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_M \
+ 0x00007000
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_cot_to_vtrim_S 12
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_M \
+ 0x00000E00
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_enter_vtrim_to_sleep_S 9
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_M \
+ 0x000001C0
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_sleep_to_vtrim_S 6
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_M \
+ 0x00000038
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_vtrim_to_cot_S 3
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_M \
+ 0x00000007
+
+#define HIB1P2_DIG_DCDC_FSM_PARAMETERS_mem_dcdc_dig_dslp_exit_cot_to_run_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_ANA_DCDC_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_reserved_S 3
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_M \
+ 0x00000007
+
+#define HIB1P2_ANA_DCDC_FSM_PARAMETERS_mem_dcdc_ana_dslp_exit_sleep_to_run_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SRAM_SKA_LDO_FSM_PARAMETERS register.
+//
+//******************************************************************************
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_M \
+ 0xFFFFFFC0
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_reserved_S 6
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_M \
+ 0x00000038
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_ska_ldo_en_to_sram_ldo_dis_S 3
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_M \
+ 0x00000007
+
+#define HIB1P2_SRAM_SKA_LDO_FSM_PARAMETERS_mem_sram_ldo_en_to_ska_ldo_dis_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_BGAP_DUTY_CYCLING_EXIT_CFG register.
+//
+//******************************************************************************
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_reserved_S 3
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_M \
+ 0x00000007
+
+#define HIB1P2_BGAP_DUTY_CYCLING_EXIT_CFG_mem_bgap_duty_cycling_exit_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_CM_OSC_16M_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_CM_OSC_16M_CONFIG_reserved_M \
+ 0xFFFC0000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_reserved_S 18
+#define HIB1P2_CM_OSC_16M_CONFIG_cm_clk_good_16m \
+ 0x00020000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_en_osc_16m \
+ 0x00010000
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_M \
+ 0x0000FC00
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_trim_S 10
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_M \
+ 0x000003F0
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_16m_spare_S 4
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_osc_en_sli_16m \
+ 0x00000008
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_M \
+ 0x00000007
+
+#define HIB1P2_CM_OSC_16M_CONFIG_mem_cm_sli_16m_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_SOP_SENSE_VALUE register.
+//
+//******************************************************************************
+#define HIB1P2_SOP_SENSE_VALUE_reserved_M \
+ 0xFFFFFF00
+
+#define HIB1P2_SOP_SENSE_VALUE_reserved_S 8
+#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_M \
+ 0x000000FF
+
+#define HIB1P2_SOP_SENSE_VALUE_sop_sense_value_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_RTC_TIMER_LSW_1P2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_RTC_TIMER_LSW_1P2_hib_rtc_timer_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_RTC_TIMER_MSW_1P2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_RTC_TIMER_MSW_1P2_hib_rtc_timer_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_BGAP_TRIM_OVERRIDES register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_M \
+ 0xFF800000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_reserved_S 23
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_ctrl \
+ 0x00400000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_M \
+ 0x003FC000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_mag_trim_override_S 14
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_ctrl \
+ 0x00002000
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_M \
+ 0x00001FC0
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_temp_trim_override_S 6
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_ctrl \
+ 0x00000020
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_M \
+ 0x0000001F
+
+#define HIB1P2_HIB1P2_BGAP_TRIM_OVERRIDES_mem_bgap_rtrim_override_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_EFUSE_READ_REG0 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_M \
+ 0xFFFFFFFF // Corresponds to ROW_12 of
+ // FUSEFARM. [7:0] :
+ // DCDC_DIG_ILIM_TRIM_LOWV(7:0)
+ // [15:8] :
+ // DCDC_ANA_ILIM_TRIM_LOWV(7:0)
+ // [23:16] :
+ // DCDC_FLASH_ILIM_TRIM_LOWV(7:0)
+ // [24:24] : DTHE SHA DISABLE
+ // [25:25] : DTHE DES DISABLE
+ // [26:26] : DTHE AES DISABLE
+ // [31:27] : HD_BG_RTRIM (4:0)
+
+#define HIB1P2_HIB1P2_EFUSE_READ_REG0_FUSEFARM_ROW_12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_EFUSE_READ_REG1 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_M \
+ 0xFFFFFFFF // Corresponds to ROW_13 of the
+ // FUSEFARM. [7:0] : HD_BG_MAG_TRIM
+ // (7:0) [14:8] : HD_BG_TEMP_TRIM
+ // (6:0) [15:15] : GREYOUT ENABLE
+ // DUTY CYCLING [31:16] :
+ // Reserved/Checksum
+
+#define HIB1P2_HIB1P2_EFUSE_READ_REG1_FUSEFARM_ROW_13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB1P2_POR_TEST_CTRL register.
+//
+//******************************************************************************
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_M \
+ 0xFFFFFF00
+
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_reserved_S 8
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_M \
+ 0x000000FF
+
+#define HIB1P2_HIB1P2_POR_TEST_CTRL_mem_prcm_por_test_ctrl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG0 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_reserved_S 16
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_M \
+ 0x0000FF00
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_time_S 8
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_M \
+ 0x000000FE
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_NU1_S 1
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG0_mem_cfg_calib_start \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CALIB_CFG1 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_M \
+ 0xFFF00000
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_reserved_S 20
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_M \
+ 0x000FFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_CALIB_CFG1_fast_calib_count_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_CFG2 register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_M \
+ 0xFFFFFE00
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_reserved_S 9
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_hib_unload \
+ 0x00000100
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_M \
+ 0x000000FC
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_NU1_S 2
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_tsf_adj \
+ 0x00000002
+
+#define HIB1P2_HIB_TIMER_SYNC_CFG2_mem_cfg_update_tsf \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_ADJ_VAL register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_ADJ_VAL_mem_tsf_adj_val_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_LSW_rtc_gts_timestamp_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_reserved_S 16
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_TIMER_RTC_GTS_TIMESTAMP_MSW_rtc_gts_timestamp_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_LSW_rtc_wup_timestamp_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_reserved_S 16
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_M \
+ 0x0000FFFF
+
+#define HIB1P2_HIB_TIMER_RTC_WUP_TIMESTAMP_MSW_rtc_wup_timestamp_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_WAKE_OFFSET_ERR register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_M \
+ 0xFFFFF000
+
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_reserved_S 12
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_M \
+ 0x00000FFF
+
+#define HIB1P2_HIB_TIMER_SYNC_WAKE_OFFSET_ERR_wup_offset_error_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_LSW_tsf_curr_val_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW register.
+//
+//******************************************************************************
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_HIB_TIMER_SYNC_TSF_CURR_VAL_MSW_tsf_curr_val_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the HIB1P2_O_CM_SPARE register.
+//
+//******************************************************************************
+#define HIB1P2_CM_SPARE_CM_SPARE_OUT_M \
+ 0xFF000000
+
+#define HIB1P2_CM_SPARE_CM_SPARE_OUT_S 24
+#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_M \
+ 0x00FF0000
+
+#define HIB1P2_CM_SPARE_MEM_CM_TEST_CTRL_S 16
+#define HIB1P2_CM_SPARE_MEM_CM_SPARE_M \
+ 0x0000FFFF
+
+#define HIB1P2_CM_SPARE_MEM_CM_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_PORPOL_SPARE register.
+//
+//******************************************************************************
+#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_M \
+ 0xFFFFFFFF
+
+#define HIB1P2_PORPOL_SPARE_MEM_PORPOL_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_DIG_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_DIG_DCDC_CLK_CONFIG_MEM_DIG_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_ANA_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_ANA_DCDC_CLK_CONFIG_MEM_ANA_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_FLASH_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_FLASH_DCDC_CLK_CONFIG_MEM_FLASH_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_PA_DCDC_CLK_CONFIG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_ENABLE \
+ 0x00000100
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_OFF_TIME_S 4
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_PA_DCDC_CLK_CONFIG_MEM_PA_DCDC_CLK_PLLGEN_ON_TIME_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_VNWA_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE_CTRL \
+ 0x00000002
+
+#define HIB1P2_MEM_SLDO_VNWA_OVERRIDE_MEM_SLDO_EN_TOP_VNWA_OVERRIDE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE_CTRL \
+ 0x00000002
+
+#define HIB1P2_MEM_BGAP_DUTY_CYCLING_ENABLE_OVERRIDE_MEM_BGAP_DUTY_CYCLING_OVERRIDE \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_HIB_FSM_DEBUG register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_M \
+ 0x00000700
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_SRAM_PS_S 8
+#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_M \
+ 0x000000F0
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_ANA_DCDC_PS_S 4
+#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_M \
+ 0x0000000F
+
+#define HIB1P2_MEM_HIB_FSM_DEBUG_DIG_DCDC_PS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_VNWA_SW_CTRL register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_M \
+ 0x000FFFFF
+
+#define HIB1P2_MEM_SLDO_VNWA_SW_CTRL_MEM_SLDO_VNWA_SW_CTRL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_SLDO_WEAK_PROCESS register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_SLDO_WEAK_PROCESS_MEM_SLDO_WEAK_PROCESS \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_PA_DCDC_OV_UV_STATUS register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_PA_DCDC_OV_UV_STATUS_dcdc_pa_ov_prot_out_lowv \
+ 0x00000002
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB1P2_O_MEM_CM_TEST_MODE register.
+//
+//******************************************************************************
+#define HIB1P2_MEM_CM_TEST_MODE_mem_cm_test_mode \
+ 0x00000001
+
+
+
+
+#endif // __HW_HIB1P2_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_hib3p3.h b/ext/hal/ti/cc3220sdk/inc/hw_hib3p3.h
new file mode 100644
index 0000000..42cde5b
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_hib3p3.h
@@ -0,0 +1,1136 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_HIB3P3_H__
+#define __HW_HIB3P3_H__
+
+//*****************************************************************************
+//
+// The following are defines for the HIB3P3 register offsets.
+//
+//*****************************************************************************
+#define HIB3P3_O_MEM_HIB_REQ 0x00000000
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE \
+ 0x00000004
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_RESET \
+ 0x00000008
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_READ \
+ 0x0000000C
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_LSW \
+ 0x00000010
+
+#define HIB3P3_O_MEM_HIB_RTC_TIMER_MSW \
+ 0x00000014
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_EN \
+ 0x00000018
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF \
+ 0x0000001C
+
+#define HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF \
+ 0x00000020
+
+#define HIB3P3_O_MEM_INT_OSC_CONF \
+ 0x0000002C
+
+#define HIB3P3_O_MEM_XTAL_OSC_CONF \
+ 0x00000034
+
+#define HIB3P3_O_MEM_BGAP_PARAMETERS0 \
+ 0x00000038
+
+#define HIB3P3_O_MEM_BGAP_PARAMETERS1 \
+ 0x0000003C
+
+#define HIB3P3_O_MEM_HIB_DETECTION_STATUS \
+ 0x00000040
+
+#define HIB3P3_O_MEM_HIB_MISC_CONTROLS \
+ 0x00000044
+
+#define HIB3P3_O_MEM_HIB_CONFIG 0x00000050
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE \
+ 0x00000054
+
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF \
+ 0x00000058
+
+#define HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF \
+ 0x0000005C
+
+#define HIB3P3_O_MEM_HIB_UART_CONF \
+ 0x00000400
+
+#define HIB3P3_O_MEM_GPIO_WAKE_EN \
+ 0x00000404
+
+#define HIB3P3_O_MEM_GPIO_WAKE_CONF \
+ 0x00000408
+
+#define HIB3P3_O_MEM_PAD_OEN_RET33_CONF \
+ 0x0000040C
+
+#define HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF \
+ 0x00000410
+
+#define HIB3P3_O_MEM_JTAG_CONF 0x00000414
+#define HIB3P3_O_MEM_HIB_REG0 0x00000418
+#define HIB3P3_O_MEM_HIB_REG1 0x0000041C
+#define HIB3P3_O_MEM_HIB_REG2 0x00000420
+#define HIB3P3_O_MEM_HIB_REG3 0x00000424
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 \
+ 0x0000045C
+
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 \
+ 0x00000460
+
+#define HIB3P3_O_MEM_HIB_MISC_CONFIG \
+ 0x00000464
+
+#define HIB3P3_O_MEM_HIB_WAKE_STATUS \
+ 0x00000468
+
+#define HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL \
+ 0x0000046C
+
+#define HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 \
+ 0x00000470
+
+#define HIB3P3_O_HIBANA_SPARE_LOWV \
+ 0x00000474
+
+#define HIB3P3_O_HIB_TMUX_CTRL 0x00000478
+#define HIB3P3_O_HIB_1P2_1P8_LDO_TRIM \
+ 0x0000047C
+
+#define HIB3P3_O_HIB_COMP_TRIM 0x00000480
+#define HIB3P3_O_HIB_EN_TS 0x00000484
+#define HIB3P3_O_HIB_1P8V_DET_EN \
+ 0x00000488
+
+#define HIB3P3_O_HIB_VBAT_MON_EN \
+ 0x0000048C
+
+#define HIB3P3_O_HIB_NHIB_ENABLE \
+ 0x00000490
+
+#define HIB3P3_O_HIB_UART_RTS_SW_ENABLE \
+ 0x00000494
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REQ register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REQ_reserved_M \
+ 0xFFFFFE00
+
+#define HIB3P3_MEM_HIB_REQ_reserved_S 9
+#define HIB3P3_MEM_HIB_REQ_NU1_M \
+ 0x000001FC
+
+#define HIB3P3_MEM_HIB_REQ_NU1_S 2
+#define HIB3P3_MEM_HIB_REQ_mem_hib_clk_disable \
+ 0x00000002 // 1 - Specifies that the Hiberante
+ // mode is without clocks ; 0 -
+ // Specified that the Hibernate mode
+ // is with clocks This register will
+ // be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+#define HIB3P3_MEM_HIB_REQ_mem_hib_req \
+ 0x00000001 // 1 - Request for hibernate mode
+ // (This is an auto-clear bit) ; 0 -
+ // Donot request for hibernate mode
+ // This register will be reset
+ // during Hibernate -WO-Clks mode
+ // (but not during Hibernate-W-Clks
+ // mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_ENABLE_mem_hib_rtc_timer_enable \
+ 0x00000001 // 1 - Enable the RTC timer to
+ // start running ; 0 - Keep the RTC
+ // timer disabled This register will
+ // be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_RESET register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_RESET_mem_hib_rtc_timer_reset \
+ 0x00000001 // 1 - Reset the RTC timer ; 0 -
+ // Donot reset the RTC timer. This
+ // is an auto-clear bit. This
+ // register will be reset during
+ // Hibernate -WO-Clks mode (but not
+ // during Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_READ register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_TIMER_READ_mem_hib_rtc_timer_read \
+ 0x00000001 // 1 - Latch the running RTC timer
+ // into local registers. After
+ // programming this bit to 1, the
+ // F/w can read the latched RTC
+ // timer values from
+ // MEM_HIB_RTC_TIMER_LSW and
+ // MEM_HIB_RTC_TIMER_MSW. Before the
+ // F/w (APPS or NWP) wants to read
+ // the RTC-Timer, it has to program
+ // this bit to 1, then only read the
+ // MSW and LSW values. This is an
+ // auto-clear bit. This register
+ // will be reset during Hibernate
+ // -WO-Clks mode (but not during
+ // Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_LSW register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_M \
+ 0xFFFFFFFF // Lower 32b value of the latched
+ // RTC-Timer.
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_LSW_hib_rtc_timer_lsw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_TIMER_MSW register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_reserved_S 16
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_M \
+ 0x0000FFFF // Upper 32b value of the latched
+ // RTC-Timer.
+
+#define HIB3P3_MEM_HIB_RTC_TIMER_MSW_hib_rtc_timer_msw_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_EN register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_reserved_S 1
+#define HIB3P3_MEM_HIB_RTC_WAKE_EN_mem_hib_rtc_wake_en \
+ 0x00000001 // 1 - Enable the RTC timer based
+ // wakeup during Hibernate mode ; 0
+ // - Disable the RTC timer based
+ // wakeup during Hibernate mode This
+ // register will be reset during
+ // Hibernate-WO-Clks mode (but not
+ // during Hibernate-W-Clks mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_LSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_M \
+ 0xFFFFFFFF // Configuration for RTC-Timer
+ // Wakeup (Lower 32b word)
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_LSW_CONF_mem_hib_rtc_wake_lsw_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_WAKE_MSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_reserved_S 16
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_M \
+ 0x0000FFFF // Configuration for RTC-Timer
+ // Wakeup (Upper 16b word)
+
+#define HIB3P3_MEM_HIB_RTC_WAKE_MSW_CONF_mem_hib_rtc_wake_msw_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_INT_OSC_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_INT_OSC_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_INT_OSC_CONF_reserved_S 16
+#define HIB3P3_MEM_INT_OSC_CONF_cm_clk_good_32k_int \
+ 0x00008000 // 1 - Internal 32kHz Oscillator is
+ // valid ; 0 - Internal 32k
+ // oscillator clk is not valid
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_M \
+ 0x00007E00
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_spare_S 9
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k_override_ctrl \
+ 0x00000100 // When 1, the INT_32K_OSC_EN comes
+ // from bit [0] of this register,
+ // else comes from the FSM. This
+ // register will be reset during
+ // Hibernate-WO-Clks mode (but not
+ // during Hibernate-W-Clks mode)
+
+#define HIB3P3_MEM_INT_OSC_CONF_NU1 \
+ 0x00000080
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_M \
+ 0x0000007E
+
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_intosc_32k_trim_S 1
+#define HIB3P3_MEM_INT_OSC_CONF_mem_cm_en_intosc_32k \
+ 0x00000001 // Override value for INT_OSC_EN.
+ // Applicable only when bit [3] of
+ // this register is set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_XTAL_OSC_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_M \
+ 0xFFF00000
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_reserved_S 20
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k_override_ctrl \
+ 0x00080000 // When 1, the SLICER_EN comes from
+ // bit [10] of this register, else
+ // comes from the FSM.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k_override_ctrl \
+ 0x00040000 // When 1, the XTAL_EN comes from
+ // bit [0] of this register, else
+ // comes from the FSM.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_cm_clk_good_xtal \
+ 0x00020000 // 1 - XTAL Clk is good ; 0 - XTAL
+ // Clk is yet to be valid.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_M \
+ 0x0001F800
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_xtal_trim_S 11
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_sli_32k \
+ 0x00000400 // SLICER_EN Override value :
+ // Applicable only when bit [19] of
+ // this register is set to 1.
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_M \
+ 0x00000380
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_sli_32k_trim_S 7
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_M \
+ 0x00000070
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_fref_32k_slicer_itrim_S 4
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_fref_32k_slicer \
+ 0x00000008
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_M \
+ 0x00000006
+
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_input_sense_S 1
+#define HIB3P3_MEM_XTAL_OSC_CONF_mem_cm_en_xtal_32k \
+ 0x00000001 // XTAL_EN Override value :
+ // Applicable only when bit [18] of
+ // this register is set to 1.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_BGAP_PARAMETERS0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_M \
+ 0xFFF80000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_reserved_S 19
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_en_seq \
+ 0x00040000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_M \
+ 0x0001C000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_vbok4bg_comp_trim_S 14
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbat_ok_4bg \
+ 0x00001000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp \
+ 0x00000800
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_en_vbok4bg_comp_ref \
+ 0x00000400
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_M \
+ 0x000003FF
+
+#define HIB3P3_MEM_BGAP_PARAMETERS0_mem_bgap_spare_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_BGAP_PARAMETERS1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_M \
+ 0xE0000000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_reserved_S 29
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_M \
+ 0x1F000000
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_act_iref_itrim_S 24
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_act_iref \
+ 0x00000008
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_v2i \
+ 0x00000004
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en_cap_sw \
+ 0x00000002
+
+#define HIB3P3_MEM_BGAP_PARAMETERS1_mem_bgap_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_DETECTION_STATUS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_M \
+ 0xFFFFFF80
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_reserved_S 7
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_ana_status \
+ 0x00000040 // 1 - 1.8 V supply forced mode.
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_forced_flash_status \
+ 0x00000004 // 1 - 3.3 V supply forced mode for
+ // Flash supply
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_ext_clk_det_out_status \
+ 0x00000002 // 1 - Forced clock mode
+
+#define HIB3P3_MEM_HIB_DETECTION_STATUS_hib_xtal_det_out_status \
+ 0x00000001 // 1 - XTAL clock mode
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_MISC_CONTROLS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_M \
+ 0xFFFFF800
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_reserved_S 11
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp \
+ 0x00000400
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_pok_por_comp_ref \
+ 0x00000200
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_M \
+ 0x000001C0
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_pok_por_comp_trim_S 6
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_NU1 \
+ 0x00000020
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_flash_det_en \
+ 0x00000010
+
+#define HIB3P3_MEM_HIB_MISC_CONTROLS_mem_hib_en_tmux \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_CONFIG register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_M \
+ 0xFF000000
+
+#define HIB3P3_MEM_HIB_CONFIG_TOP_MUX_CTRL_SOP_SPIO_S 24
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED3 \
+ 0x00080000 // 1 - Enable VDD_FLASH_INDP_PAD
+ // for digital path (SHARED4) ; 0 -
+ // Disable VDD_FLASH_INDP_PAD for
+ // digital path (SHARED4) ; Before
+ // programming this bit to 1, ensure
+ // that the device is in FORCED 3.3
+ // supply Mode, which can be
+ // inferred from the register :
+ // MEM_HIB_DETECTION_STATUS : 0x0040
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED2 \
+ 0x00040000 // 1 - Enable the
+ // VDD_FB_GPIO_MUX_PAD for digital
+ // path (SHARED3) ; 0 - Disable the
+ // VDD_FB_GPIO_MUX_PAD for digital
+ // path (SHARED3) ; This pin can be
+ // used only in modes other than
+ // SOP("111")
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED1 \
+ 0x00020000 // 1 - Enable the PM_TEST_PAD for
+ // digital GPIO path (SHARED2) ; 0 -
+ // Disable the PM_TEST_PAD for
+ // digital GPIO path (SHARED2) This
+ // pin can be used for digital only
+ // in modes other then SOP-111
+
+#define HIB3P3_MEM_HIB_CONFIG_EN_ANA_DIG_SHARED0 \
+ 0x00010000 // 1 - Enable the XTAL_N pin
+ // digital GPIO path (SHARED1); 0 -
+ // Disable the XTAL_N pin digital
+ // GPIO path (SHARED1). Before
+ // programming this bit to 1, ensure
+ // that the device is in FORCED CLK
+ // Mode, which can inferred from the
+ // register :
+ // MEM_HIB_DETECTION_STATUS :
+ // 0x0040.
+
+#define HIB3P3_MEM_HIB_CONFIG_mem_hib_xtal_enable \
+ 0x00000100 // 1 - Enable the XTAL Clock ; 0 -
+ // Donot enable the XTAL Clock. This
+ // bit has to be programmed to 1 (by
+ // APPS Devinit F/w), during exit
+ // from OFF or Hib_wo_clks modes,
+ // after checking if the slow_clk
+ // mode is XTAL_CLK mode. Once
+ // enabled the XTAL will be disabled
+ // only after entering HIB_WO_CLKS
+ // mode. This register will be reset
+ // during Hibernate -WO-Clks mode
+ // (but not during Hibernate-W-Clks
+ // mode).
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_ENABLE_HIB_RTC_IRQ_ENABLE \
+ 0x00000001 // 1 - Enable the HIB RTC - IRQ ; 0
+ // - Disable the HIB RTC - IRQ
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_LSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_M \
+ 0xFFFFFFFF // Configuration for LSW of the
+ // RTC-Timestamp at which interrupt
+ // need to be generated
+
+#define HIB3P3_MEM_HIB_RTC_IRQ_LSW_CONF_HIB_RTC_IRQ_LSW_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_RTC_IRQ_MSW_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_M \
+ 0x0000FFFF // Configuration for MSW of thr
+ // RTC-Timestamp at which the
+ // interrupt need to be generated
+
+#define HIB3P3_MEM_HIB_RTC_IRQ_MSW_CONF_HIB_RTC_IRQ_MSW_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_UART_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_UART_CONF_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_MEM_HIB_UART_CONF_reserved_S 1
+#define HIB3P3_MEM_HIB_UART_CONF_mem_hib_uart_wake_en \
+ 0x00000001 // 1 - Enable the UART-Autonomous
+ // mode wakeup during Hibernate mode
+ // ; This is an auto-clear bit, once
+ // programmed to 1, it will latched
+ // into an internal register which
+ // remain asserted until the
+ // Hib-wakeup is initiated.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_GPIO_WAKE_EN register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_M \
+ 0xFFFFFF00
+
+#define HIB3P3_MEM_GPIO_WAKE_EN_reserved_S 8
+#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_M \
+ 0x000000FF // 1 - Enable the GPIO-Autonomous
+ // mode wakeup during Hibernate mode
+ // ; This is an auto-clear bit, once
+ // programmed to 1, it will latched
+ // into an internal register which
+ // remain asserted until the
+ // Hib-wakeup is initiated.
+
+#define HIB3P3_MEM_GPIO_WAKE_EN_mem_gpio_wake_en_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_GPIO_WAKE_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_GPIO_WAKE_CONF_reserved_S 16
+#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_M \
+ 0x0000FFFF // Configuration to say whether the
+ // GPIO wakeup has to happen on
+ // Level0 or falling-edge for the
+ // given group. “00� – Level0 “01� –
+ // Level1 “10�- Fall-edge “11�-
+ // Rise-edge [1:0] – Conf for GPIO0
+ // [3:2] – Conf for GPIO1 [5:4] –
+ // Conf for GPIO2 [7:6] – Conf for
+ // GPIO3 [9:8] – Conf for GPIO4
+ // [11:10] – Conf for GPIO5 [13:12]
+ // – Conf for GPIO6
+
+#define HIB3P3_MEM_GPIO_WAKE_CONF_mem_gpio_wake_conf_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_PAD_OEN_RET33_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_mem_pad_oen_ret33_override_ctrl \
+ 0x00000004 // 1 - Override the OEN33 and RET33
+ // controls of GPIOs during
+ // SOP-Bootdebug mode ; 0 - Donot
+ // override the OEN33 and RET33
+ // controls of GPIOs during
+ // SOP-Bootdebug mode
+
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_PAD_OEN_RET33_CONF_PAD_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_UART_RTS_OEN_RET33_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_mem_uart_nrts_oen_ret33_override_ctrl \
+ 0x00000004 // 1 - Override the OEN33 and RET33
+ // controls of UART NRTS GPIO during
+ // SOP-Bootdebug mode ; 0 - Donot
+ // override the OEN33 and RET33
+ // controls of UART NRTS GPIO during
+ // SOP-Bootdebug mode
+
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_UART_RTS_OEN_RET33_CONF_PAD_UART_RTS_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_JTAG_CONF register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_JTAG_CONF_mem_jtag1_oen_ret33_override_ctrl \
+ 0x00000200
+
+#define HIB3P3_MEM_JTAG_CONF_mem_jtag0_oen_ret33_override_ctrl \
+ 0x00000100
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_OEN33_CONF \
+ 0x00000008
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG1_RTS_RET33_CONF \
+ 0x00000004
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_OEN33_CONF \
+ 0x00000002
+
+#define HIB3P3_MEM_JTAG_CONF_PAD_JTAG0_RTS_RET33_CONF \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG0_mem_hib_reg0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG1_mem_hib_reg1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG2 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG2_mem_hib_reg2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_REG3 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_M \
+ 0xFFFFFFFF
+
+#define HIB3P3_MEM_HIB_REG3_mem_hib_reg3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG0 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_M \
+ 0xFFFF0000 // Configuration for the number of
+ // slow-clks between de-assertion of
+ // EN_BG_3P3V to assertion of
+ // EN_BG_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev0_to_ev1_time_S 16
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_NU1 \
+ 0x00008000
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_M \
+ 0x00006000 // Configuration for the number of
+ // slow-clks between assertion of
+ // EN_COMP_3P3V and assertion of
+ // EN_COMP_LATCH_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev3_to_ev4_time_S 13
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_M \
+ 0x00001800 // Configuration for the number of
+ // slow-clks between assertion of
+ // (EN_CAP_SW_3P3V,EN_COMP_REF) and
+ // assertion of (EN_COMP_3P3V)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev2_to_ev3_time_S 11
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_M \
+ 0x00000600 // Configuration for the number of
+ // slow-clks between assertion of
+ // (EN_BG_3P3V) and assertion of
+ // (EN_CAP_SW_3P3V,
+ // EN_COMP_REF_3P3V)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bdc_ev1_to_ev2_time_S 9
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_crude_ref_comp \
+ 0x00000100
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_ref_override_ctrl \
+ 0x00000080 // 1 - EN_VBOK4BG_REF comes from
+ // bit[10] of the register
+ // MEM_BGAP_PARAMETERS0 [0x0038]. 0
+ // - EN_VBOK4BG_REF comes directly
+ // from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_vbok4bg_comp_override_ctrl \
+ 0x00000040 // 1 - EN_VBOK4BG comes from
+ // bit[11] of the register
+ // MEM_BGAP_PARAMETERS0 [0x0038]. 0
+ // - EN_VBOK4BG comes directly from
+ // the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_v2i_override_ctrl \
+ 0x00000020 // 1 - EN_V2I comes from bit[2] of
+ // the register MEM_BGAP_PARAMETERS1
+ // [0x003C]. 0 - EN_V2I comes
+ // directly from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_por_comp_ref_override_ctrl \
+ 0x00000010 // 1 - EN_POR_COMP_REF comes from
+ // bit[9] of the register
+ // MEM_HIB_MISC_CONTROLS [0x0044]. 0
+ // - EN_POR_COMP_REF comes directly
+ // from the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_en_por_comp_override_ctrl \
+ 0x00000008 // 1 - EN_POR_COMP comes from
+ // bit[10] of the register
+ // MEM_HIB_MISC_CONTROLS [0x044]. 0
+ // - EN_POR_COMP comes directly from
+ // the Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_cap_sw_override_ctrl \
+ 0x00000004 // 1 - EN_CAP_SW comes from bit[1]
+ // of the register
+ // MEM_BGAP_PARAMETERS1 [0x003C]. 0
+ // - EN_CAP_SW comes directly from
+ // Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_bg_override_ctrl \
+ 0x00000002 // 1 - EN_BGAP comes from bit[0] of
+ // the register MEM_BGAP_PARAMETERS1
+ // [0x003C]. 0 - EN_BGAP comes
+ // directly from Hib-Sequencer.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG0_mem_act_iref_override_ctrl \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG1 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_M \
+ 0xFFFF0000
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_reserved_S 16
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_M \
+ 0x0000C000 // Configuration for number of
+ // slow-clks between de-assertion of
+ // EN_COMP_LATCH and assertion of
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_ev5_to_ev6_time_S 14
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_M \
+ 0x00003000 // Configuration for number of
+ // slow-clks between assertion of
+ // EN_COMP_REF to assertion of
+ // EN_COMP during HIB-Exit
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev1_to_ev2_time_S 12
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_M \
+ 0x00000C00 // TBD
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_ev1_time_S 10
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_M \
+ 0x00000300 // Configuration in number of
+ // slow-clks between assertion of
+ // (EN_BGAP_3P3V, EN_CAP_SW_3P3V,
+ // EN_ACT_IREF_3P3V, EN_COMP_REF) to
+ // assertion of EN_COMP_3P3V
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_bdc_to_active_ev0_to_active_S 8
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_M \
+ 0x000000C0 // Configuration in number of
+ // slow-clks between de-assertion of
+ // (EN_COMP_3P3V, EN_COMP_REF_3P3V,
+ // EN_ACT_IREF_3P3V, EN_CAP_SW_3P3V)
+ // to deassertion of EN_BGAP_3P3V.
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_mem_active_to_bdc_ev1_to_bdc_ev0_time_S 6
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_M \
+ 0x0000003F
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG1_NU1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_MISC_CONFIG register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_MISC_CONFIG_mem_en_pll_untrim_current \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_WAKE_STATUS register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_M \
+ 0x0000001E // "0100" - GPIO ; "0010" - RTC ;
+ // "0001" - UART Others - Reserved
+
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_src_S 1
+#define HIB3P3_MEM_HIB_WAKE_STATUS_hib_wake_status \
+ 0x00000001 // 1 - Wake from Hibernate ; 0 -
+ // Wake from OFF
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_LPDS_GPIO_SEL register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_M \
+ 0x00000007
+
+#define HIB3P3_MEM_HIB_LPDS_GPIO_SEL_HIB_LPDS_GPIO_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_MEM_HIB_SEQUENCER_CFG2 register.
+//
+//******************************************************************************
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_M \
+ 0xFFFFF800
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_reserved_S 11
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_M \
+ 0x00000600 // Deassertion of EN_COMP_LATCH_3P3
+ // to deassertion of (EN_COMP_3P3,
+ // EN_COMP_REF_3P3, EN_ACT_IREF_3P3,
+ // EN_CAP_SW_3P3)
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_active_to_bdc_ev0_to_active_to_bdc_ev1_time_S 9
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_M \
+ 0x000001C0 // Assertion of EN_COMP_LATCH_3P3
+ // to deassertion of
+ // EN_COMP_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev4_to_ev5_time_S 6
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_M \
+ 0x00000030 // Deassertion of (EN_CAP_SW_3P3,
+ // EN_COMP_REF_3P3, EN_COMP_3P3,
+ // EN_COMP_OUT_LATCH_3P3) to
+ // deassertion of EN_BGAP_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_ev6_to_ev7_time_S 4
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_M \
+ 0x0000000C // Assertion of EN_COMP_3P3 to
+ // assertion of EN_COMPOUT_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_bdc_to_active_ev1_to_ev2_time_S 2
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_M \
+ 0x00000003 // Assertion of EN_COMP_3P3 to
+ // assertion of EN_COMPOUT_LATCH_3P3
+
+#define HIB3P3_MEM_HIB_SEQUENCER_CFG2_mem_hib_to_active_ev2_to_ev3_time_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIBANA_SPARE_LOWV register.
+//
+//******************************************************************************
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_M \
+ 0xFFC00000
+
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare1_S 22
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_M \
+ 0x0001FFFF
+
+#define HIB3P3_HIBANA_SPARE_LOWV_mem_hibana_spare0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_TMUX_CTRL register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_TMUX_CTRL_reserved_M \
+ 0xFFFFFC00
+
+#define HIB3P3_HIB_TMUX_CTRL_reserved_S 10
+#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_M \
+ 0x000003FF
+
+#define HIB3P3_HIB_TMUX_CTRL_mem_hd_tmux_cntrl_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_1P2_1P8_LDO_TRIM register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_M \
+ 0xFFFFF000
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_reserved_S 12
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override_ctrl \
+ 0x00000800
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override_ctrl \
+ 0x00000400
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_en_override \
+ 0x00000200
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_en_override \
+ 0x00000100
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_M \
+ 0x000000F0
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p2_ldo_vtrim_S 4
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_M \
+ 0x0000000F
+
+#define HIB3P3_HIB_1P2_1P8_LDO_TRIM_mem_hd_1p8_ldo_vtrim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_COMP_TRIM register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_COMP_TRIM_reserved_M \
+ 0xFFFFFFF8
+
+#define HIB3P3_HIB_COMP_TRIM_reserved_S 3
+#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_M \
+ 0x00000007
+
+#define HIB3P3_HIB_COMP_TRIM_mem_hd_comp_trim_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_EN_TS register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_EN_TS_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_HIB_EN_TS_reserved_S 1
+#define HIB3P3_HIB_EN_TS_mem_hd_en_ts \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_1P8V_DET_EN register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_1P8V_DET_EN_reserved_M \
+ 0xFFFFFFFE
+
+#define HIB3P3_HIB_1P8V_DET_EN_reserved_S 1
+#define HIB3P3_HIB_1P8V_DET_EN_mem_hib_1p8v_det_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_VBAT_MON_EN register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_VBAT_MON_EN_reserved_M \
+ 0xFFFFFFFC
+
+#define HIB3P3_HIB_VBAT_MON_EN_reserved_S 2
+#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_del_en \
+ 0x00000002
+
+#define HIB3P3_HIB_VBAT_MON_EN_mem_hib_vbat_mon_en \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_NHIB_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_NHIB_ENABLE_mem_hib_nhib_enable \
+ 0x00000001
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// HIB3P3_O_HIB_UART_RTS_SW_ENABLE register.
+//
+//******************************************************************************
+#define HIB3P3_HIB_UART_RTS_SW_ENABLE_mem_hib_uart_rts_sw_enable \
+ 0x00000001
+
+
+
+
+#endif // __HW_HIB3P3_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_ints.h b/ext/hal/ti/cc3220sdk/inc/hw_ints.h
new file mode 100644
index 0000000..af2c02f
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_ints.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on CC3200.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_GPIOA0 16 // GPIO Port S0
+#define INT_GPIOA1 17 // GPIO Port S1
+#define INT_GPIOA2 18 // GPIO Port S2
+#define INT_GPIOA3 19 // GPIO Port S3
+#define INT_UARTA0 21 // UART0 Rx and Tx
+#define INT_UARTA1 22 // UART1 Rx and Tx
+#define INT_I2CA0 24 // I2C controller
+#define INT_ADCCH0 30 // ADC Sequence 0
+#define INT_ADCCH1 31 // ADC Sequence 1
+#define INT_ADCCH2 32 // ADC Sequence 2
+#define INT_ADCCH3 33 // ADC Sequence 3
+#define INT_WDT 34 // Watchdog Timer0
+#define INT_TIMERA0A 35 // Timer 0 subtimer A
+#define INT_TIMERA0B 36 // Timer 0 subtimer B
+#define INT_TIMERA1A 37 // Timer 1 subtimer A
+#define INT_TIMERA1B 38 // Timer 1 subtimer B
+#define INT_TIMERA2A 39 // Timer 2 subtimer A
+#define INT_TIMERA2B 40 // Timer 2 subtimer B
+#define INT_FLASH 45 // FLASH Control
+#define INT_TIMERA3A 51 // Timer 3 subtimer A
+#define INT_TIMERA3B 52 // Timer 3 subtimer B
+#define INT_UDMA 62 // uDMA controller
+#define INT_UDMAERR 63 // uDMA Error
+#define INT_SHA 164 // SHA
+#define INT_AES 167 // AES
+#define INT_DES 169 // DES
+#define INT_MMCHS 175 // SDIO
+#define INT_I2S 177 // McAPS
+#define INT_CAMERA 179 // Camera
+#define INT_NWPIC 187 // Interprocessor communication
+#define INT_PRCM 188 // Power, Reset and Clock Module
+#define INT_SSPI 191 // Shared SPI
+#define INT_GSPI 192 // Generic SPI
+#define INT_LSPI 193 // Link SPI
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS 195 //The above number plus 2?
+
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+
+#endif // __HW_INTS_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_memmap.h b/ext/hal/ti/cc3220sdk/inc/hw_memmap.h
new file mode 100644
index 0000000..1e26774
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_memmap.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals on the slave_1 interface.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x01000000
+#define SRAM_BASE 0x20000000
+#define WDT_BASE 0x40000000
+#define GPIOA0_BASE 0x40004000
+#define GPIOA1_BASE 0x40005000
+#define GPIOA2_BASE 0x40006000
+#define GPIOA3_BASE 0x40007000
+#define GPIOA4_BASE 0x40024000
+#define UARTA0_BASE 0x4000C000
+#define UARTA1_BASE 0x4000D000
+#define I2CA0_BASE 0x40020000
+#define TIMERA0_BASE 0x40030000
+#define TIMERA1_BASE 0x40031000
+#define TIMERA2_BASE 0x40032000
+#define TIMERA3_BASE 0x40033000
+#define STACKDIE_CTRL_BASE 0x400F5000
+#define COMMON_REG_BASE 0x400F7000
+#define FLASH_CONTROL_BASE 0x400FD000
+#define SYSTEM_CONTROL_BASE 0x400FE000
+#define UDMA_BASE 0x400FF000
+#define SDHOST_BASE 0x44010000
+#define CAMERA_BASE 0x44018000
+#define I2S_BASE 0x4401C000
+#define SSPI_BASE 0x44020000
+#define GSPI_BASE 0x44021000
+#define LSPI_BASE 0x44022000
+#define ARCM_BASE 0x44025000
+#define APPS_CONFIG_BASE 0x44026000
+#define GPRCM_BASE 0x4402D000
+#define OCP_SHARED_BASE 0x4402E000
+#define ADC_BASE 0x4402E800
+#define HIB1P2_BASE 0x4402F000
+#define HIB3P3_BASE 0x4402F800
+#define DTHE_BASE 0x44030000
+#define SHAMD5_BASE 0x44035000
+#define AES_BASE 0x44037000
+#define DES_BASE 0x44039000
+
+
+#endif // __HW_MEMMAP_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_ocp_shared.h b/ext/hal/ti/cc3220sdk/inc/hw_ocp_shared.h
new file mode 100644
index 0000000..79b5f76
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_ocp_shared.h
@@ -0,0 +1,3443 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_OCP_SHARED_H__
+#define __HW_OCP_SHARED_H__
+
+//*****************************************************************************
+//
+// The following are defines for the OCP_SHARED register offsets.
+//
+//*****************************************************************************
+#define OCP_SHARED_O_SEMAPHORE1 0x00000000
+#define OCP_SHARED_O_SEMAPHORE2 0x00000004
+#define OCP_SHARED_O_SEMAPHORE3 0x00000008
+#define OCP_SHARED_O_SEMAPHORE4 0x0000000C
+#define OCP_SHARED_O_SEMAPHORE5 0x00000010
+#define OCP_SHARED_O_SEMAPHORE6 0x00000014
+#define OCP_SHARED_O_SEMAPHORE7 0x00000018
+#define OCP_SHARED_O_SEMAPHORE8 0x0000001C
+#define OCP_SHARED_O_SEMAPHORE9 0x00000020
+#define OCP_SHARED_O_SEMAPHORE10 \
+ 0x00000024
+
+#define OCP_SHARED_O_SEMAPHORE11 \
+ 0x00000028
+
+#define OCP_SHARED_O_SEMAPHORE12 \
+ 0x0000002C
+
+#define OCP_SHARED_O_IC_LOCKER_ID \
+ 0x00000030
+
+#define OCP_SHARED_O_MCU_SEMAPHORE_PEND \
+ 0x00000034
+
+#define OCP_SHARED_O_WL_SEMAPHORE_PEND \
+ 0x00000038
+
+#define OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY \
+ 0x0000003C
+
+#define OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY \
+ 0x00000040
+
+#define OCP_SHARED_O_CC3XX_CONFIG_CTRL \
+ 0x00000044
+
+#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB \
+ 0x00000048
+
+#define OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB \
+ 0x0000004C
+
+#define OCP_SHARED_O_WLAN_ELP_WAKE_EN \
+ 0x00000050
+
+#define OCP_SHARED_O_DEVINIT_ROM_START_ADDR \
+ 0x00000054
+
+#define OCP_SHARED_O_DEVINIT_ROM_END_ADDR \
+ 0x00000058
+
+#define OCP_SHARED_O_SSBD_SEED 0x0000005C
+#define OCP_SHARED_O_SSBD_CHK 0x00000060
+#define OCP_SHARED_O_SSBD_POLY_SEL \
+ 0x00000064
+
+#define OCP_SHARED_O_SPARE_REG_0 \
+ 0x00000068
+
+#define OCP_SHARED_O_SPARE_REG_1 \
+ 0x0000006C
+
+#define OCP_SHARED_O_SPARE_REG_2 \
+ 0x00000070
+
+#define OCP_SHARED_O_SPARE_REG_3 \
+ 0x00000074
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_0 \
+ 0x000000A0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_1 \
+ 0x000000A4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_2 \
+ 0x000000A8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_3 \
+ 0x000000AC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_4 \
+ 0x000000B0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_5 \
+ 0x000000B4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_6 \
+ 0x000000B8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_7 \
+ 0x000000BC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_8 \
+ 0x000000C0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_9 \
+ 0x000000C4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_10 \
+ 0x000000C8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_11 \
+ 0x000000CC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_12 \
+ 0x000000D0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_13 \
+ 0x000000D4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_14 \
+ 0x000000D8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_15 \
+ 0x000000DC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_16 \
+ 0x000000E0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_17 \
+ 0x000000E4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_18 \
+ 0x000000E8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_19 \
+ 0x000000EC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_20 \
+ 0x000000F0
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_21 \
+ 0x000000F4
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_22 \
+ 0x000000F8
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_23 \
+ 0x000000FC
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_24 \
+ 0x00000100
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_25 \
+ 0x00000104
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_26 \
+ 0x00000108
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_27 \
+ 0x0000010C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_28 \
+ 0x00000110
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_29 \
+ 0x00000114
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_30 \
+ 0x00000118
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_31 \
+ 0x0000011C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_32 \
+ 0x00000120
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_33 \
+ 0x00000124
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_34 \
+ 0x00000128
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_35 \
+ 0x0000012C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_36 \
+ 0x00000130
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_37 \
+ 0x00000134
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_38 \
+ 0x00000138
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_39 \
+ 0x0000013C
+
+#define OCP_SHARED_O_GPIO_PAD_CONFIG_40 \
+ 0x00000140
+
+#define OCP_SHARED_O_GPIO_PAD_CMN_CONFIG \
+ 0x00000144 // This register provide control to
+ // GPIO_CC3XXV1 IO PAD. Common
+ // control signals to all bottom Die
+ // IO's are controlled via this.
+
+#define OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG \
+ 0x00000148
+
+#define OCP_SHARED_O_D2D_TOSTACK_PAD_CONF \
+ 0x0000014C
+
+#define OCP_SHARED_O_D2D_MISC_PAD_CONF \
+ 0x00000150
+
+#define OCP_SHARED_O_SOP_CONF_OVERRIDE \
+ 0x00000154
+
+#define OCP_SHARED_O_CC3XX_DEBUGSS_STATUS \
+ 0x00000158
+
+#define OCP_SHARED_O_CC3XX_DEBUGMUX_SEL \
+ 0x0000015C
+
+#define OCP_SHARED_O_ALT_PC_VAL_NW \
+ 0x00000160
+
+#define OCP_SHARED_O_ALT_PC_VAL_APPS \
+ 0x00000164
+
+#define OCP_SHARED_O_SPARE_REG_4 \
+ 0x00000168
+
+#define OCP_SHARED_O_SPARE_REG_5 \
+ 0x0000016C
+
+#define OCP_SHARED_O_SH_SPI_CS_MASK \
+ 0x00000170
+
+#define OCP_SHARED_O_CC3XX_DEVICE_TYPE \
+ 0x00000174
+
+#define OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE \
+ 0x00000178
+
+#define OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT \
+ 0x0000017C
+
+#define OCP_SHARED_O_AUTONMS_SPICLK_SEL \
+ 0x00000180
+
+#define OCP_SHARED_O_CC3XX_DEV_PADCONF \
+ 0x00000184
+
+#define OCP_SHARED_O_SPARE_REG_8 \
+ 0x00000188
+
+#define OCP_SHARED_O_SPARE_REG_6 \
+ 0x0000018C
+
+#define OCP_SHARED_O_SPARE_REG_7 \
+ 0x00000190
+
+#define OCP_SHARED_O_APPS_WLAN_ORBIT \
+ 0x00000194
+
+#define OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD \
+ 0x00000198
+
+
+
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE1_MEM_SEMAPHORE1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE2_MEM_SEMAPHORE2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE3_MEM_SEMAPHORE3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE4_MEM_SEMAPHORE4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE5_MEM_SEMAPHORE5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE6_MEM_SEMAPHORE6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE7_MEM_SEMAPHORE7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE8 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE8_MEM_SEMAPHORE8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE9 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE9_MEM_SEMAPHORE9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE10 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE10_MEM_SEMAPHORE10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE11 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE11_MEM_SEMAPHORE11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORE12 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_M \
+ 0x00000003 // General Purpose Semaphore for SW
+ // Usage. If any of the 2 bits of a
+ // given register is set to 1, it
+ // means that the semaphore is
+ // locked by one of the masters.
+ // Each bit represents a master IP
+ // as follows: {WLAN,NWP}. The JTAG
+ // cannot capture the semaphore but
+ // it can release it. As a master IP
+ // reads the semaphore, it will be
+ // caputed and the masters
+ // correlating bit will be set to 1
+ // (set upon read). As any IP writes
+ // to this address (independent of
+ // the written data) the semaphore
+ // will be set to 2'b00.
+
+#define OCP_SHARED_SEMAPHORE12_MEM_SEMAPHORE12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_IC_LOCKER_ID register.
+//
+//******************************************************************************
+#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_M \
+ 0x00000007 // This register is used for
+ // allowing only one master OCP to
+ // perform write transactions to the
+ // OCP slaves. Each bit represents
+ // an IP in the following format: {
+ // JTAG,WLAN, NWP mcu}. As any of
+ // the bits is set to one, the
+ // correlating IP is preventing the
+ // other IP's from performing write
+ // transactions to the slaves. As
+ // the Inter Connect is locked, the
+ // only the locking IP can write to
+ // the register and by that
+ // releasing the lock. 3'b000 => IC
+ // is not locked. 3'b001 => IC is
+ // locked by NWP mcu. 3'b010 => IC
+ // is locked by WLAN. 3'b100 => IC
+ // is locked by JTAG.
+
+#define OCP_SHARED_IC_LOCKER_ID_MEM_IC_LOCKER_ID_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_MCU_SEMAPHORE_PEND register.
+//
+//******************************************************************************
+#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_M \
+ 0x0000FFFF // This register specifies the
+ // semaphore for which the NWP mcu
+ // is waiting to be released. It is
+ // set to the serial number of a
+ // given locked semaphore after it
+ // was read by the NWP mcu. Only
+ // [11:0] is used.
+
+#define OCP_SHARED_MCU_SEMAPHORE_PEND_MEM_MCU_SEMAPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_WL_SEMAPHORE_PEND register.
+//
+//******************************************************************************
+#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_M \
+ 0x0000FFFF // This register specifies the
+ // semaphore for which the WLAN is
+ // waiting to be released. It is set
+ // to the serial number of a given
+ // locked semaphore after it was
+ // read by the WLAN. Only [11:0] is
+ // used.
+
+#define OCP_SHARED_WL_SEMAPHORE_PEND_MEM_WL_SEMAPHORE_PEND_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_PLATFORM_DETECTION_RD_ONLY register.
+//
+//******************************************************************************
+#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_M \
+ 0x0000FFFF // This information serves the IPs
+ // for knowing in which platform are
+ // they integrated at: 0 = CC31XX.
+
+#define OCP_SHARED_PLATFORM_DETECTION_RD_ONLY_PLATFORM_DETECTION_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SEMAPHORES_STATUS_RD_ONLY register.
+//
+//******************************************************************************
+#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_M \
+ 0x00000FFF // Captured/released semaphores
+ // status for the 12 semaphores.
+ // Each bit of the 12 bits
+ // represents a semaphore. 0 =>
+ // Semaphore Free. 1 => Semaphore
+ // Captured.
+
+#define OCP_SHARED_SEMAPHORES_STATUS_RD_ONLY_SEMAPHORES_STATUS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_CONFIG_CTRL register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_IC_TO_EN \
+ 0x00000010 // This bit is used to enable
+ // timeout mechanism for top_ocp_ic
+ // (for debug puropse). When 1 value
+ // , in case any ocp slave doesn't
+ // give sresponse within 16 cylcles
+ // top_ic will give error response
+ // itself to avoid bus hange.
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_APPS \
+ 0x00000008 // 1 bit should be accessible only
+ // in devinit. This will enable 0x4
+ // hack for apps processor
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_ALT_PC_EN_NW \
+ 0x00000004 // 1 bit, should be accessible only
+ // in devinit. This will enable 0x4
+ // hack for nw processor
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_EXTEND_NW_ROM \
+ 0x00000002 // When set NW can take over apps
+ // rom and flash via IDCODE bus.
+ // Apps will able to access this
+ // register only during devinit and
+ // reset value should be 0.
+
+#define OCP_SHARED_CC3XX_CONFIG_CTRL_MEM_WLAN_HOST_INTF_SEL \
+ 0x00000001 // When this bit is set to 0 WPSI
+ // host interface wil be selected,
+ // when this bit is set to 1 , WLAN
+ // host async bridge will be
+ // selected.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_LSB register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_M \
+ 0x3FFFFFFF // This register provides memss RAM
+ // column configuration for column 0
+ // to 9. 3 bits are allocated per
+ // column. This register is required
+ // to be configured before starting
+ // RAM access. Changing register
+ // setting while code is running
+ // will result into unpredictable
+ // memory behaviour. Register is
+ // supported to configured ones
+ // after core is booted up. 3 bit
+ // encoding per column is as
+ // follows: when 000 : WLAN, 001:
+ // NWP, 010: APPS, 011: PHY, 100:
+ // OCLA column 0 select: bit [2:0]
+ // :when 000 -> WLAN,001 -> NWP,010
+ // -> APPS, 011 -> PHY, 100 -> OCLA
+ // column 1 select: bit [5:3]
+ // :column 2 select: bit [8 : 6]:
+ // column 3 select : bit [11: 9]
+ // column 4 select : bit [14:12]
+ // column 5 select : bit [17:15]
+ // column 6 select : bit [20:18]
+ // column 7 select : bit [23:21]
+ // column 8 select : bit [26:24]
+ // column 9 select : bit [29:27]
+ // column 10 select
+
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_LSB_MEM_SHARED_MEM_SEL_LSB_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_SHARED_MEM_SEL_MSB register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_M \
+ 0x00000FFF // This register provides memss RAM
+ // column configuration for column
+ // 10 to 15. 3 bits are allocated
+ // per column. This register is
+ // required to be configured before
+ // starting RAM access. Changing
+ // register setting while code is
+ // running will result into
+ // unpredictable memory behaviour.
+ // Register is supported to
+ // configured ones after core is
+ // booted up. 3 bit encoding per
+ // column is as follows: when 000 :
+ // WLAN, 001: NWP, 010: APPS, 011:
+ // PHY, 100: OCLA column 11 select :
+ // bit [2:0] column 12 select : bit
+ // [5:3] column 13 select : bit [8 :
+ // 6] column 14 select :
+
+#define OCP_SHARED_CC3XX_SHARED_MEM_SEL_MSB_MEM_SHARED_MEM_SEL_MSB_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_WLAN_ELP_WAKE_EN register.
+//
+//******************************************************************************
+#define OCP_SHARED_WLAN_ELP_WAKE_EN_MEM_WLAN_ELP_WAKE_EN \
+ 0x00000001 // when '1' : signal will enabled
+ // ELP power doamin when '0': ELP is
+ // not powered up.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_DEVINIT_ROM_START_ADDR register.
+//
+//******************************************************************************
+#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module. This register is not used
+ // , similar register availble in
+ // GPRCM space.
+
+#define OCP_SHARED_DEVINIT_ROM_START_ADDR_MEM_DEVINIT_ROM_START_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_DEVINIT_ROM_END_ADDR register.
+//
+//******************************************************************************
+#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_DEVINIT_ROM_END_ADDR_MEM_DEVINIT_ROM_END_ADDR_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_SEED register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_SEED_MEM_SSBD_SEED_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_CHK register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_M \
+ 0xFFFFFFFF // 32 bit, Writable only during
+ // devinit, and whole 32 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_CHK_MEM_SSBD_CHK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SSBD_POLY_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_M \
+ 0x00000003 // 2 bit, Writable only during
+ // devinit, and whole 2 bit should
+ // be output of the config register
+ // module.
+
+#define OCP_SHARED_SSBD_POLY_SEL_MEM_SSBD_POLY_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_0 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_M \
+ 0xFFFFFFFF // Devinit code should look for
+ // whether corresponding fuse is
+ // blown and if blown write to the
+ // 11th bit of this register to
+ // disable flshtst interface
+
+#define OCP_SHARED_SPARE_REG_0_MEM_SPARE_REG_0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_1_MEM_SPARE_REG_1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_2_MEM_SPARE_REG_2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_M \
+ 0xFFFFFFFF // APPS Software register
+
+#define OCP_SHARED_SPARE_REG_3_MEM_SPARE_REG_3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_0 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." "For example in
+ // case of I2C Value gets latched at
+ // rising edge of RET33.""" """ 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_0_MEM_GPIO_PAD_CONFIG_0_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_1 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_1_MEM_GPIO_PAD_CONFIG_1_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_2 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_2_MEM_GPIO_PAD_CONFIG_2_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_3 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_3_MEM_GPIO_PAD_CONFIG_3_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_4_MEM_GPIO_PAD_CONFIG_4_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_5_MEM_GPIO_PAD_CONFIG_5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_6_MEM_GPIO_PAD_CONFIG_6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_7_MEM_GPIO_PAD_CONFIG_7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_8 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_8_MEM_GPIO_PAD_CONFIG_8_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_9 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_9_MEM_GPIO_PAD_CONFIG_9_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_10 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_10_MEM_GPIO_PAD_CONFIG_10_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_11 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_11_MEM_GPIO_PAD_CONFIG_11_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_12 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_12_MEM_GPIO_PAD_CONFIG_12_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_13 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_13_MEM_GPIO_PAD_CONFIG_13_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_14 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_14_MEM_GPIO_PAD_CONFIG_14_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_15 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_15_MEM_GPIO_PAD_CONFIG_15_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_16 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_16_MEM_GPIO_PAD_CONFIG_16_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_17 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_17_MEM_GPIO_PAD_CONFIG_17_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_18 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_18_MEM_GPIO_PAD_CONFIG_18_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_19 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_19_MEM_GPIO_PAD_CONFIG_19_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_20 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_20_MEM_GPIO_PAD_CONFIG_20_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_21 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_21_MEM_GPIO_PAD_CONFIG_21_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_22 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_22_MEM_GPIO_PAD_CONFIG_22_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_23 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_23_MEM_GPIO_PAD_CONFIG_23_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_24 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_24_MEM_GPIO_PAD_CONFIG_24_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_25 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_25_MEM_GPIO_PAD_CONFIG_25_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_26 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_26_MEM_GPIO_PAD_CONFIG_26_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_27 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_27_MEM_GPIO_PAD_CONFIG_27_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_28 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_28_MEM_GPIO_PAD_CONFIG_28_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_29 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_29_MEM_GPIO_PAD_CONFIG_29_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_30 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_30_MEM_GPIO_PAD_CONFIG_30_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_31 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_31_MEM_GPIO_PAD_CONFIG_31_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_32 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_M \
+ 0x00000FFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." it can be used
+ // for I2C type of peripherals. 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_32_MEM_GPIO_PAD_CONFIG_32_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_33 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_33_MEM_GPIO_PAD_CONFIG_33_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_34 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_34_MEM_GPIO_PAD_CONFIG_34_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_35 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_35_MEM_GPIO_PAD_CONFIG_35_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_36 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_36_MEM_GPIO_PAD_CONFIG_36_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_37 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_37_MEM_GPIO_PAD_CONFIG_37_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_38 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_38_MEM_GPIO_PAD_CONFIG_38_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_39 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_M \
+ 0x0000003F // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 5 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'. IODEN and I8MAEN
+ // is diesabled for all development
+ // IO's. These signals are tied to
+ // logic level '0'. common control
+ // is implemented for I2MAEN,
+ // I4MAEN, WKPU, WKPD control .
+ // refer dev_pad_cmn_config register
+ // bits.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_39_MEM_GPIO_PAD_CONFIG_39_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CONFIG_40 register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_M \
+ 0x0007FFFF // GPIO 0 register: "Bit 0 - 3 is
+ // used for PAD IO mode selection.
+ // io_register={ "" 0 =>
+ // """"CONFMODE[0]"""""" "" 1 =>
+ // """"CONFMODE[1]"""""" "" 2 =>
+ // """"CONFMODE[2]"""""" "" 3 =>
+ // """"CONFMODE[3]"""" 4 =>
+ // """"IODEN"""" --> When level ‘1’
+ // this disables the PMOS xtors of
+ // the output stages making them
+ // open-drain type." "For example in
+ // case of I2C Value gets latched at
+ // rising edge of RET33.""" """ 5 =>
+ // """"I2MAEN"""" --> Level ‘1’
+ // enables the approx 2mA output
+ // stage""" """ 6 => """"I4MAEN""""
+ // --> Level ‘1’ enables the approx
+ // 4mA output stage""" """ 7 =>
+ // """"I8MAEN"""" --> Level ‘1’
+ // enables the approx 8mA output
+ // stage. Note: any drive strength
+ // between 2mA and 14mA can be
+ // obtained with combination of 2mA
+ // 4mA and 8mA.""" """ 8 =>
+ // """"IWKPUEN"""" --> 10uA pull up
+ // (weak strength)""" """ 9 =>
+ // """"IWKPDEN"""" --> 10uA pull
+ // down (weak strength)""" """ 10 =>
+ // """"IOE_N"""" --> output enable
+ // value. level ‘0’ enables the IDO
+ // to PAD path. Else PAD is
+ // tristated (except for the PU/PD
+ // which are independent)." "Value
+ // gets latched at rising edge of
+ // RET33""" """ 11 =>""""
+ // IOE_N_OV"""" --> output enable
+ // overirde. when bit is set to
+ // logic '1' IOE_N (bit 4) value
+ // will control IO IOE_N signal else
+ // IOE_N is control via selected HW
+ // logic. strong PULL UP and PULL
+ // Down control is disabled for all
+ // IO's. both controls are tied to
+ // logic level '0'.
+
+#define OCP_SHARED_GPIO_PAD_CONFIG_40_MEM_GPIO_PAD_CONFIG_40_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_GPIO_PAD_CMN_CONFIG register.
+//
+//******************************************************************************
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_A_EN \
+ 0x00000080 // when '1' enable ISO A control to
+ // D2D Pads else ISO is disabled.
+ // For these PADS to be functional
+ // this signals should be set 0.
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_D2D_ISO_Y_EN \
+ 0x00000040 // when '1' enable ISO Y control to
+ // D2D Pads else ISO is disabled.
+ // For these PADS to be functional
+ // this signals should be set 0.
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_JTAG_IDIEN \
+ 0x00000020 // If level ‘1’ enables the PAD to
+ // ODI path for JTAG PADS [PAD 23,
+ // 24, 28, 29]. Else ODI is pulled
+ // ‘Low’ regardless of PAD level."
+ // "Value gets latched at rising
+ // edge of RET33.""" """
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_M \
+ 0x00000018 // 00’: hysteriris = 10% of VDDS
+ // (difference between upper and
+ // lower threshold of the schmit
+ // trigger) ‘01’: hysteriris = 20%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger) ‘10’: hysteriris = 30%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger) ‘11’: hysteriris = 40%
+ // of VDDS (difference between upper
+ // and lower threshold of the schmit
+ // trigger)" """
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTVAL_S 3
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_HYSTEN \
+ 0x00000004 // If logic ‘0’ there is no
+ // hysteresis. Set to ‘1’ to enable
+ // hysteresis. Leave the choice to
+ // customers"""
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IBIASEN \
+ 0x00000002 // Normal functional operation set
+ // this to logic ‘1’ to increase the
+ // speed of the o/p buffer at the
+ // cost of 0.2uA static current
+ // consumption per IO. During IDDQ
+ // test and during Hibernate this
+ // would be forced to logic ‘0’.
+ // Value is not latched at rising
+ // edge of RET33.""
+
+#define OCP_SHARED_GPIO_PAD_CMN_CONFIG_MEM_PAD_IDIEN \
+ 0x00000001 // If level ‘1’ enables the PAD to
+ // ODI path. Else ODI is pulled
+ // ‘Low’ regardless of PAD level."
+ // "Value gets latched at rising
+ // edge of RET33.""" """
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_DEV_PAD_CMN_CONFIG register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_M \
+ 0x0000003F // this register implements common
+ // IO control to all devement mode
+ // PADs; these PADs are DEV_PAD33 to
+ // DEV_PAD39. Bit [1:0] : Drive
+ // strength control. These 2 bits
+ // are connected to DEV PAD drive
+ // strength control. possible drive
+ // stregnths are 2MA, 4MA and 6 MA
+ // for the these IO's. bit 0: when
+ // set to logic value '1' enable 2MA
+ // drive strength for DEVPAD01 to 07
+ // bit 1: when set to logic value
+ // '1' enable 4MA drive strength for
+ // DEVPAD01 to 07. bit[3:2] : WK
+ // PULL UP and PULL down control.
+ // These 2 bits provide IWKPUEN and
+ // IWKPDEN control for all DEV IO's.
+ // bit 2: when set to logic value
+ // '1' enable WKPU to DEVPAD01 to 07
+ // bit 3: when set to logic value
+ // '1' enable WKPD to DEVPAD01 to
+ // 07. bit 4: WK PULL control for
+ // DEV_PKG_DETECT pin. when '1'
+ // pullup enabled else it is
+ // disable. bit 5: when set to logic
+ // value '1' enable 8MA drive
+ // strength for DEVPAD01 to 07.
+
+#define OCP_SHARED_D2D_DEV_PAD_CMN_CONFIG_MEM_DEV_PAD_CMN_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_TOSTACK_PAD_CONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_M \
+ 0x1FFFFFFF // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+ // this register control OEN2X pin
+ // of D2D TOSTACK PAD: OEN1X and
+ // OEN2X decoding is as follows:
+ // "when ""00"" :" "when ""01"" :
+ // dirve strength is '1' and output
+ // buffer enabled." "when ""10"" :
+ // drive strength is 2 and output
+ // buffer is disabled." "when ""11""
+ // : dirve strength is '3' and
+ // output buffer enabled."
+
+#define OCP_SHARED_D2D_TOSTACK_PAD_CONF_MEM_D2D_TOSTACK_PAD_CONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_D2D_MISC_PAD_CONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_POR_RESET_N \
+ 0x00000200 // This register provide OEN2X
+ // control to D2D PADS OEN/OEN2X
+ // control. When 0 : Act as input
+ // buffer else output buffer with
+ // drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_RESET_N \
+ 0x00000100 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_HCLK \
+ 0x00000080 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TCK \
+ 0x00000040 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TMS \
+ 0x00000020 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_JTAG_TDI \
+ 0x00000010 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_PIOSC \
+ 0x00000008 // OEN/OEN2X control. When 0 : Act
+ // as input buffer else output
+ // buffer with drive strength 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_M \
+ 0x00000007 // D2D SPARE PAD OEN/OEN2X control.
+ // When 0: Act as input buffer else
+ // output buffer with drive strength
+ // 2.
+
+#define OCP_SHARED_D2D_MISC_PAD_CONF_MEM_D2D_SPARE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SOP_CONF_OVERRIDE register.
+//
+//******************************************************************************
+#define OCP_SHARED_SOP_CONF_OVERRIDE_MEM_SOP_CONF_OVERRIDE \
+ 0x00000001 // when '1' : signal will ovberride
+ // SoP setting of JTAG PADS. when
+ // '0': SoP setting will control
+ // JTAG PADs [ TDI, TDO, TMS, TCK]
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEBUGSS_STATUS register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_MCU_JTAGNSW \
+ 0x00000020 // This register contains debug
+ // subsystem status bits From APPS
+ // MCU status bit to indicates
+ // whether serial wire or 4 pins
+ // jtag select.
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_CJTAG_BYPASS_STATUS \
+ 0x00000010 // cjtag bypass bit select
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SW_INTERFACE_SEL_STATUS \
+ 0x00000008 // serial wire interface bit select
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_APPS_TAP_ENABLE_STATUS \
+ 0x00000004 // apps tap enable status
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_TAPS_ENABLE_STATUS \
+ 0x00000002 // tap enable status
+
+#define OCP_SHARED_CC3XX_DEBUGSS_STATUS_SSBD_UNLOCK \
+ 0x00000001 // ssbd unlock status
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEBUGMUX_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_M \
+ 0x0000FFFF // debug mux select register. Upper
+ // 8 bits are used for debug module
+ // selection. Lower 8 bit [7:0] used
+ // inside debug module for selecting
+ // module specific signals.
+ // Bits[15:8: when set x"00" : GPRCM
+ // debug bus. When "o1" : SDIO debug
+ // debug bus when x"02" :
+ // autonoumous SPI when x"03" :
+ // TOPIC when x"04": memss when
+ // x"25": mcu debug bus : APPS debug
+ // when x"45": mcu debug bus : NWP
+ // debug when x"65": mcu debug bus :
+ // AHB2VBUS debug when x"85": mcu
+ // debug bus : VBUS2HAB debug when
+ // x"95": mcu debug bus : RCM debug
+ // when x"A5": mcu debug bus :
+ // crypto debug when x"06": WLAN
+ // debug bus when x"07": debugss bus
+ // when x"08": ADC debug when x"09":
+ // SDIO PHY debug bus then "others"
+ // : no debug is selected
+
+#define OCP_SHARED_CC3XX_DEBUGMUX_SEL_MEM_CC3XX_DEBUGMUX_SEL_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_ALT_PC_VAL_NW register.
+//
+//******************************************************************************
+#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_M \
+ 0xFFFFFFFF // 32 bit. Program counter value
+ // for 0x4 address when Alt_pc_en_nw
+ // is set.
+
+#define OCP_SHARED_ALT_PC_VAL_NW_MEM_ALT_PC_VAL_NW_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_ALT_PC_VAL_APPS register.
+//
+//******************************************************************************
+#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_M \
+ 0xFFFFFFFF // 32 bit. Program counter value
+ // for 0x4 address when
+ // Alt_pc_en_apps is set
+
+#define OCP_SHARED_ALT_PC_VAL_APPS_MEM_ALT_PC_VAL_APPS_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_4 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_M \
+ 0xFFFFFFFE // HW register
+
+#define OCP_SHARED_SPARE_REG_4_MEM_SPARE_REG_4_S 1
+#define OCP_SHARED_SPARE_REG_4_INVERT_D2D_INTERFACE \
+ 0x00000001 // Data to the top die launched at
+ // negative edge instead of positive
+ // edge.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_5 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_M \
+ 0xFFFFFFFF // HW register
+
+#define OCP_SHARED_SPARE_REG_5_MEM_SPARE_REG_5_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SH_SPI_CS_MASK register.
+//
+//******************************************************************************
+#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_M \
+ 0x0000000F // ( chip select 0 is unmasked
+ // after reset. When ‘1’ : CS is
+ // unmasked or else masked. Valid
+ // configurations are 1000, 0100,
+ // 0010 or 0001. Any other setting
+ // can lead to unpredictable
+ // behavior.
+
+#define OCP_SHARED_SH_SPI_CS_MASK_MEM_SH_SPI_CS_MASK_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEVICE_TYPE register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_M \
+ 0x00000060 // reserved bits tied off "00".
+
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_reserved_S 5
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_M \
+ 0x0000001F // CC3XX Device type information.
+
+#define OCP_SHARED_CC3XX_DEVICE_TYPE_DEVICE_TYPE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_MEM_TOPMUXCTRL_IFORCE register.
+//
+//******************************************************************************
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_M \
+ 0x000000F0 // [4] 1: switch between
+ // WLAN_I2C_SCL and
+ // TOP_GPIO_PORT4_I2C closes 0:
+ // switch opens [5] 1: switch
+ // between WLAN_I2C_SCL and
+ // TOP_VSENSE_PORT closes 0: switch
+ // opens [6] 1: switch between
+ // WLAN_I2C_SCL and WLAN_ANA_TP4
+ // closes 0: switch opens [7]
+ // Reserved
+
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE1_S 4
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_M \
+ 0x0000000F // [0] 1: switch between
+ // WLAN_I2C_SDA and
+ // TOP_GPIO_PORT3_I2C closes 0:
+ // switch opens [1] 1: switch
+ // between WLAN_I2C_SDA and
+ // TOP_IFORCE_PORT closes 0: switch
+ // opens [2] 1: switch between
+ // WLAN_I2C_SDA and WLAN_ANA_TP3
+ // closes 0: switch opens [3]
+ // Reserved
+
+#define OCP_SHARED_MEM_TOPMUXCTRL_IFORCE_MEM_TOPMUXCTRL_IFORCE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEV_PACKAGE_DETECT register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEV_PACKAGE_DETECT_DEV_PKG_DETECT \
+ 0x00000001 // when '0' indicates package type
+ // is development.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_AUTONMS_SPICLK_SEL register.
+//
+//******************************************************************************
+#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONOMOUS_BYPASS \
+ 0x00000002 // This bit is used to bypass MCPSI
+ // autonomous mode .if this bit is 1
+ // autonomous MCSPI logic will be
+ // bypassed and it will act as link
+ // SPI
+
+#define OCP_SHARED_AUTONMS_SPICLK_SEL_MEM_AUTONMS_SPICLK_SEL \
+ 0x00000001 // This bit is used in SPI
+ // Autonomous mode to switch clock
+ // from system clock to SPI clk that
+ // is coming from PAD. When value 1
+ // PAD SPI clk is used as system
+ // clock in LPDS mode by SPI as well
+ // as autonomous wrapper logic.
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_CC3XX_DEV_PADCONF register.
+//
+//******************************************************************************
+#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_M \
+ 0x0000FFFF
+
+#define OCP_SHARED_CC3XX_DEV_PADCONF_MEM_CC3XX_DEV_PADCONF_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_IDMEM_TIM_UPDATE register.
+//
+//******************************************************************************
+#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_M \
+ 0xFFFFFFFF
+
+#define OCP_SHARED_IDMEM_TIM_UPDATE_MEM_IDMEM_TIM_UPDATE_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_6 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_6_MEM_SPARE_REG_6_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_SPARE_REG_7 register.
+//
+//******************************************************************************
+#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_M \
+ 0xFFFFFFFF // NWP Software register
+
+#define OCP_SHARED_SPARE_REG_7_MEM_SPARE_REG_7_S 0
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_APPS_WLAN_ORBIT register.
+//
+//******************************************************************************
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_M \
+ 0xFFFFFC00 // Spare bit
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_spare_S 10
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_status \
+ 0x00000200 // A rising edge on this bit
+ // indicates that the test case
+ // passes. This bit would be brought
+ // out on the pin interface during
+ // ORBIT.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_exec \
+ 0x00000100 // This register bit is writable by
+ // the FW and when set to 1 it
+ // indicates the start of a test
+ // execution. A failing edge on this
+ // bit indicates that the test
+ // execution is complete. This bit
+ // would be brought out on the pin
+ // interface during ORBIT.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_M \
+ 0x000000FC // Implies the test case ID that
+ // needs to run.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_id_S 2
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_halt_proc \
+ 0x00000002 // This bit is used to trigger the
+ // execution of test cases within
+ // the (ROM based) IP.
+
+#define OCP_SHARED_APPS_WLAN_ORBIT_mem_orbit_test_mode \
+ 0x00000001 // When this bit is 1 it implies
+ // ORBIT mode of operation and the
+ // (ROM based) IP start the
+ // execution from a test case
+ // perspective
+
+//******************************************************************************
+//
+// The following are defines for the bit fields in the
+// OCP_SHARED_O_APPS_WLAN_SCRATCH_PAD register.
+//
+//******************************************************************************
+#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_M \
+ 0xFFFFFFFF // scratch pad register.
+
+#define OCP_SHARED_APPS_WLAN_SCRATCH_PAD_MEM_APPS_WLAN_SCRATCH_PAD_S 0
+
+
+
+#endif // __HW_OCP_SHARED_H__
diff --git a/ext/hal/ti/cc3220sdk/inc/hw_types.h b/ext/hal/ti/cc3220sdk/inc/hw_types.h
new file mode 100644
index 0000000..8eff4e4
--- /dev/null
+++ b/ext/hal/ti/cc3220sdk/inc/hw_types.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Define a boolean type, and values for true and false.
+//
+//*****************************************************************************
+typedef unsigned char tBoolean;
+
+#ifndef true
+#define true 1
+#endif
+
+#ifndef false
+#define false 0
+#endif
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile unsigned long *)(x)))
+#define HWREGH(x) \
+ (*((volatile unsigned short *)(x)))
+#define HWREGB(x) \
+ (*((volatile unsigned char *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \
+ (((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+
+#endif // __HW_TYPES_H__
