)]}'
{
  "commit": "b5016714b08273da6eba7a0a115ee2a2e22cc24f",
  "tree": "d87f8f3e51283080b926d5c29017e7086a4f4b20",
  "parents": [
    "98ffd1addd6a606d07a916b8ab1a6b9b63c068da"
  ],
  "author": {
    "name": "Daniel Leung",
    "email": "daniel.leung@intel.com",
    "time": "Thu Aug 17 15:36:47 2023 -0700"
  },
  "committer": {
    "name": "Anas Nashif",
    "email": "anas.nashif@intel.com",
    "time": "Sat Aug 26 16:50:40 2023 -0400"
  },
  "message": "xtensa: mmu: handle TLB misses during user exception\n\nThis adds code to deal with TLB misses as these comes as\nlevel 1 interrupts.\n\nSigned-off-by: Daniel Leung \u003cdaniel.leung@intel.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c7dbb44ddfe10c53e7c4a9a86f86c94829088b73",
      "old_mode": 33188,
      "old_path": "arch/xtensa/core/xtensa-asm2-util.S",
      "new_id": "66dd712a9167169ab4c2682acfcd76d328e18cf4",
      "new_mode": 33188,
      "new_path": "arch/xtensa/core/xtensa-asm2-util.S"
    }
  ]
}