/*
 * Copyright (c) 2019, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <arm/armv8-m.dtsi>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-m33f";
			reg = <0>;
		};
		cpu@1 {
			compatible = "arm,cortex-m33";
			reg = <1>;
		};
	};

	sram0:memory@30000000 {
		compatible = "mmio-sram";
		reg = <0x30000000 DT_SIZE_K(64)>;
	};

	sram1:memory@30010000 {
		compatible = "mmio-sram";
		reg = <0x30010000 DT_SIZE_K(64)>;
	};

	sram2:memory@30020000 {
		compatible = "mmio-sram";
		reg = <0x30020000 DT_SIZE_K(64)>;
	};

	sram3:memory@30030000 {
		compatible = "mmio-sram";
		reg = <0x30030000 DT_SIZE_K(64)>;
	};

	sramx:memory@14000000{
		compatible = "mmio-sram";
		reg = <0x14000000 DT_SIZE_K(32)>;
	};

	soc {

		flash0:flash@10000000 {
			compatible = "soc-nv-flash";
			reg = <0x10000000 DT_SIZE_K(630)>;
		};

		usart0:usart@50086000 {
			compatible = "nxp,lpc-usart";
			reg = <0x50086000 0xE44>;
			interrupts = <14 0>;
			label = "USART_0";
			status = "disabled";
		};

		gpio0:gpio@0 {
			compatible = "nxp,lpc-gpio";
			reg = <0x5008c000 0x2488>;
			interrupts = <4 2>,<5 2>,<6 2>,<7 2>;
			label = "GPIO_0";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio1:gpio@1 {
			compatible = "nxp,lpc-gpio";
			reg = <0x5008c000 0x2488>;
			interrupts = <32 2>,<33 2>,<34 2>,<35 2>;
			label = "GPIO_1";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio2:gpio@2 {
			compatible = "nxp,lpc-gpio";
			reg = <0x5008c000 0x2488>;
			label = "GPIO_2";
			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio3:gpio@3 {
			compatible = "nxp,lpc-gpio";
			reg = <0x5008c000 0x2488>;
			label = "GPIO_3";
			gpio-controller;
			#gpio-cells = <2>;
		};

		spi8: spi@5009f000 {
			compatible = "nxp,lpc-spi";
			reg = <0x5009f000 0x1000>;
			interrupts = <59 0>;
			label = "SPI_8";
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <3>;
};