/*
 * Copyright (c) 2017 BayLibre, SAS
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <st/f0/stm32f0.dtsi>

/ {
	soc {
		flash-controller@40022000 {
			flash0: flash@8000000 {
				erase-block-size = <2048>;
			};
		};

		pinctrl: pin-controller@48000000 {

			gpioe: gpio@48001000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x48001000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
				label = "GPIOE";
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
			status = "disabled";
			label = "TIMERS_2";

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				st,prescaler = <0>;
				label = "PWM_2";
				#pwm-cells = <2>;
			};
		};

		spi2: spi@40003800 {
			compatible = "st,stm32-spi-fifo";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40003800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
			interrupts = <26 3>;
			status = "disabled";
			label = "SPI_2";
		};

		usb: usb@40005c00 {
			compatible = "st,stm32-usb";
			reg = <0x40005c00 0x400>;
			interrupts = <31 0>;
			interrupt-names = "usb";
			num-bidir-endpoints = <8>;
			ram-size = <1024>;
			phys = <&usb_fs_phy>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
			status = "disabled";
			label= "USB";
		};

		can1: can@40006400 {
			compatible = "st,stm32-can";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40006400 0x400>;
			interrupts = <30 0>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
			status = "disabled";
			label = "CAN_1";
			bus-speed = <250000>;
			sjw = <1>;
			prop-seg = <0>;
			phase-seg1 = <5>;
			phase-seg2 = <6>;
		};

		dma1: dma@40020000 {
			interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
		};
	};

	usb_fs_phy: usbphy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
		label = "USB_FS_PHY";
	};
};