/*
 * Copyright (c) 2018 qianfan Zhao
 * Copyright (c) 2019 Centaur Analytics, Inc
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m3";
			reg = <0>;
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	soc {
		flash-controller@40023c00 {
			compatible = "st,stm32f2-flash-controller";
			label = "FLASH_CTRL";
			reg = <0x40023c00 0x400>;
			interrupts = <4 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "soc-nv-flash";
				label = "FLASH_STM32";

				write-block-size = <1>;
			};
		};

		rcc: rcc@40023800 {
			compatible = "st,stm32-rcc";
			#clock-cells = <2>;
			reg = <0x40023800 0x400>;
			label = "STM32_CLK_RCC";
		};

		pinctrl: pin-controller@40020000 {
			compatible = "st,stm32-pinmux";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40020000 0x2000>;

			gpioa: gpio@40020000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40020000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
				label = "GPIOA";
			};

			gpiob: gpio@40020400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40020400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
				label = "GPIOB";
			};

			gpioc: gpio@40020800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40020800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
				label = "GPIOC";
			};

			gpiod: gpio@40020c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40020c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
				label = "GPIOD";
			};

			gpioe: gpio@40021000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
				label = "GPIOE";
			};

			gpiof: gpio@40021400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
				label = "GPIOF";
			};

			gpiog: gpio@40021800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
				label = "GPIOG";
			};

			gpioh: gpio@40021c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40021c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
				label = "GPIOH";
			};

			gpioi: gpio@40022000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x40022000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
				label = "GPIOI";
			};
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			label = "IWDG";
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002C00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
			label = "WWDG";
			interrupts = <0 7>;
			status = "disabled";
		};

		usart1: serial@40011000 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			interrupts = <37 0>;
			status = "disabled";
			label = "UART_1";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			interrupts = <38 0>;
			status = "disabled";
			label = "UART_2";
		};

		usart3: serial@40004800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
			interrupts = <39 0>;
			status = "disabled";
			label = "UART_3";
		};

		usart6: serial@40011400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40011400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
			interrupts = <71 0>;
			status = "disabled";
			label = "UART_6";
		};

		uart4: serial@40004c00 {
			compatible ="st,stm32-uart";
			reg = <0x40004c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
			interrupts = <52 0>;
			status = "disabled";
			label = "UART_4";
		};

		uart5: serial@40005000 {
			compatible = "st,stm32-uart";
			reg = <0x40005000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
			interrupts = <53 0>;
			status = "disabled";
			label = "UART_5";
		};

		usbotg_fs: usb@50000000 {
			compatible = "st,stm32-otgfs";
			reg = <0x50000000 0x40000>;
			interrupts = <67 0>;
			interrupt-names = "otgfs";
			num-bidir-endpoints = <4>;
			ram-size = <1280>;
			maximum-speed = "full-speed";
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
			phys = <&otgfs_phy>;
			status = "disabled";
			label = "OTGFS";
		};

		adc1: adc@40012000 {
			compatible = "st,stm32-adc";
			reg = <0x40012000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
			interrupts = <18 0>;
			status = "disabled";
			label = "ADC_1";
			#io-channel-cells = <1>;
		};

		dma1: dma@40026000 {
			compatible = "st,stm32-dma";
			#dma-cells = <4>;
			reg = <0x40026000 0x400>;
			interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
			status = "disabled";
			label = "DMA_1";
		};

		dma2: dma@40026400 {
			compatible = "st,stm32-dma";
			#dma-cells = <4>;
			reg = <0x40026400 0x400>;
			interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
			st,mem2mem;
			status = "disabled";
			label = "DMA_2";
		};
	};

	otgfs_phy: otgfs_phy {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
		label = "OTGFS_PHY";
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};