/*
 * Copyright (c) 2020, NXP
 *
 * SPDX-License-Identifier: Apache-2.0
 */

/dts-v1/;

#include <nxp/nxp_rt6xx.dtsi>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/regulator/pca9420_i2c.h>

#include "mimxrt685_evk_cm33-pinctrl.dtsi"

/ {
	model = "NXP MIMXRT685-EVK board";
	compatible = "nxp,mimxrt685";

	aliases {
		sw0 = &user_button_1;
		sw1 = &user_button_2;
		led0 = &green_led;
		led1 = &blue_led;
		led2 = &red_led;
		usart-0 = &flexcomm0;
		/* For pwm test suites */
		pwm-0 = &sc_timer;
		pwm-led0 = &green_pwm_led;
		green-pwm-led = &green_pwm_led;
		blue-pwm-led = &blue_pwm_led;
		red-pwm-led = &red_pwm_led;
		watchdog0 = &wwdt0;
		magn0 = &fxos8700;
		accel0 = &fxos8700;
		sdhc0 = &usdhc0;
	};

	chosen {
		zephyr,flash-controller = &flexspi;
		zephyr,flash = &mx25um51345g;
		zephyr,code-partition = &slot0_partition;
		zephyr,sram = &sram0;
		zephyr,console = &flexcomm0;
		zephyr,shell-uart = &flexcomm0;
	};

	gpio_keys {
		compatible = "gpio-keys";
		user_button_1: button_0 {
			label = "User SW1";
			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
		};
		user_button_2: button_1 {
			label = "User SW2";
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};
	};

	leds {
		compatible = "gpio-leds";
		green_led: led_1 {
			gpios = <&gpio0 14 0>;
			label = "User LED_GREEN";
		};
		blue_led: led_2 {
			gpios = <&gpio0 26 0>;
			label = "User LED_BLUE";
		};
		red_led: led_3 {
			gpios = <&gpio0 31 0>;
			label = "User LED_RED";
		};
	};

	pwmleds {
		compatible = "pwm-leds";
		green_pwm_led: green_pwm_led {
			pwms = <&sc_timer 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
			label = "Green PWM LED";
			status = "okay";
		};
		blue_pwm_led: blue_pwm_led {
			pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
			label = "Blue PWM LED";
			status = "okay";
		};
		red_pwm_led: red_pwm_led {
			pwms = <&sc_timer 6 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
			label = "Red PWM LED";
			status = "disabled";
		};
	};

	arduino_header: arduino-connector {
		compatible = "arduino-header-r3";
		#gpio-cells = <2>;
		gpio-map-mask = <0xffffffff 0xffffffc0>;
		gpio-map-pass-thru = <0 0x3f>;
		gpio-map =	<0 0 &gpio0 5 0>,	/* A0 */
				<1 0 &gpio0 6 0>,	/* A1 */
				<2 0 &gpio0 19 0>,	/* A2 */
				<3 0 &gpio0 20 0>,	/* A3 */
				<4 0 &gpio0 17 0>,	/* A4 */
				<5 0 &gpio0 18 0>,	/* A5 */
				<6 0 &gpio0 30 0>,	/* D0 */
				<7 0 &gpio0 29 0>,	/* D1 */
				<8 0 &gpio0 28 0>,	/* D2 */
				<9 0 &gpio0 27 0>,	/* D3 */
				<10 0 &gpio1 0 0>,	/* D4 */
				<11 0 &gpio1 10 0>,	/* D5 */
				<12 0 &gpio1 2 0>,	/* D6 */
				<13 0 &gpio1 8 0>,	/* D7 */
				<14 0 &gpio1 9 0>,	/* D8 */
				<15 0 &gpio1 7 0>,	/* D9 */
				<16 0 &gpio1 6 0>,	/* D10 */
				<17 0 &gpio1 5 0>,	/* D11 */
				<18 0 &gpio1 4 0>,	/* D12 */
				<19 0 &gpio1 3 0>,	/* D13 */
				<20 0 &gpio0 17 0>,	/* D14 */
				<21 0 &gpio0 18 0>;	/* D15 */
	};

	power-states {
		idle: idle {
			compatible = "zephyr,power-state";
			power-state-name = "runtime-idle";
			min-residency-us = <10>;
		};
		suspend: suspend {
			compatible = "zephyr,power-state";
			power-state-name = "suspend-to-idle";
			min-residency-us = <1000>;
		};
	};
};

&cpu0 {
	cpu-power-states = <&idle &suspend>;
};

/*
 * RT600 EVK board uses OS timer as the kernel timer
 * In case we need to switch to SYSTICK timer, then
 * replace &os_timer with &systick
 */
&os_timer {
	status = "okay";
};

&rtc {
	status = "okay";
};

&flexcomm0 {
	compatible = "nxp,lpc-usart";
	status = "okay";
	current-speed = <115200>;
	pinctrl-0 = <&pinmux_flexcomm0_usart>;
	pinctrl-names = "default";
};

arduino_i2c: &flexcomm2 {
	compatible = "nxp,lpc-i2c";
	status = "okay";
	pinctrl-0 = <&pinmux_flexcomm2_i2c>;
	pinctrl-names = "default";
	clock-frequency = <I2C_BITRATE_FAST>;
	#address-cells = <1>;
	#size-cells = <0>;

	fxos8700: fxos8700@1e {
		compatible = "nxp,fxos8700";
		reg = <0x1e>;
		int1-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
		reset-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
	};
};

arduino_serial: &flexcomm4 {
	compatible = "nxp,lpc-usart";
	current-speed = <115200>;
	pinctrl-0 = <&pinmux_flexcomm4_usart>;
	pinctrl-names = "default";
};

arduino_spi: &flexcomm5 {
	compatible = "nxp,lpc-spi";
	status = "okay";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&dma0 10>, <&dma0 11>;
	dma-names = "rx", "tx";
	pinctrl-0 = <&pinmux_flexcomm5_spi>;
	pinctrl-names = "default";
};

/* I2S receive channel */
i2s0: &flexcomm1 {
	status = "okay";
	compatible = "nxp,lpc-i2s";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&dma0 2>;
	dma-names = "rx";
	pinctrl-0 = <&pinmux_flexcomm1_i2s>;
	pinctrl-names = "default";
};

/* I2S transmit channel */
i2s1: &flexcomm3 {
	status = "okay";
	compatible = "nxp,lpc-i2s";
	#address-cells = <1>;
	#size-cells = <0>;
	dmas = <&dma0 7>;
	dma-names = "tx";
	pinctrl-0 = <&pinmux_flexcomm3_i2s>;
	pinctrl-names = "default";
};

/* PCA9420 PMIC */
&pmic_i2c {
	status = "okay";
	compatible = "nxp,lpc-i2c";
	clock-frequency = <I2C_BITRATE_FAST>;
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-0 = <&pinmux_pmic_i2c>;
	pinctrl-names = "default";

	pca9420: pca9420@61 {
		reg = <0x61>;

		pca9420_sw1: sw1_buck {
			compatible = "regulator-pmic";
			voltage-range = <PCA9420_SW1_VOLTAGE_RANGE>;
			current-levels = <PCA9420_CURRENT_LIMIT_LEVELS>;
			num-voltages = <42>;
			ilim-reg = <PCA9420_TOP_CNTL0>;
			ilim-mask = <PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK>;
			num-current-levels = <7>;
			vsel-reg = <PCA9420_MODECFG_0_0>;
			vsel-mask = <PCA9420_MODECFG_0_SW1_OUT_MASK>;
			enable-reg = <PCA9420_MODECFG_0_2>;
			enable-mask = <PCA9420_MODECFG_2_SW1_EN_MASK>;
			enable-val = <PCA9420_MODECFG_2_SW1_EN_VAL>;
			min-uV = <500000>;
			max-uV = <1800000>;
		};

		pca9420_sw2: sw2_buck {
			compatible = "regulator-pmic";
			voltage-range = <PCA9420_SW2_VOLTAGE_RANGE>;
			num-voltages = <50>;
			current-levels = <PCA9420_CURRENT_LIMIT_LEVELS>;
			ilim-reg = <PCA9420_TOP_CNTL0>;
			ilim-mask = <PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK>;
			num-current-levels = <7>;
			vsel-reg = <PCA9420_MODECFG_0_1>;
			vsel-mask = <PCA9420_MODECFG_1_SW2_OUT_MASK>;
			enable-reg = <PCA9420_MODECFG_0_2>;
			enable-mask = <PCA9420_MODECFG_2_SW2_EN_MASK>;
			enable-val = <PCA9420_MODECFG_2_SW2_EN_VAL>;
			min-uV = <1500000>;
			max-uV = <3300000>;
		};

		pca9420_ldo1: ldo1_reg {
			compatible = "regulator-pmic";
			voltage-range = <PCA9420_LDO1_VOLTAGE_RANGE>;
			num-voltages = <9>;
			current-levels = <PCA9420_CURRENT_LIMIT_LEVELS>;
			ilim-reg = <PCA9420_TOP_CNTL0>;
			ilim-mask = <PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK>;
			num-current-levels = <7>;
			vsel-reg = <PCA9420_MODECFG_0_2>;
			vsel-mask = <PCA9420_MODECFG_2_LDO1_OUT_MASK>;
			enable-reg = <PCA9420_MODECFG_0_2>;
			enable-mask = <PCA9420_MODECFG_2_LDO1_EN_MASK>;
			enable-val = <PCA9420_MODECFG_2_LDO1_EN_VAL>;
			min-uV = <1700000>;
			max-uV = <1900000>;
		};

		pca9420_ldo2: ldo2_reg {
			compatible = "regulator-pmic";
			voltage-range = <PCA9420_LDO2_VOLTAGE_RANGE>;
			num-voltages = <50>;
			current-levels = <PCA9420_CURRENT_LIMIT_LEVELS>;
			ilim-reg = <PCA9420_TOP_CNTL0>;
			ilim-mask = <PCA9420_TOP_CNTL0_VIN_ILIM_SEL_MASK>;
			num-current-levels = <7>;
			vsel-reg = <PCA9420_MODECFG_0_3>;
			vsel-mask = <PCA9420_MODECFG_3_LDO2_OUT_MASK>;
			enable-reg = <PCA9420_MODECFG_0_2>;
			enable-mask = <PCA9420_MODECFG_2_LDO2_EN_MASK>;
			enable-val = <PCA9420_MODECFG_2_LDO2_EN_VAL>;
			min-uV = <1500000>;
			max-uV = <3300000>;
		};


	};
};

&flexspi {
	pinctrl-0 = <&pinmux_flexspi>;
	pinctrl-names = "default";
	status = "okay";
	mx25um51345g: mx25um51345g@2 {
		compatible = "nxp,imx-flexspi-mx25um51345g";
		/* MX25UM51245G is 64MB, 512MBit flash part */
		size = <DT_SIZE_M(64 * 8)>;
		reg = <2>;
		spi-max-frequency = <200000000>;
		status = "okay";
		jedec-id = [c2 81 3a];
		erase-block-size = <4096>;
		/*
		 * Note- ECC will be disabled with a
		 * write block size of 1 byte. To enable ECC, ensure
		 * writes are in multiples of 16 bytes. This reduced
		 * block size is required for MCUBoot support.
		 */
		write-block-size = <1>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			boot_partition: partition@0 {
				label = "mcuboot";
				reg = <0x00000000 DT_SIZE_K(64)>;
			};
			slot0_partition: partition@10000 {
				label = "image-0";
				reg = <0x00010000 DT_SIZE_M(24)>;
			};
			slot1_partition: partition@1810000 {
				label = "image-1";
				reg = <0x01810000 DT_SIZE_M(24)>;
			};
			scratch_partition: partition@3010000 {
				label = "image-scratch";
				reg = <0x03010000 DT_SIZE_K(8128)>;
			};
			storage_partition: partition@3f00000 {
				label = "storage";
				reg = <0x03f00000 DT_SIZE_M(1)>;
			};
		};
	};
};

&gpio0 {
	status = "okay";
};

&gpio1 {
	status = "okay";
};

&gpio2 {
	status = "okay";
};

&dma0 {
	/*
	 * The total number of dma channels available is defined by
	 * FSL_FEATURE_DMA_NUMBER_OF_CHANNELS in the SoC features file.
	 * Since memory from the heap pool is allocated based on the number
	 * of DMA channels, set this property to as many channels is needed
	 * for the platform. Adjust HEAP_MEM_POOL_SIZE in case you need more
	 * memory.
	 */
	dma-channels = <20>;
	status = "okay";
};

&wwdt0 {
	status = "okay";
};

&user_button_1 {
	status = "okay";
};

&user_button_2 {
	status = "okay";
};

&green_led {
	status = "okay";
};

&blue_led {
	status = "okay";
};

&red_led {
	status = "okay";
};

&sc_timer {
	status = "okay";
	pinctrl-0 = <&pinmux_sctimer>;
	pinctrl-names = "default";
};

&usdhc0 {
	status = "okay";
	/* Quick fix for 1.8V SD cards on RT600- disable 1.8V negotiation */
	no-1-8-v;
	pwr-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
	cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
	mmc {
		compatible = "zephyr,sdmmc-disk";
		status = "okay";
	};
	pinctrl-0 = <&pinmux_usdhc>;
	pinctrl-names = "default";
};

&lpadc0 {
	status = "okay";
	pinctrl-0 = <&pinmux_lpadc0>;
	pinctrl-names = "default";
};

zephyr_udc0: &usbhs {
	status = "okay";
};

&ctimer0 {
	status = "okay";
};

&ctimer1 {
	status = "okay";
};

&ctimer2 {
	status = "okay";
};

&ctimer3 {
	status = "okay";
};

&ctimer4 {
	status = "okay";
};

&i3c0 {
	pinctrl-0 = <&pinmux_i3c>;
	pinctrl-names = "default";

	status = "okay";
};