dts/xtensa/espressif/esp32s2.dtsi

/*
 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
 *
 * SPDX-License-Identifier: Apache-2.0
 */
#include <mem.h>
#include <xtensa/xtensa.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
#include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
#include <dt-bindings/pinctrl/esp32-pinctrl.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	chosen {
		zephyr,entropy = &trng0;
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "cdns,tensilica-xtensa-lx7";
			reg = <0>;
		};
	};

	wifi: wifi {
		compatible = "espressif,esp32-wifi";
		status = "disabled";
	};

	pinctrl: pin-controller {
		compatible = "espressif,esp32-pinctrl";
		status = "okay";
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		sram0: memory@3ffb0000 {
			compatible = "mmio-sram";
			reg = <0x3ffb0000 0x50000>;
		};

		intc: interrupt-controller@3f4c2000 {
			#interrupt-cells = <1>;
			compatible = "espressif,esp32-intc";
			interrupt-controller;
			reg = <0x3f4c2000 0x114>;
			status = "okay";
		};

		rtc: rtc@3f408000 {
			compatible = "espressif,esp32-rtc";
			reg = <0x3f408000 0x0D8>;
			xtal-freq = <ESP32_CLK_XTAL_40M>;
			#clock-cells = <1>;
			status = "okay";

			rtc_timer: rtc_timer {
				compatible = "espressif,esp32-rtc-timer";
				slow-clk-freq = <ESP32_RTC_SLOW_CLK_FREQ_90K>;
				interrupts = <RTC_CORE_INTR_SOURCE>;
				interrupt-parent = <&intc>;
				status = "okay";
			};
		};

		flash: flash-controller@3f402000 {
			compatible = "espressif,esp32-flash-controller";
			reg = <0x3f402000 0x1000>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@0 {
				compatible = "soc-nv-flash";
				reg = <0 0x400000>;
				erase-block-size = <4096>;
				write-block-size = <4>;
			};
		};

		uart0: uart@3f400000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3f400000 0x400>;
			status = "disabled";
			interrupts = <UART0_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_UART0_MODULE>;
		};

		uart1: uart@3f410000 {
			compatible = "espressif,esp32-uart";
			reg = <0x3f410000 0x400>;
			status = "disabled";
			interrupts = <UART1_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_UART1_MODULE>;
			current-speed = <115200>;
		};

		pcnt: pcnt@3f417000 {
			compatible = "espressif,esp32-pcnt";
			reg = <0x3f417000 0x1000>;
			interrupts = <PCNT_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_PCNT_MODULE>;
			status = "disabled";
		};

		ledc0: ledc@3f419000 {
			compatible = "espressif,esp32-ledc";
			pwm-controller;
			#pwm-cells = <3>;
			reg = <0x3f419000 0x1000>;
			clocks = <&rtc ESP32_LEDC_MODULE>;
			status = "disabled";
		};

		gpio0: gpio@3f404000 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3f404000 0x800>;
			interrupts = <GPIO_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			ngpios = <32>;   /* 0..31 */
		};

		gpio1: gpio@3f404800 {
			compatible = "espressif,esp32-gpio";
			gpio-controller;
			#gpio-cells = <2>;
			reg = <0x3f404800 0x800>;
			interrupts = <GPIO_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			ngpios = <22>;   /* 32..53 */
		};

		i2c0: i2c@3f413000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3f413000 0x1000>;
			interrupts = <I2C_EXT0_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_I2C0_MODULE>;
			status = "disabled";
		};

		i2c1: i2c@3f427000 {
			compatible = "espressif,esp32-i2c";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3f427000 0x1000>;
			interrupts = <I2C_EXT1_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_I2C1_MODULE>;
			status = "disabled";
		};

		timer0: counter@3f41f000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3f41f000 DT_SIZE_K(4)>;
			group = <0>;
			index = <0>;
			interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer1: counter@3f41f024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3f41f024 DT_SIZE_K(4)>;
			group = <0>;
			index = <1>;
			interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer2: counter@3f420000 {
			compatible = "espressif,esp32-timer";
			reg = <0x3f420000 DT_SIZE_K(4)>;
			group = <1>;
			index = <0>;
			interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			status = "disabled";
		};

		timer3: counter@3f420024 {
			compatible = "espressif,esp32-timer";
			reg = <0x3f420024 DT_SIZE_K(4)>;
			group = <1>;
			index = <1>;
			interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
		};

		trng0: trng@3f435110 {
			compatible = "espressif,esp32-trng";
			reg = <0x3f435110 0x4>;
			status = "disabled";
		};

		spi2: spi@3f424000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3f424000 DT_SIZE_K(4)>;
			interrupts = <SPI2_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_FSPI_MODULE>;
			status = "disabled";
		};

		spi3: spi@3f425000 {
			compatible = "espressif,esp32-spi";
			reg = <0x3f425000 DT_SIZE_K(4)>;
			interrupts = <SPI3_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_HSPI_MODULE>;
			status = "disabled";
		};

		wdt0: watchdog@3f41f048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3f41f048 0x20>;
			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_TIMG0_MODULE>;
			status = "disabled";
		};

		wdt1: watchdog@3f42f048 {
			compatible = "espressif,esp32-watchdog";
			reg = <0x3f42f048 0x20>;
			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
			interrupt-parent = <&intc>;
			clocks = <&rtc ESP32_TIMG1_MODULE>;
			status = "disabled";
		};
	};

};