/*
 * Copyright (c) 2023 STMicroelectronics
 *
 * SPDX-License-Identifier: Apache-2.0
 */


#include <arm/armv8-m.dtsi>
#include <zephyr/dt-bindings/clock/stm32wba_clock.h>
#include <zephyr/dt-bindings/reset/stm32wba_reset.h>
#include <zephyr/dt-bindings/adc/stm32u5_adc.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/adc/adc.h>

#include <freq.h>

/ {
	chosen {
		zephyr,entropy = &rng;
		zephyr,flash-controller = &flash;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m33";
			reg = <0>;
			cpu-power-states = <&stop0 &stop1>;
			#address-cells = <1>;
			#size-cells = <1>;

			mpu: mpu@e000ed90 {
				compatible = "arm,armv8m-mpu";
				reg = <0xe000ed90 0x40>;
				arm,num-mpu-regions = <8>;
			};
		};

		power-states {
			stop0: state0 {
				compatible = "zephyr,power-state";
				power-state-name = "suspend-to-idle";
				substate-id = <1>;
				min-residency-us = <100>;
			};
			stop1: state1 {
				compatible = "zephyr,power-state";
				power-state-name = "suspend-to-idle";
				substate-id = <2>;
				min-residency-us = <500>;
			};
		};
	};

	sram0: memory@20000000 {
		compatible = "mmio-sram";
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "st,stm32wba-hse-clock";
			clock-frequency = <DT_FREQ_M(32)>;
			status = "disabled";
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_M(16)>;
			status = "disabled";
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "st,stm32-lse-clock";
			clock-frequency = <32768>;
			driving-capability = <1>;
			status = "disabled";
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <DT_FREQ_K(32)>;
			status = "disabled";
		};

		pll1: pll: pll {
			#clock-cells = <0>;
			compatible = "st,stm32wba-pll-clock";
			status = "disabled";
		};
	};

	soc {
		flash: flash-controller@40022000 {
			compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller";
			reg = <0x40022000 0x400>;
			interrupts = <6 0>;

			#address-cells = <1>;
			#size-cells = <1>;

			flash0: flash@8000000 {
				compatible = "st,stm32-nv-flash", "soc-nv-flash";

				write-block-size = <16>;
				erase-block-size = <8192>;
				/* maximum erase time(ms) for a 8K sector */
				max-erase-time = <5>;
			};
		};

		rcc: rcc@46020c00 {
			compatible = "st,stm32wba-rcc";
			clocks-controller;
			#clock-cells = <2>;
			reg = <0x46020c00 0x400>;

			rctl: reset-controller {
				compatible = "st,stm32-rcc-rctl";
				#reset-cells = <1>;
			};
		};

		exti: interrupt-controller@46022000 {
			compatible = "st,stm32g0-exti", "st,stm32-exti";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x46022000 0x400>;
			num-lines = <16>;
			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
				     <15 0>, <16 0>, <17 0>, <18 0>,
				     <19 0>, <20 0>, <21 0>, <22 0>,
				     <23 0>, <24 0>, <25 0>, <26 0>;
			interrupt-names = "line0", "line1", "line2", "line3",
					  "line4", "line5", "line6", "line7",
					  "line8", "line9", "line10", "line11",
					  "line12", "line13", "line14", "line15";
			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
				      <4 1>, <5 1>, <6 1>, <7 1>,
				      <8 1>, <9 1>, <10 1>, <11 1>,
				      <12 1>, <13 1>, <14 1>, <15 1>;
		};

		pinctrl: pin-controller@42020000 {
			compatible = "st,stm32-pinctrl";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x42020000 0x2000>;

			gpioa: gpio@42020000 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020000 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
			};

			gpiob: gpio@42020400 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020400 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
			};

			gpioc: gpio@42020800 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42020800 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
			};

			gpioh: gpio@42021c00 {
				compatible = "st,stm32-gpio";
				gpio-controller;
				#gpio-cells = <2>;
				reg = <0x42021c00 0x400>;
				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
			};
		};

		iwdg: watchdog@40003000 {
			compatible = "st,stm32-watchdog";
			reg = <0x40003000 0x400>;
			status = "disabled";
		};

		wwdg: watchdog@40002c00 {
			compatible = "st,stm32-window-watchdog";
			reg = <0x40002C00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
			interrupts = <0 7>;
			status = "disabled";
		};

		usart1: serial@40013800 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40013800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
			resets = <&rctl STM32_RESET(APB2, 14U)>;
			interrupts = <46 0>;
			status = "disabled";
		};

		usart2: serial@40004400 {
			compatible = "st,stm32-usart", "st,stm32-uart";
			reg = <0x40004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
			resets = <&rctl STM32_RESET(APB1L, 17U)>;
			interrupts = <47 0>;
			status = "disabled";
		};

		lpuart1: serial@46002400 {
			compatible = "st,stm32-lpuart", "st,stm32-uart";
			reg = <0x46002400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000040>;
			resets = <&rctl STM32_RESET(APB7, 6U)>;
			interrupts = <48 0>;
			status = "disabled";
		};

		spi1: spi@40013000 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40013000 0x400>;
			interrupts = <45 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
			status = "disabled";
		};

		spi3: spi@46002000 {
			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x46002000 0x400>;
			interrupts = <63 5>;
			clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000020>;
			status = "disabled";
		};

		i2c1: i2c@40005400 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40005400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
			interrupts = <43 0>, <44 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		i2c3: i2c@46002800 {
			compatible = "st,stm32-i2c-v2";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x46002800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000080>;
			interrupts = <54 0>, <55 0>;
			interrupt-names = "event", "error";
			status = "disabled";
		};

		timers1: timers@40012c00 {
			compatible = "st,stm32-timers";
			reg = <0x40012c00 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
			resets = <&rctl STM32_RESET(APB2, 11U)>;
			interrupts = <37 0>, <38 0>, <39 0>, <40 0>;
			interrupt-names = "brk", "up", "trgcom", "cc";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers2: timers@40000000 {
			compatible = "st,stm32-timers";
			reg = <0x40000000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
			resets = <&rctl STM32_RESET(APB1L, 0U)>;
			interrupts = <41 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers3: timers@40000400 {
			compatible = "st,stm32-timers";
			reg = <0x40000400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
			resets = <&rctl STM32_RESET(APB1L, 1U)>;
			interrupts = <42 0>;
			interrupt-names = "global";
			st,prescaler = <0>;
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers16: timers@40014400 {
			compatible = "st,stm32-timers";
			reg = <0x40014400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
			resets = <&rctl STM32_RESET(APB2, 17U)>;
			interrupts = <51 0>;
			interrupt-names = "global";
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		timers17: timers@40014800 {
			compatible = "st,stm32-timers";
			reg = <0x40014800 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
			resets = <&rctl STM32_RESET(APB2, 18U)>;
			interrupts = <52 0>;
			interrupt-names = "global";
			status = "disabled";

			counter {
				compatible = "st,stm32-counter";
				status = "disabled";
			};

			pwm {
				compatible = "st,stm32-pwm";
				status = "disabled";
				#pwm-cells = <3>;
			};
		};

		adc4: adc@46021000 {
			compatible = "st,stm32-adc";
			reg = <0x46021000 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB4 0x00000020>;
			interrupts = <65 0>;
			status = "disabled";
			#io-channel-cells = <1>;
			resolutions = <STM32_ADC_RES(12, 0x00)
				       STM32_ADC_RES(10, 0x01)
				       STM32_ADC_RES(8, 0x02)
				       STM32_ADC_RES(6, 0x03)>;
			sampling-times = <2 4 8 13 20 40 80 815>;
			num-sampling-time-common-channels = <2>;
			st,adc-clock-source = <ASYNC>;
			st,adc-sequencer = <NOT_FULLY_CONFIGURABLE>;
		};

		lptim1: timers@46004400 {
			compatible = "st,stm32-lptim";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x46004400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>;
			interrupts = <49 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		lptim2: timers@40009400 {
			compatible = "st,stm32-lptim";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40009400 0x400>;
			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
			interrupts = <50 1>;
			interrupt-names = "wakeup";
			status = "disabled";
		};

		rng: rng@520c0800 {
			compatible = "st,stm32-rng";
			reg = <0x520c0800 0x400>;
			interrupts = <59 0>;
			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00040000>,
				 <&rcc STM32_SRC_PLL1_Q RNG_SEL(3)>;
			nist-config = <0xf00d>;
			health-test-config = <0xaac7>;
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <4>;
};