)]}'
{
  "commit": "b9ae0d38b25387abe3471a082fa72b7d836aad4a",
  "tree": "4268f196884a6575948e10d15e97c81629c80f86",
  "parents": [
    "01c9f2bd9dc2b44b357fe10fb40ae8c7f93e18b6"
  ],
  "author": {
    "name": "Holt Sun",
    "email": "holt.sun@nxp.com",
    "time": "Thu Mar 19 16:20:24 2026 +0800"
  },
  "committer": {
    "name": "Benjamin Cabé",
    "email": "kartben@gmail.com",
    "time": "Sun May 17 10:40:43 2026 +0200"
  },
  "message": "soc: nxp: mcxc: add power management support\n\nAdd the MCXC power management implementation and wire it into the SoC\nbuild and Kconfig flow.\n\nDefault MCUX_LPTMR_TIMER to y when CONFIG_PM is enabled and the\nzephyr,system-timer chosen property points to an LPTMR node, so the\nLPTMR serves as the tickless system timer in PM use cases. (Zephyr\n4.5 stopped auto-defaulting MCUX_LPTMR_TIMER from the chosen property,\nmatching the convention later adopted for MCXW7XX.) When LPTMR is\nselected, override the SoC-side SysTick default, set\nSYS_CLOCK_TICKS_PER_SEC\u003d1024 and derive SYS_CLOCK_HW_CYCLES_PER_SEC\nfrom the chosen LPTMR\u0027s clock-frequency. Default WUC to y whenever PM\nand an LLWU node are enabled, so the LPTMR system timer driver can\nregister itself as a wakeup source through the WUC API.\n\nSet OSC0_CR.EREFSTEN once at PM init so the system OSC keeps running\nacross STOP modes. This keeps ERCLK32K alive as the LPTMR system-timer\nclock source while the CPU is suspended; without it the timer would\nlose its clock on STOP entry and never wake the CPU.\n\nSigned-off-by: Holt Sun \u003cholt.sun@nxp.com\u003e\n",
  "tree_diff": [
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      "old_path": "soc/nxp/mcx/mcxc/CMakeLists.txt",
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      "new_mode": 33188,
      "new_path": "soc/nxp/mcx/mcxc/CMakeLists.txt"
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      "new_path": "soc/nxp/mcx/mcxc/Kconfig"
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      "new_path": "soc/nxp/mcx/mcxc/Kconfig.defconfig"
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    {
      "type": "add",
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      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8550cafd2fbcfc264fc4c8852521a259dc0bcc06",
      "new_mode": 33188,
      "new_path": "soc/nxp/mcx/mcxc/power.c"
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}