/*
 * Copyright (c) 2021 BrainCo Inc.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <mem.h>
#include <gd/gd32f3x0/gd32f3x0.dtsi>

/ {
	soc {
		dac: dac@40007400 {
			compatible = "gd,gd32-dac";
			reg = <0x40007400 0x400>;
			clocks = <&cctl GD32_CLOCK_DAC>;
			resets = <&rctl GD32_RESET_DAC>;
			num-channels = <1>;
			status = "disabled";
			#io-channel-cells = <1>;
		};
	};
};