/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Copyright (C) 2021-2022, Intel Corporation
 *
 */

#include <arm64/armv8-a.dtsi>
#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
#include <zephyr/dt-bindings/clock/intel_socfpga_clock.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells= <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53";
			reg = <0>;
		};
	};

	gic: interrupt-controller@fffc1000 {
		compatible = "arm,gic";
		reg = <0xfffc1000 0x1000>,
		      <0xfffc2000 0x2000>;
		interrupt-controller;
		#interrupt-cells = <4>;
		status = "okay";
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 14 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 11 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>,
			     <GIC_PPI 10 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>;
	};

	sysmgr: sysmgr@ffd12000 {
		compatible = "syscon";
		reg = <0xffd12000 0x1000>;
	};

	clock: clock@ffd10000 {
		compatible = "intel,agilex-clock";
		reg = <0xffd10000 0x1000>;
		#clock-cells = <1>;
	};

	mem0: memory@10000000 {
		device_type = "memory";
		reg = <0x10000000 0x40000>;
	};

	uart0: uart@ffc02000 {
		compatible = "ns16550";
		reg-shift = <2>;
		reg = <0xffc02000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL
			      IRQ_DEFAULT_PRIORITY>;
		interrupt-names = "irq_0";
		clocks = <&clock INTEL_SOCFPGA_CLOCK_UART>;
		status = "disabled";
	};
};