/*
 * Copyright (c) 2018 Intel Corporation
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <device.h>
#include <init.h>
#include <kernel.h>

#include "soc.h"

#define UART_GPIO_CFG \
	(MCHP_GPIO_CTRL_PUD_NONE + MCHP_GPIO_CTRL_PWRG_VTR_IO +\
		MCHP_GPIO_CTRL_IDET_DISABLE + MCHP_GPIO_CTRL_BUFT_PUSHPULL +\
		MCHP_GPIO_CTRL_DIR_INPUT + MCHP_GPIO_CTRL_AOD_DIS +\
		MCHP_GPIO_CTRL_POL_NON_INVERT)

#define GPIO_CFG_OUT \
	(MCHP_GPIO_CTRL_PUD_NONE + MCHP_GPIO_CTRL_PWRG_VTR_IO +\
		MCHP_GPIO_CTRL_IDET_DISABLE + MCHP_GPIO_CTRL_BUFT_PUSHPULL +\
		MCHP_GPIO_CTRL_DIR_OUTPUT + MCHP_GPIO_CTRL_AOD_DIS +\
		MCHP_GPIO_CTRL_POL_NON_INVERT)

static int board_pinmux_init(struct device *dev)
{
	ARG_UNUSED(dev);

	/* See table 2-4 from the Data sheet*/
#ifdef CONFIG_UART_NS16550_PORT_0
	/* Set muxing, for UART 0 and power up */
	mchp_pcr_periph_slp_ctrl(PCR_UART0, MCHP_PCR_SLEEP_DIS);

	UART0_REGS->CFG_SEL = (MCHP_UART_LD_CFG_INTCLK +
		MCHP_UART_LD_CFG_RESET_SYS + MCHP_UART_LD_CFG_NO_INVERT);
	UART0_REGS->ACTV = MCHP_UART_LD_ACTIVATE;

	GPIO_CTRL_REGS->CTRL_0104 = UART_GPIO_CFG + MCHP_GPIO_CTRL_MUX_F1;
	GPIO_CTRL_REGS->CTRL_0105 = UART_GPIO_CFG + MCHP_GPIO_CTRL_MUX_F1;
#endif

#ifdef CONFIG_UART_NS16550_PORT_1
	/* Set muxing, for UART 1 and power up */
	mchp_pcr_periph_slp_ctrl(PCR_UART1, MCHP_PCR_SLEEP_DIS);

	UART1_REGS->CFG_SEL = (MCHP_UART_LD_CFG_INTCLK +
		MCHP_UART_LD_CFG_RESET_SYS + MCHP_UART_LD_CFG_NO_INVERT);
	UART1_REGS->ACTV = MCHP_UART_LD_ACTIVATE;

	GPIO_CTRL_REGS->CTRL_0170 = UART_GPIO_CFG + MCHP_GPIO_CTRL_MUX_F1;
	GPIO_CTRL_REGS->CTRL_0171 = UART_GPIO_CFG + MCHP_GPIO_CTRL_MUX_F1;
#endif
	return 0;
}

SYS_INIT(board_pinmux_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);