/*
 * Copyright (c) 2018, Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include "skeleton.dtsi"

#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "snps,arcem";
			reg = <1>;
		};

		intc: arcv2-intc {
			compatible = "snps,arcv2-intc";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	iccm0: iccm@20000000 {
		device_type = "memory";
		compatible = "arc,iccm";
		reg = <0x20000000 0x40000>;
	};

	dccm0: dccm@80000000 {
		device_type = "memory";
		compatible = "arc,dccm";
		reg = <0x80000000 0x20000>;
	};


	sram: memory@30000000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x30000000 0x20000>;
	};

	flash0: flash@0 {
		compatible = "soc-nv-flash";
		reg = <0x0 0x40000>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;


		uart0: uart@80014000 {
			compatible = "ns16550";
			clock-frequency = <16000000>;
			reg = <0x80014000 0x100>;
			label = "UART_0";
			interrupts = <86 0>;
			interrupt-parent = <&intc>;
			dlf = <0x01>;
		};

		uart1: uart@80014100 {
			compatible = "ns16550";
			clock-frequency = <16000000>;
			reg = <0x80014100 0x100>;
			label = "UART_1";
			interrupts = <87 0>;
			interrupt-parent = <&intc>;

		};

		uart2: uart@80014200 {
			compatible = "ns16550";
			clock-frequency = <16000000>;
			reg = <0x80014200 0x1000>;
			label = "UART_2";
			interrupts = <88 0>;
			interrupt-parent = <&intc>;

		};

		uart3: uart@80014300 {
			compatible = "ns16550";
			clock-frequency = <144000000>;
			reg = <0x80014300 0x100>;
			label = "UART_3";
			interrupts = <89 0>;
			interrupt-parent = <&intc>;

		};

		gpio8b0: gpio@80017800 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017800 0x100>;
			interrupts = <54 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_8B_0";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio8b1: gpio@80017900 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017900 0x100>;
			interrupts = <55 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_8B_1";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio8b2: gpio@80017a00 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017a00 0x100>;
			interrupts = <56 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_8B_2";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio8b3: gpio@80017b00 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017b00 0x100>;
			interrupts = <57 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_8B_3";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio4b0: gpio@80017c00 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017c00 0x100>;
			interrupts = <19 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_4B_0";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio4b1: gpio@80017d00 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017d00 0x100>;
			interrupts = <52 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_4B_1";

			gpio-controller;
			#gpio-cells = <2>;
		};

		gpio4b2: gpio@80017e00 {
			compatible = "intel,qmsi-ss-gpio";
			reg = <0x80017e00 0x100>;
			interrupts = <53 1>;
			interrupt-parent = <&intc>;
			label = "GPIO_4B_2";

			gpio-controller;
			#gpio-cells = <2>;
		};


		i2c0: i2c@80012000 {
			compatible = "intel,qmsi-ss-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80012000 0x100>;
			interrupts = <58 1>, <61 1>, <60 1>, <59 1>;
			interrupt-names = "error", "stop", "tx", "rx";
			interrupt-parent = <&intc>;
			label = "I2C_0";

			status = "disabled";
		};

		i2c1: i2c@80012100 {
			compatible = "intel,qmsi-ss-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80012100 0x100>;
			interrupts = <62 1>, <65 1>, <64 1>, <63 1>;
			interrupt-names = "error", "stop", "tx", "rx";
			interrupt-parent = <&intc>;
			label = "I2C_1";

			status = "disabled";
		};

		i2c2: i2c@80012200 {
			compatible = "intel,qmsi-ss-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80012200 0x100>;
			interrupts = <66 1>, <69 1>, <68 1>, <67 1>;
			interrupt-names = "error", "stop", "tx", "rx";
			interrupt-parent = <&intc>;
			label = "I2C_2";

			status = "disabled";
		};

		spi0: spi@80010000 {
			compatible = "snps,designware-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80010000 0x100>;
			interrupts = <70 2>, <71 2>, <72 2>;
			interrupt-names = "err-int", "rx-avail", "tx-req";
			interrupt-parent = <&intc>;
			label = "SPI_0";
			status = "disabled";
		};

		spi1: spi@80010100 {
			compatible = "snps,designware-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80010100 0x100>;
			interrupts = <74 2>, <75 2>, <76 2>;
			interrupt-names = "err-int", "rx-avail", "tx-req";
			interrupt-parent = <&intc>;
			label = "SPI_1";
			status = "disabled";
		};

		spi2: spi@80010200 {
			compatible = "snps,designware-spi";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x80010200 0x100>;
			interrupts = <78 2>, <79 2>, <80 2>;
			interrupt-names = "err-int", "rx-avail", "tx-req";
			interrupt-parent = <&intc>;
			label = "SPI_2";
			status = "disabled";
		};

	};
};