| commit | c959b58bf15659628d2b64b1b38f5a89348d4db4 | [log] [tgz] |
|---|---|---|
| author | Thomas Stranger <thomas.stranger@outlook.com> | Tue Jun 28 20:58:05 2022 +0200 |
| committer | Carles Cufí <carles.cufi@nordicsemi.no> | Mon Jul 04 16:41:24 2022 +0200 |
| tree | ee286102f145838ff401df5112a7fb06b34f108a | |
| parent | 2801c9969add29d4a632f9d16af45ff2f120d572 [diff] |
drivers/clock_control: stm32 common: enable PLL_P/Q and set PLL_P div This commit configures the PLL_P divider for SOCs compatible to the stm32_ll_common driver in case a value was defined via a dts property. Additionally, in case the divider value is defined in the device tree, the respective pll output is enabled during initialization in set_up_plls(). Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>