dts/arm/nxp/nxp_kl25z.dtsi

#include "armv6-m.dtsi"
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/i2c/i2c.h>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-m0+";
			reg = <0>;
		};
	};

	sram0: memory@1FFFF000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0x1FFFF000 0x4000>;
	};

	soc {
		flash0: flash@0 {
			reg = <0 0x20000>;
		};

		i2c0: i2c@40066000 {
			compatible = "nxp,kinetis-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40066000 0x1000>;
			interrupts = <8 0>;
			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
			label = "I2C_0";
			status = "disabled";
		};

		i2c1: i2c@40067000 {
			compatible = "nxp,kinetis-i2c";
			clock-frequency = <I2C_BITRATE_STANDARD>;
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x40067000 0x1000>;
			interrupts = <9 0>;
			clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
			label = "I2C_1";
			status = "disabled";
		};

		sim: sim@40047000 {
			compatible = "nxp,kinetis-sim";
			reg = <0x40047000 0x1060>;
			label = "SIM";

			clk-divider-core = <1>;
			clk-divider-bus = <2>;
			clk-divider-flexbus = <3>;
			clk-divider-flash = <5>;

			clock-controller;
			#clocks-cells = <3>;
		};

		uart0: uart@4006A000 {
			compatible = "nxp,kinetis-lpsci";
			reg = <0x4006A000 0xc>;
			interrupts = <12 0>;
			clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
			label = "UART_0";

			status = "disabled";
		};

		adc0: adc@4003b000{
			compatible = "nxp,kinetis-adc16";
			reg = <0x4003b000 0x70>;
			interrupts = <15 0>;
			label = "ADC_0";
			status = "disabled";
		};
	};
};

&nvic {
	arm,num-irq-priority-bits = <2>;
};